CN115878343A

CN115878343A - Inter-process communication method and related device

Info

Publication number: CN115878343A
Application number: CN202111155635.5A
Authority: CN
Inventors: 缪晴朗; 蔡卫光
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-09-29
Filing date: 2021-09-29
Publication date: 2023-03-31
Also published as: WO2023051591A1

Abstract

The application discloses an inter-process communication method which is applied to electronic equipment running a plurality of processes. The method comprises the following steps: acquiring a first instruction for requesting to acquire an address of a shared memory; returning a first address to the first process according to the first instruction, and adding the first address to a filter table for storing addresses of the shared memory which can be accessed by the first process; acquiring a second instruction from the first process, wherein the second instruction comprises a first address, and the second instruction is used for requesting to use a storage space corresponding to the first address; triggering and inquiring a filter table based on the first address in the second instruction as the address of the shared memory, and executing the second instruction according to the first address in the filter table; after executing the second instruction, the first address is deleted in the filter table. Based on the method, when the software has errors, the process in communication can not access the memory segment used by other processes, so that the system downtime caused by the damage of data in the shared memory is avoided.

Description

Inter-process communication method and related device

Technical Field

The present application relates to the field of computer technologies, and in particular, to an inter-process communication method and a related apparatus.

Background

In recent years, with the improvement of the quality of life and the leap of the technical level of people, the vehicle-mounted market has never been provided with opportunities to be intelligent. In an intelligent driving scene, a large amount of inter-process communication exists, for example, a sensor process transmits an image to different processing processes, and the processing processes execute corresponding identification processing and then send control signals to corresponding components in a vehicle. Practical application shows that the intelligent driving scene has high requirements on efficiency and safety of inter-process communication, the efficiency influences the speed of a vehicle for reacting to emergency, and the safety is directly closely related to the life safety of passengers.

In the conventional method, inter-process communication is generally implemented based on a socket (socket) technology and a Message Queue (Message Queue) technology. However, both the socket technology and the Message Queue technology involve copying of data, and communication efficiency is poor. Therefore, at present, a shared memory mode is mainly adopted to realize interprocess communication. The communication is carried out based on a mode of sharing the memory, data copying is not needed, and the communication efficiency is high.

In the scenario of communication through a shared memory, multiple processes in communication access different memory segments in the shared memory at any time. However, when an error occurs during the running of the software, one process in communication may access a memory segment being used by another process, which may destroy data in the shared memory, thereby causing a system downtime. In an intelligent driving scenario, personal safety may be jeopardized once this situation occurs.

Disclosure of Invention

The embodiment of the application provides an inter-process communication method, which can ensure that when software has an error, a process in communication cannot access a memory segment used by other processes, so that the phenomenon that a system is down due to the fact that data in a shared memory is damaged is avoided, and normal operation of the system is ensured.

A first aspect of the present application provides an inter-process communication method, which is applied to an electronic device running multiple processes, for example, a wireless electronic device in an intelligent driving scenario. The method comprises the following steps: the processor acquires a first instruction from a first process, wherein the first instruction is used for requesting to acquire an address of the shared memory so as to facilitate the first process to write data into the shared memory or read data in the shared memory. The shared memory is used for interprocess communication. In an intelligent driving scene, a first process is a sensor process for example and is responsible for acquiring sensor data and sending the sensor data to a processing process; the first process may also be a processing process, and is responsible for receiving sensor data transmitted by the shared memory, and executing corresponding processing operations according to the sensor data.

And the processor returns a first address to the first process according to the first instruction, and adds the first address to a filter table corresponding to the first process. The first address may be an address range, and is used to indicate an address segment corresponding to a memory segment in the shared memory. And the memory segment corresponding to the first address is a memory used for the inter-process communication of the first process. The filtering table is used for storing addresses of the shared memory which can be accessed by the first process, and the addresses recorded in the filtering table are all the addresses in the shared memory.

The processor acquires a second instruction from the first process, wherein the second instruction comprises the first address, and the second instruction is used for requesting to use the storage space corresponding to the first address so as to realize inter-process communication based on the storage space corresponding to the first address.

And the processor triggers and inquires the filter table based on the fact that the first address in the second instruction is the address of the shared memory, and executes the second instruction according to the fact that the first address is located in the filter table. That is, when the processor obtains an instruction for accessing an address and determines that the address is an address in the shared memory, the processor triggers a query of the filter table to determine whether the address is located in the filter table. If the address is in the filter table, then the representative process has the right to access the address; if the address is not located in the filter table, the delegate process does not have access to the address.

And after executing the second instruction, the processor deletes the first address in the filter table, so that the first process no longer has the right to access the first address.

In the scheme, a first process needing communication based on the shared memory obtains the address of the shared memory through an instruction, and the instruction triggers the obtained address of the shared memory to be added into a filter table; when the first process accesses the address of the shared memory, triggering and inquiring the filter table to determine whether the first process has the authority of accessing the shared memory. And after the first process successfully accesses the shared memory, releasing the access authority of the first process in the filter table, thereby ensuring that the process cannot tread down the shared memory used by another process due to software errors or attacks. Based on the scheme, when software is wrong or is attacked maliciously, the process in communication can not access the memory segment used by other processes, so that the phenomenon that the system is down due to the fact that data in the shared memory is damaged is avoided, and normal operation of the system is guaranteed.

In a possible implementation manner, the first process is a sender process, the second instruction further includes first data, the second instruction is used to instruct to write the first data into a storage space corresponding to the first address, and the first data is data to be transmitted to a second process. The process of the processor executing the second instruction comprises: and writing the first data into the storage space corresponding to the first address by the processor.

In a possible implementation manner, the first process is a receiver process, the second instruction is used to instruct to read second data in a storage space corresponding to the first address, and the second data is data transmitted by the second process to the first process. The process of the processor executing the second instruction comprises: and the processor reads second data in the storage space corresponding to the first address and returns the second data to the first process.

In a possible implementation manner, when a bug occurs or a malicious attack is applied to a first process, a processor acquires a third instruction from the first process, where the third instruction includes a second address, and the third instruction is used to request to use a storage space corresponding to the second address. The second address is an address in the shared memory and is not located in a filter table. That is, the processor may be one that does not trigger the addition of the second address to the filter table; the processor may also delete the second address from the filter table after the first process loses access to the second address.

And the processor triggers and inquires the filter table based on the second address in the third instruction as the address of the shared memory, and refuses to execute the third instruction according to the condition that the second address is not in the filter table.

In the scheme, when the second address requested to be accessed by the first process belongs to an address in a shared memory and is not located in the filter table, the processor can refuse to execute an instruction of the first process for requesting to access the second address, so that the first process cannot use a storage space corresponding to the second address, and the phenomenon that the first process tramples a storage space used by other processes is avoided.

In a possible implementation manner, after the shared memory is allocated to the first process or the first instruction from the first process is acquired, the processor adds a mark in a page table entry corresponding to the first process. The flag is used to indicate that the first address is an address used for inter-process communication, the page table entry is used to indicate a mapping relationship between the first address and a physical address corresponding to the first address, and the first address is a virtual address.

After obtaining the second instruction, the processor may search the page table entry based on the first address in the second instruction, and determine that the first address in the second instruction is an address of the shared memory according to a flag in the page table entry.

In the scheme, the marks are added in the page table entry to indicate the addresses belonging to the shared memory, so that the processor can identify that the first address in the second instruction is the address of the shared memory, and the feasibility of the scheme is improved.

In a possible implementation manner, after the processor allocates the shared memory to the first process, the first instruction generated by the first process includes an identifier of the shared memory, and the first instruction is used to request to acquire an address of the shared memory.

And the processor acquires the descriptor corresponding to the shared memory according to the identifier in the first instruction. The descriptor may be created by the processor after the shared memory is allocated to the first process, and the descriptor is used to record the usage of the shared memory. That is, after the processor allocates the shared memory to two processes that need to communicate each time, a descriptor is established for the allocated shared memory to record the usage of the shared memory.

And the processor determines the first address according to the content of the descriptor and returns the first address to the first process, wherein the storage space corresponding to the first address is a storage space to be written in or read from the shared memory.

According to the scheme, the descriptor is adopted to record the use condition of the shared memory in real time, so that the processor can acquire the use condition of the shared memory when acquiring the instruction for requesting to acquire the address in the shared memory, and the effective address of the memory segment is returned to the process.

In one possible implementation, the processor may generate a descriptor table for a first process when the first process first establishes communication with other processes. When a processor acquires a first instruction comprising an identifier of a shared memory, the processor acquires an address of a descriptor corresponding to the identifier in a descriptor table corresponding to a first process according to the identifier in the first instruction, wherein the descriptor table is used for storing addresses of one or more descriptors corresponding to the first process. The processor acquires the descriptor according to the address of the descriptor.

In the scheme, the descriptor table is used for recording the addresses of the descriptors, so that a plurality of descriptors corresponding to the same process can be effectively managed, and the realizability of the scheme is ensured.

In a possible implementation manner, the shared memory allocated by the processor to the first process includes a plurality of memory blocks, and the plurality of memory blocks form a circular queue for reading and writing by the process. The descriptor corresponding to the shared memory records and manages the state of each memory block in the plurality of memory blocks. Specifically, the descriptor includes a write pointer and a read pointer, where the write pointer is used to indicate a location, in the ring queue, of a memory block to be written in the multiple memory blocks, and the read pointer is used to indicate a location, in the ring queue, of a memory block to be read in the multiple memory blocks. Based on the write pointer and the read pointer in the descriptor, the processor may quickly determine the address of the memory block for writing data and the address of the memory block for reading data.

In the scheme, the multiple memory blocks in the shared memory are organized into the ring queue, and the state of the memory blocks in the ring queue is recorded by the descriptor, so that the processes of the two parties in communication can work asynchronously, namely, the process of the sending party and the process of the receiving party access different memory blocks in the shared memory at the same time, and the communication efficiency is improved.

In addition, because a plurality of memory blocks in the shared memory are organized into a ring queue, the process of the sender can write data into the ring queue circularly, thereby realizing the cyclic utilization of the shared memory and saving the communication overhead.

In a possible implementation manner, after the second instruction is executed, the processor updates the write pointer in the descriptor to update a position of a memory block to be written in the plurality of memory blocks in the ring queue;

or after executing the second instruction, the processor updates the read pointer in the descriptor to update the position of the memory block to be read in the circular queue among the plurality of memory blocks.

In one possible implementation manner, before the first process establishes communication with other processes, the processor acquires a fourth instruction from the first process, where the fourth instruction is used for requesting allocation of a memory for inter-process communication. And the processor allocates the shared memory for the first process according to the fourth instruction, and returns the identifier of the shared memory to the first process.

In a possible implementation manner, after acquiring a fourth instruction from the first process, the processor further generates a descriptor corresponding to the shared memory according to the fourth instruction, and adds an address of the descriptor to a descriptor table corresponding to the first process. After the processor allocates the shared memory to the first process according to the fourth instruction, the processor may further add the identifier of the shared memory to the descriptor table to establish a correspondence between the address of the descriptor and the identifier of the shared memory, so that a subsequent processor can determine a corresponding descriptor according to the identifier of the shared memory.

In a possible implementation manner, after the second instruction is executed, the processor acquires a fifth instruction from the first process, where the fifth instruction is used to indicate that the storage space corresponding to the first address is used up. And the processor deletes the first address in the filter table according to the fifth instruction.

The processor is triggered by the second instruction sent by the first process to cancel the access authority of the first process to the shared memory, so that the behavior of the processes accessing the shared memory can be controlled, the processes in communication cannot access the memory segments used by other processes, and the phenomenon that the system is down due to the fact that data in the shared memory is damaged is avoided.

A second aspect of the present application provides an electronic device, including an obtaining unit, a processing unit, and a sending unit; the acquiring unit is used for acquiring a first instruction from a first process, wherein the first instruction is used for requesting to acquire an address of a shared memory, and the shared memory is used for interprocess communication; the sending unit is configured to return a first address to the first process according to the first instruction, and add the first address to a filter table corresponding to the first process, where the first address is an address in the shared memory, and the filter table is used to store an address of the shared memory that can be accessed by the first process; the obtaining unit is further configured to obtain a second instruction from the first process, where the second instruction includes the first address, and the second instruction is used to request to use a storage space corresponding to the first address; the processing unit is configured to trigger query of the filter table based on that a first address in the second instruction is an address of a shared memory, and execute the second instruction according to that the first address is located in the filter table; the processing unit is further configured to delete the first address in the filter table after the second instruction is executed.

In a possible implementation manner, the second instruction further includes first data, where the second instruction is used to instruct to write the first data into a storage space corresponding to the first address, and the first data is data to be transmitted to a second process; the processing unit is specifically configured to write the first data into the storage space corresponding to the first address.

In a possible implementation manner, the second instruction is used to instruct to read second data in a storage space corresponding to the first address, where the second data is data transmitted from a second process to the first process; the processing unit is specifically configured to read second data in the storage space corresponding to the first address, and return the second data to the first process.

In a possible implementation manner, the obtaining unit is further configured to obtain a third instruction from the first process, where the third instruction includes a second address, the third instruction is configured to request to use a storage space corresponding to the second address, and the second address is an address in the shared memory; the processing unit is specifically configured to trigger query of the filter table based on that a second address in the third instruction is an address of a shared memory, and refuse to execute the third instruction according to that the second address is not located in the filter table.

In a possible implementation manner, the processing unit is further configured to add a mark to a page table entry corresponding to the first process, where the mark is used to indicate that the first address is an address used for inter-process communication, the page table entry is used to indicate a mapping relationship between the first address and a physical address corresponding to the first address, and the first address is a virtual address; the processing unit is specifically configured to: searching the page table entry based on the first address in the second instruction; and determining that the first address in the second instruction is the address of the shared memory according to the mark in the page table entry.

In a possible implementation manner, the first instruction includes an identifier of the shared memory; the processing unit is specifically configured to obtain a descriptor according to the identifier, where the descriptor is used to record a use condition of the shared memory; the sending unit is specifically configured to determine the first address according to the descriptor, and return the first address to the first process, where a storage space corresponding to the first address is a storage space to be written in or read from the shared memory.

In a possible implementation manner, the processing unit is specifically configured to: according to the identification, obtaining the address of the descriptor corresponding to the identification in a descriptor table corresponding to a first process, wherein the descriptor table is used for storing the addresses of one or more descriptors corresponding to the first process; and acquiring the descriptor according to the address of the descriptor.

In a possible implementation manner, the shared memory includes a plurality of memory blocks, and the plurality of memory blocks form a ring queue for reading and writing by a process; the descriptor includes a write pointer and a read pointer, where the write pointer is used to indicate a location of a memory block to be written in the plurality of memory blocks in the circular queue, and the read pointer is used to indicate a location of a memory block to be read in the plurality of memory blocks in the circular queue.

In a possible implementation manner, the processing unit is specifically configured to: after the second instruction is executed, updating the write pointer in the descriptor to update a position of a memory block to be written in the plurality of memory blocks in the circular queue; or after the second instruction is executed, the read pointer in the descriptor is updated to update the position of the memory block to be read in the circular queue among the plurality of memory blocks.

In a possible implementation manner, the obtaining unit is further configured to obtain a fourth instruction from the first process, where the fourth instruction is used to request allocation of a memory for inter-process communication; the processing unit is further configured to allocate the shared memory to the first process according to the fourth instruction, and return an identifier of the shared memory to the first process.

In a possible implementation manner, the processing unit is further configured to generate a descriptor corresponding to the shared memory according to the fourth instruction, and add an address of the descriptor to a descriptor table corresponding to the first process.

In a possible implementation manner, the obtaining unit is further configured to obtain a fifth instruction from the first process, where the fifth instruction is used to indicate that the storage space corresponding to the first address is used up; and the processing unit is further configured to delete the first address in the filter table according to the fifth instruction.

A third aspect of the present application provides an electronic device, comprising: a memory and a processor; the memory stores code, the processor is configured to execute the code, and when executed, the electronic device performs the method as any one of the implementation manners of the first aspect.

The present application fourth aspect provides an intelligent vehicle, which includes: a memory and a processor; the memory stores code, and the processor is configured to execute the code, and when executed, the smart car performs the method as any one of the implementation manners in the first aspect.

A fifth aspect of the present application provides a computer-readable storage medium having stored thereon a computer program which, when run on a computer, causes the computer to perform a method as implemented in any one of the first or second aspects.

A sixth aspect of the present application provides a computer program product which, when run on a computer, causes the computer to perform a method as implemented in any one of the first or second aspects.

A seventh aspect of the present application provides a chip comprising one or more processors. Part or all of the processor is used for reading and executing the computer program stored in the memory to execute the method in any possible implementation mode of any one of the aspects.

Optionally, the chip may include a memory, and the memory and the processor may be connected to the memory through a circuit or a wire. Optionally, the chip further comprises a communication interface, and the processor is connected to the communication interface. The communication interface is used for receiving data and/or information needing to be processed, the processor acquires the data and/or information from the communication interface, processes the data and/or information, and outputs a processing result through the communication interface. The communication interface may be an input output interface. The method provided by the application can be realized by one chip or by cooperation of a plurality of chips.

Drawings

Fig. 1 is a schematic communication diagram based on a socket technology according to an embodiment of the present application;

fig. 2 is a schematic communication diagram based on a Message Queue technology according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of a vehicle 100 according to an embodiment of the present disclosure;

FIG. 4 is a schematic structural diagram of a computer system 101 in a vehicle according to an embodiment of the present disclosure;

fig. 5 is a flowchart illustrating an interprocess communication method 500 according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a page table entry according to an embodiment of the present application;

FIG. 7 is a diagram illustrating a descriptor structure according to an embodiment of the present application;

fig. 8 is a flowchart illustrating an interprocess communication method 800 according to an embodiment of the present application;

fig. 9 is a schematic diagram illustrating a state change of a memory block in a shared memory according to an embodiment of the present application;

FIG. 10 is a system architecture diagram of interprocess communication according to an embodiment of the present application;

FIG. 11A is a block diagram of a descriptor table according to an embodiment of the present disclosure;

FIG. 11B is a block diagram of a descriptor according to an embodiment of the present application;

fig. 12 is a schematic diagram of a system architecture in an intelligent driving scenario according to an embodiment of the present application;

fig. 13 is a flowchart illustrating an inter-process communication method 1300 according to an embodiment of the present application;

fig. 14 is a schematic structural diagram of an electronic device 1400 according to an embodiment of the present disclosure;

fig. 15 is a schematic structural diagram of a computer-readable storage medium 1500 according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Embodiments of the present application are described below with reference to the accompanying drawings. As can be known to those skilled in the art, with the development of technology and the emergence of new scenes, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

In recent years, with the improvement of the quality of life and the leap of the technical level of people, the vehicle-mounted market has never been provided with opportunities to be intelligent. In an intelligent driving scene, a large amount of inter-process communication exists, for example, a sensor process transmits an image to different processing processes, and the processing processes send control signals to corresponding components in a vehicle after corresponding identification processing is executed. Practical application shows that the intelligent driving scene has high requirements on efficiency and safety of inter-process communication, the efficiency influences the speed of a vehicle for reacting to emergency, and the safety is directly closely related to the life safety of passengers.

Furthermore, in smart driving scenarios, the two processes that need to communicate are typically located on different processors. Thus, interprocess communication in a smart driving scenario is often referred to as inter-core communication.

In the conventional method, inter-process communication is generally implemented based on a socket (socket) technology and a Message Queue (Message Queue) technology.

The socket technology is a common mode of process communication in a network, and can also be applied to interprocess communication in the same computer system. As shown in fig. 1, fig. 1 is a schematic communication diagram based on a socket technology according to an embodiment of the present application. For a Transmission Control Protocol (TCP) client and a TCP server to be communicated, the TCP client and the TCP server respectively establish a socket object.

The TCP server does not locate the socket of a specific client but is in a listening state all the time. The socket of the TCP client needs to describe the socket of a server to which the TCP client is connected and provides an address and a port number; then, the TCP client makes a connection request to the socket of the TCP server. After receiving the connection request sent by the socket of the TCP client, the socket of the TCP server responds to the request of the socket of the TCP client, establishes a new thread and sends the description of the socket of the TCP server to the client. Once the TCP client confirms the description returned by the TCP server, the connection is established on-the-fly. And the socket of the TCP server side is continuously in a monitoring state, and the connection requests of the sockets of other clients are continuously received.

Message Queue is one of the more common communication technologies in Linux. The Message Queue technology establishes a Message Queue in a kernel, copies data of a Message buffer area of a process in a user mode space to a kernel mode, and copies the data to a Message buffer area of another process, thereby completing communication between the processes. As shown in fig. 2, fig. 2 is a schematic communication diagram based on a Message Queue technology according to an embodiment of the present application.

However, both the socket technology and the Message Queue technology involve copying of data in the communication process, and the communication efficiency is low. Therefore, at present, a shared memory mode is mainly adopted to realize interprocess communication. The communication is carried out based on a mode of sharing the memory, data copying is not needed, and the communication efficiency is high.

Shared memory is currently the most efficient way of interprocess communication. Under the condition of communication based on the shared memory, the same physical address in the memory is mapped to address spaces of different processes, and two processes in communication asynchronously read and write the same physical address in the memory, so that copy-free communication of data is realized.

Generally, in a scenario where communication is performed via a shared memory, multiple processes in communication access different memory segments in the shared memory at any time. However, when software has an error during its operation (for example, the software has a BUG), one of the communicating processes may access a memory segment being used by another process, which may destroy data in the shared memory, thereby causing a system downtime. In an intelligent driving scenario, personal safety may be jeopardized once such a situation occurs.

In addition, in most interprocess communication services, after data sent by a sender process is received, a receiver process performs data validity check. If the data is legal, the receiver process processes the data again. However, in the process of processing data by the receiver process, if the sender modifies the data again, the receiver process cannot check the validity of the data any more, thereby introducing security holes. In an intelligent driving scenario, an attacker can attack a sender process by checking a Time of use (TOCTTOU) attack. After the process of the sender is controlled by the attack, the process of the sender can send legal data firstly; the receiver process will begin processing after the data is verified to be legitimate. At this point, the sender process may attack by modifying the content of the data.

In view of this, an embodiment of the present application provides an inter-process communication method, where a process that needs to perform communication based on a shared memory obtains an address of the shared memory through an instruction, and the instruction triggers the obtained address of the shared memory to be added to a filter table; when the process accesses the address of the shared memory, triggering and inquiring the filter table to determine whether the process has the authority of accessing the shared memory. And after the process successfully accesses the shared memory, the access right of the process is released in the filter table, so that the process is prevented from trampling the shared memory used by another process due to software errors or attacks.

Based on the scheme of the embodiment, when software is in error or is attacked maliciously, the process in communication cannot access the memory segment in use by other processes, so that the phenomenon that the system is down due to the fact that data in the shared memory is damaged is avoided, and normal operation of the system is guaranteed.

Specifically, the interprocess communication method provided by the embodiment of the application can be applied to electronic equipment. Illustratively, the electronic device may be, for example, a wireless electronic device in smart driving, a server, a smart phone (mobile phone), a Personal Computer (PC), a notebook computer, a tablet computer, a smart television, a Mobile Internet Device (MID), a wearable device, a Virtual Reality (VR) device, an Augmented Reality (AR) device, a wireless electronic device in industrial control (industrial control), a wireless electronic device in remote surgery (remote medical supply), a wireless electronic device in smart grid (smart grid), a wireless electronic device in transportation safety, a wireless electronic device in smart city (smart city), a wireless electronic device in smart home (smart home), and the like.

For convenience of description, the method provided by the embodiment of the present application will be described below by taking the application of the method provided by the embodiment of the present application to a wireless electronic device in intelligent driving as an example.

For facilitating understanding of the present solution, in the embodiment of the present application, first, a structure of a vehicle in an intelligent driving scenario provided by the present application is described with reference to fig. 3. Referring to fig. 3, fig. 3 is a schematic structural diagram of a vehicle 100 according to an embodiment of the present disclosure.

In one embodiment, the vehicle 100 may be configured in a fully or partially autonomous driving mode. For example, the vehicle 100 may control itself while in the autonomous driving mode, and may determine a current state of the vehicle and its surroundings by human operation, determine a possible behavior of at least one other vehicle in the surroundings, and determine a confidence level corresponding to a likelihood that the other vehicle performs the possible behavior, controlling the vehicle 100 based on the determined information. While the vehicle 100 is in the autonomous driving mode, the vehicle 100 may be placed into operation without human interaction.

The vehicle 100 may include various subsystems such as a travel system 102, a sensor system 104, a control system 106, one or more peripherals 108, as well as a power supply 110, a computer system 112, and a user interface 116. Alternatively, the vehicle 100 may include more or fewer subsystems, and each subsystem may include multiple elements, e.g., each subsystem includes multiple ECUs. In addition, each of the sub-systems and elements of the vehicle 100 may be interconnected by wire or wirelessly.

The travel system 102 may include components that provide powered motion to the vehicle 100. In one embodiment, the propulsion system 102 may include an engine 118, an energy source 119, a transmission 120, and wheels/tires 121. The engine 118 may be an internal combustion engine, an electric motor, an air compression engine, or other types of engine combinations, such as a hybrid engine consisting of a gasoline engine and an electric motor, a hybrid engine consisting of an internal combustion engine and an air compression engine. The engine 118 converts the energy source 119 into mechanical energy.

Examples of energy sources 119 include gasoline, diesel, other petroleum-based fuels, propane, other compressed gas-based fuels, ethanol, solar panels, batteries, and other sources of electrical power. The energy source 119 may also provide energy to other systems of the vehicle 100.

The transmission 120 may transmit mechanical power from the engine 118 to the wheels 121. The transmission 120 may include a gearbox, a differential, and a drive shaft. In one embodiment, the transmission 120 may also include other devices, such as a clutch. Wherein the drive shaft may comprise one or more shafts that may be coupled to one or more wheels 121.

The sensor system 104 may include a number of sensors that sense information about the environment surrounding the vehicle 100. For example, the sensor system 104 may include a positioning system 122 (which may be a GPS system, a beidou system, or other positioning system), an Inertial Measurement Unit (IMU) 124, a radar 126, a laser range finder 128, and a camera 130. The sensor system 104 may also include sensors of internal systems of the monitored vehicle 100 (e.g., an in-vehicle air quality monitor, a fuel gauge, an oil temperature gauge, etc.). Sensor data from one or more of these sensors may be used to detect the object and its corresponding characteristics (position, shape, orientation, velocity, etc.). Such detection and identification is a critical function of the safe operation of the autonomous vehicle 100.

The positioning system 122 may be used to estimate the geographic location of the vehicle 100. The IMU 124 is used to sense position and orientation changes of the vehicle 100 based on inertial acceleration. In one embodiment, IMU 124 may be a combination of an accelerometer and a gyroscope.

The radar 126 may utilize radio signals to sense objects within the surrounding environment of the vehicle 100. In some embodiments, in addition to sensing objects, radar 126 may also be used to sense the speed and/or heading of an object.

The laser rangefinder 128 may utilize laser light to sense objects in the environment in which the vehicle 100 is located. In some embodiments, the laser rangefinder 128 may include one or more laser sources, laser scanners, and one or more detectors, among other system components.

The camera 130 may be used to capture multiple images of the surrounding environment of the vehicle 100. The camera 130 may be a still camera or a video camera.

The control system 106 is for controlling the operation of the vehicle 100 and its components. Control system 106 may include various elements including a steering system 132, a throttle 134, a braking unit 136, a computer vision system 140, a route control system 142, and an obstacle avoidance system 144.

The steering system 132 is operable to adjust the heading of the vehicle 100. For example, in one embodiment, a steering wheel system.

The throttle 134 is used to control the operating speed of the engine 118 and thus the speed of the vehicle 100.

The brake unit 136 is used to control the deceleration of the vehicle 100. The brake unit 136 may use friction to slow the wheel 121. In other embodiments, the brake unit 136 may convert the kinetic energy of the wheel 121 into an electric current. The brake unit 136 may take other forms to slow the rotational speed of the wheels 121 to control the speed of the vehicle 100.

The computer vision system 140 may be operable to process and analyze images captured by the camera 130 to identify objects and/or features in the environment surrounding the vehicle 100. The objects and/or features may include traffic signals, road boundaries, and obstacles. The computer vision system 140 may use object recognition algorithms, motion from Motion (SFM) algorithms, video tracking, and other computer vision techniques. In some embodiments, the computer vision system 140 may be used to map an environment, track objects, estimate the speed of objects, and so forth.

The route control system 142 is used to determine a travel route of the vehicle 100. In some embodiments, the route control system 142 may combine data from the sensors 138, the GPS 122, and one or more predetermined maps to determine a travel route for the vehicle 100.

The obstacle avoidance system 144 is used to identify, evaluate, and avoid or otherwise negotiate potential obstacles in the environment of the vehicle 100.

Of course, in one example, the control system 106 may additionally or alternatively include components other than those shown and described. Or may reduce some of the components shown above.

Vehicle 100 interacts with external sensors, other vehicles, other computer systems, or users through peripherals 108. The peripheral devices 108 may include a wireless communication system 146, an in-vehicle computer 148, a microphone 150, and/or speakers 152.

In some embodiments, the peripheral devices 108 provide a means for a user of the vehicle 100 to interact with the user interface 116. For example, the onboard computer 148 may provide information to a user of the vehicle 100. The user interface 116 may also operate the in-vehicle computer 148 to receive user input. The in-vehicle computer 148 may be operated via a touch screen. In other cases, the peripheral devices 108 may provide a means for the vehicle 100 to communicate with other devices located within the vehicle. For example, the microphone 150 may receive audio (e.g., voice commands or other audio input) from a user of the vehicle 100. Similarly, the speaker 152 may output audio to a user of the vehicle 100.

The wireless communication system 146 may communicate wirelessly with one or more devices, either directly or via a communication network. For example, the wireless communication system 146 may use 3G cellular communication, such as CDMA, EVD0, GSM/GPRS, or 4G cellular communication, such as LTE. Or 5G cellular communication. The wireless communication system 146 may communicate with a Wireless Local Area Network (WLAN) using WiFi. In some embodiments, the wireless communication system 146 may utilize an infrared link, bluetooth, or ZigBee to communicate directly with the device. Other wireless protocols, such as various vehicular communication systems, for example, the wireless communication system 146 may include one or more Dedicated Short Range Communications (DSRC) devices that may include public and/or private data communications between vehicles and/or roadside stations.

The power supply 110 may provide power to various components of the vehicle 100. In one embodiment, power source 110 may be a rechargeable lithium ion or lead acid battery. One or more battery packs of such batteries may be configured as a power source to provide power to various components of the vehicle 100. In some embodiments, the power source 110 and the energy source 119 may be implemented together, such as in some all-electric vehicles.

Some or all of the functionality of the vehicle 100 is controlled by the computer system 112. The computer system 112 may include at least one controller 113, the controller 113 executing instructions 115 stored in a non-transitory computer readable medium, such as the memory 114. The computer system 112 may also be a plurality of computing devices that control individual components or subsystems of the vehicle 100 in a distributed manner.

The controller 113 may be any conventional processor, such as a commercially available CPU. Alternatively, the processor may be a dedicated device such as an ASIC or other hardware-based processor. Although fig. 1 functionally illustrates processors, memories, and other elements of the computer 110 in the same blocks, those of ordinary skill in the art will appreciate that the processors, computers, or memories may actually comprise multiple processors, computers, or memories that may or may not be stored within the same physical housing.

For example, the memory may be a hard disk drive or other storage medium located in a different housing than the computer 110. Thus, references to a processor or computer are to be understood as including references to a collection of processors or computers or memories which may or may not operate in parallel. Rather than using a single processor to perform the steps described herein, some components, such as the steering component and the retarding component, may each have their own processor that performs only computations related to the component-specific functions.

In various aspects described herein, the processor may be located remotely from the vehicle and in wireless communication with the vehicle. In other aspects, some of the processes described herein are executed on a processor disposed within the vehicle and others are executed by a remote processor, including taking the steps necessary to perform a single maneuver.

In some embodiments, the data storage device 114 may include instructions 115 (e.g., program logic), and the instructions 115 may be executed by the processor to perform various functions of the vehicle 100, including those described above. The memory 114 may also contain additional instructions, including instructions to send data to, receive data from, interact with, and/or control one or more of the propulsion system 102, the sensor system 104, the control system 106, and the peripheral devices 108.

In addition to instructions 115, data storage device 114 may also store data such as road maps, route information, the location, direction, speed of the vehicle, and other such vehicle data, among other information. Such information may be used by the vehicle 100 and the computer system 112 during operation of the vehicle 100 in autonomous, semi-autonomous, and/or manual modes.

A user interface 116 for providing information to and receiving information from a user of the vehicle 100. Optionally, the user interface 116 may include one or more input/output devices within the collection of peripheral devices 108, such as a wireless communication system 146, an on-board vehicle computer 148, a microphone 150, and a speaker 152.

The computer system 112 may control the functions of the vehicle 100 based on inputs received from various subsystems (e.g., the travel system 102, the sensor system 104, and the control system 106) and from the user interface 116. For example, the computer system 112 may utilize input from the control system 106 in order to control the steering unit 132 to avoid obstacles detected by the sensor system 104 and the obstacle avoidance system 144. In some embodiments, the computer system 112 is operable to provide control over many aspects of the vehicle 100 and its subsystems.

Alternatively, one or more of these components described above may be mounted or associated separately from the vehicle 100. For example, the data storage device 114 may exist partially or completely separate from the vehicle 1100. The above components may be communicatively coupled together in a wired and/or wireless manner.

Optionally, the above components are only an example, in an actual application, components in the above modules may be added or deleted according to an actual need, and fig. 1 should not be construed as limiting the embodiment of the present application.

An autonomous automobile traveling on a roadway, such as vehicle 100 above, may identify objects within its surrounding environment to determine an adjustment to the current speed. The object may be another vehicle, a traffic control device, or another type of object. In some examples, each identified object may be considered independently and may be used to determine the speed at which the autonomous vehicle is to be adjusted based on the respective characteristics of the object, such as its current speed, acceleration, separation from the vehicle, and the like.

Alternatively, the autonomous automobile vehicle 100 or a computing device associated with the autonomous vehicle 100 (e.g., the computer system 112, the computer vision system 140, the data storage 114 of fig. 1) may predict behavior of the identified objects based on characteristics of the identified objects and the state of the surrounding environment (e.g., traffic, rain, ice on the road, etc.). Optionally, each identified object depends on the behavior of each other, so it is also possible to predict the behavior of a single identified object taking all identified objects together into account. The vehicle 100 is able to adjust its speed based on the predicted behaviour of said identified object.

In other words, the autonomous vehicle is able to determine what steady state the vehicle will need to adjust to (e.g., accelerate, decelerate, or stop) based on the predicted behavior of the object. In this process, other factors may also be considered to determine the speed of the vehicle 100, such as the lateral position of the vehicle 100 in the road on which it is traveling, the curvature of the road, the proximity of static and dynamic objects, and so forth.

In addition to providing instructions to adjust the speed of the autonomous vehicle, the computing device may also provide instructions to modify the steering angle of the vehicle 100 to cause the autonomous vehicle to follow a given trajectory and/or to maintain a safe lateral and longitudinal distance from objects in the vicinity of the autonomous vehicle (e.g., cars in adjacent lanes on the road).

The vehicle 100 may be a car, a truck, a motorcycle, a bus, an amusement car, a playground vehicle, construction equipment, an electric car, a golf cart, a train, etc., and the embodiment of the present application is not particularly limited.

Referring to fig. 4, fig. 4 is a schematic structural diagram of a computer system 101 in a vehicle according to an embodiment of the present disclosure. The computer system 101 shown in fig. 4 is used for executing the interprocess communication method provided by the embodiment of the application. Computer system 101 includes a processor 103, processor 103 coupled to a system bus 105. Wherein the processor 103 may be used to implement the functions of the controller described in fig. 2. Processor 103 may be one or more processors, each of which may include one or more processor cores. A display adapter (video adapter) 107, which may drive a display 109, the display 109 coupled with system bus 105. System bus 105 is coupled through a bus bridge 111 and an input/output (I/O) bus 113. The I/O interface 115 is coupled to an I/O bus. The I/O interface 115 communicates with various I/O devices, such as an input device 117 (e.g., keyboard, mouse, touch screen, etc.), a multimedia disk (media tray) 121 (e.g., CD-ROM, multimedia interface, etc.). A transceiver 123 (which can send and/or receive radio communication signals), a camera 155 (which can capture motion digital video images), and an external USB port 125. Wherein, optionally, the interface connected with the I/O interface 115 may be a USB interface.

The processor 103 may be any conventional processor, including a reduced instruction set computing ("RISC") processor, a complex instruction set computing ("CISC") processor, or a combination of the above. Alternatively, the processor may be a dedicated device such as an application specific integrated circuit ("ASIC"). Alternatively, the processor 103 may be a neural network processor or a combination of a neural network processor and a conventional processor as described above.

Optionally, in various embodiments described herein, computer system 101 may be located remotely from the autonomous vehicle and may communicate wirelessly with the autonomous vehicle. In other aspects, some processes described herein are performed on a processor disposed within an autonomous vehicle, others being performed by a remote processor, including taking the actions required to perform a single maneuver.

Computer system 101 may communicate with software deploying server 149 via network interface 129. The network interface 129 is a hardware network interface, such as a network card. The network 127 may be an external network, such as the internet, or an internal network, such as an ethernet or a Virtual Private Network (VPN). Optionally, the network 127 can also be a wireless network, such as a WiFi network, a cellular network, and the like.

The hard drive interface is coupled to system bus 105. The hardware drive interface is connected with the hard disk drive. System memory 135 is coupled to system bus 105. Data running in system memory 135 may include the operating system 137 and application programs 143 of computer 101.

The operating system includes a Shell 139 and a kernel 141.Shell 139 is an interface between the user and the kernel of the operating system. The shell is the outermost layer of the operating system. The shell manages the interaction between the user and the operating system, waiting for user input, interpreting the user input to the operating system, and processing the output results of the various operating systems.

Kernel 141 is comprised of those portions of the operating system that manage memory, files, peripherals, and system resources. Interacting directly with the hardware, the operating system kernel typically runs processes and provides inter-process communication, CPU slot management, interrupts, memory management, IO management, and the like.

The application programs 143 include data processing-related programs 147 and programs related to controlling automatic driving of the vehicle. The data processing-related program 147 manages data of each of the plurality of ECUs. The computer system 101 can realize the functions of the controller described in fig. 2, that is, manage data of a plurality of ECUs, for example, delete data stored in a certain ECU, by executing the data processing-related program 147.

The programs associated with controlling the automatic driving of the vehicle may include, for example, programs for managing the interaction of the automatically driven vehicle with obstacles on the road, programs for controlling the route or speed of the automatically driven vehicle, and programs for controlling the interaction of the automatically driven vehicle with other automatically driven vehicles on the road. Application 143 also resides on the system of the exploiting server 149.

Sensor 153 is associated with computer system 101. The sensors 153 are used to detect the environment surrounding the computer system 101. For example, the sensor 153 may detect an animal, a car, an obstacle, a crosswalk, and the like, and further, the sensor may detect an environment around the animal, the car, the obstacle, the crosswalk, and the like, such as: the environment surrounding the animal, e.g., other animals present around the animal, weather conditions, brightness of the surrounding environment, etc.

In the above, an application scenario of the inter-process communication method provided in the embodiment of the present application is introduced, and an execution flow of the inter-process communication method provided in the embodiment of the present application is described in detail below. Referring to fig. 5, fig. 5 is a flowchart illustrating an inter-process communication method 500 according to an embodiment of the present disclosure. As shown in FIG. 5, the inter-process communication method 500 includes the following steps 501-505.

Step 501, a first instruction from a first process is obtained, where the first instruction is used to request to obtain an address of a shared memory, and the shared memory is used for inter-process communication.

In this embodiment, the first process may be any process that needs to implement inter-process communication through a shared memory. The first process may be any one of processes communicating with each other. For example, the first process may be a sender process of inter-process communication, and the first process needs to send communication data to a receiver process; the first process may also be a receiver process of the inter-process communication, and the first process needs to receive communication data sent by the sender process.

For example, in a smart driving scenario, the first process may be a sensor process, which is responsible for acquiring sensor data and sending the sensor data to a processing process; the first process may also be a processing process, and is responsible for receiving sensor data transmitted by the shared memory, and executing corresponding processing operations according to the sensor data.

After the processor allocates the shared memory for communication to the first process, the processor may obtain a first instruction from the first process, where the first instruction is used to request to obtain an address of the shared memory, so that the first process can write data into the shared memory or read data from the shared memory.

Optionally, before the first process generates the first instruction, the first process may request to allocate the shared memory and obtain information of the allocated shared memory. In this way, the first process may generate a first instruction to request to obtain an address of the shared memory for communication based on the information of the allocated shared memory.

For example, assuming that a first process needs to communicate with a second process, a processor may obtain a fourth instruction from the first process, where the fourth instruction is used to request allocation of memory for inter-process communication. Then, the processor allocates the shared memory to the first process according to the fourth instruction, and returns the identifier of the shared memory to the first process. Specifically, the processor may designate a memory segment as the shared memory in the memory according to the fourth instruction, allocate a unique identifier to the shared memory, and return the identifier of the shared memory to the first process and the second process. In this way, the first process may generate a first instruction based on the identifier of the shared memory returned by the processor, where the first instruction includes the identifier of the shared memory to request to obtain the address of the shared memory.

Step 502, returning a first address to the first process according to the first instruction, and adding the first address to a filter table corresponding to the first process, where the first address is an address in the shared memory, and the filter table is used to store addresses of the shared memory that can be accessed by the first process.

After acquiring a first instruction from a first process, a processor acquires a first address in a shared memory according to the first instruction, and returns the first address to the first process, so that the first process can use a memory segment corresponding to the first address to perform inter-process communication. The first address may be an address range, and is used to indicate an address segment corresponding to a memory segment in the shared memory. And the memory segment corresponding to the first address is a memory used for the first process to perform inter-process communication.

Illustratively, the first address may include a start address and an end address, the start address is used to indicate a start address of the memory segment corresponding to the first address, and the end address is used to indicate an end address of the memory segment corresponding to the first address; the first address may also include a start address and an address offset, where the address offset is used to indicate an address length between a start address and an end address of a memory segment corresponding to the first address.

In addition, after the processor acquires the first address, the processor also adds the first address to a filter table corresponding to the first process. The filtering table is established by the processor when the first process needs to perform inter-process communication, and is used for recording addresses which can be accessed by the first process, and the addresses recorded in the filtering table are all addresses in the shared memory. That is, for addresses recorded in the filter table, the first process has a right to access the addresses recorded in the filter table; for the address of the shared memory which is not recorded in the filter table, the first process does not have access right.

Generally, assuming that a first process and a second process perform inter-process communication, a shared memory allocated by a processor for the first process and the second process is usually divided into a plurality of memory segments, so that the first process and the second process can access different memory segments in the shared memory at the same time. Therefore, by establishing the filter table and adding the address in the shared memory requested by the first process in the filter table, the address of the shared memory to which the first process has the access right can be recorded.

Step 503, obtaining a second instruction from the first process, where the second instruction includes the first address, and the second instruction is used to request to use a storage space corresponding to the first address.

And after the first process acquires the first address returned by the processor, the first process generates a second instruction according to the communication requirement. The second instruction comprises the address, and the second instruction is used for requesting to use the storage space corresponding to the first address so as to realize inter-process communication based on the storage space corresponding to the first address.

In particular, the second instructions may be instructions having different roles when the first process is a different role of inter-process communication.

Exemplarily, in a case that the first process is a sender process and the second process is a receiver process, the first process needs to transmit data to the second process, so that the second instruction further includes first data, where the second instruction is used to instruct to write the first data into a storage space corresponding to the first address, and the first data is data to be transmitted to the second process. That is to say, after acquiring the first address, the first process generates a second instruction based on the first address and first data to be transmitted to the second process, so as to request to write the first data into the shared memory.

Illustratively, in a case that the first process is a receiver process and the second process is a sender process, the first process needs to receive data transmitted by the second process, so that the second instruction is specifically used to instruct to read second data in a storage space corresponding to the first address, where the second data is data transmitted to the first process by the second process. That is to say, after acquiring the first address, the first process generates, based on the first address, a second instruction for requesting to access the storage space corresponding to the first address, so as to read second data transmitted by the second process through the storage space corresponding to the first address.

Step 504, based on the first address in the second instruction being an address of the shared memory, triggering to query the filter table, and executing the second instruction according to the first address located in the filter table.

After the processor fetches the second instruction, the processor may identify the first address in the second instruction as an address in shared memory for inter-process communication. Therefore, in order to avoid the first process stepping on the memory segment in use by other processes, the processor triggers the query of the filter table to determine whether the first process has the right to access the first address by determining whether the first address in the second instruction is located in the filter table.

That is, when the processor obtains an instruction for accessing an address and determines that the address is an address in the shared memory, the processor triggers a query of the filter table to determine whether the address is located in the filter table. If the address is in the filter table, then the representative process has the right to access the address; if the address is not located in the filter table, the delegate process does not have access to the address.

Since the first address is located in the filter table, the processor may determine that the first process has permission to access the first address, the processor executing a second instruction from the first process.

Illustratively, when the first process is a sender process and the second process is a receiver process, the second instruction further includes first data, and the processor writes the first data into the storage space corresponding to the first address according to the second instruction, so that the second process can obtain the first data transmitted by the first process from the storage space corresponding to the first address.

Illustratively, when the first process is a receiver process and the second process is a sender process, the processor reads second data in the storage space corresponding to the first address according to the second instruction, and returns the second data to the first process, so that the first process can acquire the second data transmitted by the second process.

And step 505, after the second instruction is executed, deleting the first address in the filter table.

After the processor executes the second instruction, the processor has already written the first data into the storage space corresponding to the first address or read the second data in the storage space corresponding to the first address, that is, the first process has successfully transmitted the first data or read the second data, and the first process does not need to access the storage space corresponding to the first address any more. Therefore, after the processor executes the second instruction, the first address in the filter table is deleted, so that the first process no longer has the right to access the first address.

For example, the processor may also obtain a fifth instruction from the first process, where the fifth instruction is used to indicate that the memory space corresponding to the first address is used up. And the processor deletes the first address in the filter table according to the fifth instruction.

In this way, after the first address in the filter table is deleted, if the first process continues to request access to the first address due to bug or attack, the processor may reject the request of the first process according to the filter table without the first address, thereby effectively preventing the first process from stepping on a memory space corresponding to the first address that is being used by other processes.

In this embodiment, a first process that needs to communicate based on a shared memory obtains an address of the shared memory through an instruction, and the instruction triggers to add the obtained address of the shared memory into a filter table; when the first process accesses the address of the shared memory, triggering and inquiring the filter table to determine whether the first process has the authority of accessing the shared memory. And after the first process successfully accesses the shared memory, releasing the access authority of the first process in the filter table, thereby ensuring that the process cannot step on the shared memory used by another process due to software errors or attacks.

Briefly, based on the filtering mechanism of the filtering table provided in this embodiment, the processor can refuse to access the address of the shared memory to which the process does not have access permission, so as to avoid the process from trampling the memory segment in the shared memory being used by other processes.

Illustratively, when a bug occurs in a first process or a first process is attacked by a malicious attack, a processor acquires a third instruction from the first process, wherein the third instruction comprises a second address, and the third instruction is used for requesting to use a memory space corresponding to the second address. The second address is an address in the shared memory, the second address and the first address may be the same address, and the second address and the first address may also be different addresses. And, the second address is not located in a filter table. That is, the processor may be such that adding the second address to the filter table is not triggered; the processor may also delete the second address from the filter table after the first process loses access to the second address.

And triggering and inquiring the filter table by the processor based on the second address in the third instruction as the address of the shared memory, and refusing to execute the third instruction according to the condition that the second address is not located in the filter table.

That is to say, when the second address requested to be accessed by the first process belongs to an address in the shared memory and the second address is not located in the filter table, the processor may refuse to execute an instruction for the first process to request to access the second address, thereby ensuring that the first process cannot use the storage space corresponding to the second address, and avoiding a phenomenon that the first process steps on the storage space being used by other processes.

Optionally, in step 504, in order to enable the processor to recognize that the first address in the second instruction is an address of the shared memory, the embodiment indicates an address belonging to the shared memory by adding a flag in the page table entry.

Because the addresses used by the processes are all virtual addresses, it is usually necessary to translate the virtual addresses into physical addresses in the memory space by looking up a page table, so as to be able to determine the real memory addresses corresponding to the virtual addresses. The page table is a special data structure, is placed in a page table area of a system space, and stores the corresponding relation between a virtual address and a physical address. Each process has a corresponding page table. In a page table, a physical address to which a virtual address corresponds is referred to as a page table entry. By adding a marker in the page table entry, it can be indicated that the virtual address in the page table entry belongs to an address in the shared memory.

For example, referring to fig. 6, fig. 6 is a schematic structural diagram of a page table entry according to an embodiment of the present application. As shown in fig. 6, the page table entry includes a reserved bit (reserved), and the length of the reserved bit is 10 bits. In addition, the page table entry further includes other bits, which are respectively used for indicating information such as a virtual address, a physical address, and a read-write authority of the physical address in the page table entry. In practical applications, the processor may implement the addition of the flag by setting one or more of the reserved bits of the page table entry. That is, for a virtual address, if one or more of the reserved bits in the page table entry for that virtual address are set, the processor may determine that the virtual address belongs to a shared memory address.

Specifically, in the method 500 described above, the processor may add a mark in a page table entry corresponding to the first process, where the mark is used to indicate that the first address is an address of a shared memory used for inter-process communication, the page table entry is used to indicate a mapping relationship between the first address and a physical address corresponding to the first address, and the first address is a virtual address.

After the shared memory is allocated to the first process, the processor may add a flag to page table entries corresponding to all addresses included in the shared memory to indicate that an address in the shared memory is a specific address for inter-process communication. After the first instruction from the first process is acquired, the processor may add a mark in the page table entry corresponding to the first address to indicate that the first address is a specific address for inter-process communication.

After the second instruction is obtained, the processor may search the page table entry based on the first address in the second instruction, and determine that the first address in the second instruction is an address of the shared memory according to the flag in the page table entry.

That is, after acquiring an address, the processor may search for a page table entry of the address, and determine whether the address is an address of the shared memory by determining whether a reserved bit in the page table entry of the address is set. If the reserved bit in the page table entry of the address is set, the processor may determine that the address belongs to an address of a shared memory; if the reserved bit in the page table entry for the address is not set, the processor may determine that the address does not belong to a shared memory address.

It will be appreciated that when a first process establishes communication with a second process, the processor allocates shared memory for communication for the first and second processes. Under the condition that the first process is a sender process, when the first process needs to transmit data to the second process, the first process requests the processor for the address of a memory segment in the shared memory, so that the data transmission is realized based on the requested memory segment. In the case where the first process is a receiver process, the first process needs to request the processor for an address of a memory segment in the shared memory to read data written in the memory segment by the second process.

Therefore, in order to enable the processor to return the address of a free memory segment in the shared memory to the process when acquiring the instruction requesting to acquire the address in the shared memory, a descriptor for recording the use condition of the shared memory is introduced in the embodiment. By recording the use condition of the shared memory in real time by adopting the descriptor, the processor can acquire the use condition of the shared memory when acquiring the instruction for requesting to acquire the address in the shared memory, thereby returning the effective address of the memory segment to the process.

Illustratively, after the processor allocates the shared memory to the first process, the first instruction generated by the first process includes an identifier of the shared memory, and the first instruction is used to request to acquire an address of the shared memory. The processor may obtain the descriptor corresponding to the shared memory according to the identifier in the first instruction. The descriptor may be created by the processor after the shared memory is allocated to the first process, and the descriptor is used to record the usage of the shared memory. In short, after the processor allocates the shared memory to the two processes that need to communicate each time, a descriptor is established for the allocated shared memory to record the use condition of the shared memory.

After obtaining the descriptor corresponding to the shared memory, the processor may determine the first address according to the content of the descriptor, and return the first address to the first process. And the storage space corresponding to the first address is a storage space to be written in or read from the shared memory.

That is to say, when the first process is a sender process, the processor returns a first address to the first process, and a storage space corresponding to the first address is a storage space of data to be written in the shared memory. And when the first process is a receiver process, the processor returns a first address to the first process, and the storage space corresponding to the first address is the storage space of the data to be read in the shared memory.

For ease of understanding, the contents recorded by the descriptor will be described in detail below with reference to the drawings.

In this embodiment, the shared memory allocated by the processor for the first process includes a plurality of memory blocks, and the memory blocks are organized into a ring queue for reading and writing by the process. The descriptor corresponding to the shared memory records and manages the state of each memory block in the plurality of memory blocks. Specifically, the descriptor includes a write pointer and a read pointer, where the write pointer is used to indicate a location, in the ring queue, of a memory block to be written into the multiple memory blocks, and the read pointer is used to indicate a location, in the ring queue, of a memory block to be read from the multiple memory blocks. Based on the write pointer and the read pointer in the descriptor, the processor may quickly determine the address of the memory block for writing data and the address of the memory block for reading data.

For example, referring to fig. 7, fig. 7 is a schematic structural diagram of a descriptor provided in an embodiment of the present application. As shown in fig. 7, the shared memory allocated by the processor is divided into 16 memory blocks, where the 16 memory blocks are memory block 0-memory block 15. And, the 16 memory blocks are organized into a ring queue for the process to cyclically write data or read data.

The descriptor corresponding to the shared memory includes the size of the memory block, the number of the memory blocks, the virtual address of the sender, the virtual address of the receiver, the write pointer, the read pointer, and the like. The size of the 16 memory blocks divided by the shared memory is the same, and the size of the memory block recorded in the descriptor may be, for example, 4 kilobytes (kB). The number of memory blocks indicates the number of memory blocks divided in the shared memory corresponding to the descriptor, for example, 16. The virtual address of the sender corresponds to the write pointer, the write pointer indicates the position of the memory block of the current data to be written in the circular queue, and the virtual address of the sender indicates the address of the memory block of the data to be written in, that is, the virtual address of the sender indicates a virtual address that the processor needs to return to the process of the sender. The virtual address of the receiving party corresponds to the read pointer, the read pointer indicates the position of the memory block of the current data to be read in the circular queue, and the virtual address of the receiving party indicates the address of the memory block of the data to be read, that is, the virtual address of the reading party indicates the virtual address which the processor needs to return to the process of the reading party.

For example, in fig. 7, the write pointer points to a location of the memory block 3, that is, the memory block to which data is currently to be written in the circular queue is indicated as the memory block 3; when the sender process requests to obtain the address of the shared memory, the processor may return the virtual address of the memory block 3 to the sender. In addition, the read pointer points to the location of the memory block 0, that is, the memory block currently to be read in the circular queue is indicated as the memory block 0.

By organizing a plurality of memory blocks in a shared memory into a ring queue and recording the state of the memory blocks in the ring queue by using descriptors, the processes of two parties in communication can work asynchronously, namely, a sender process and a receiver process access different memory blocks in the shared memory at the same time.

For example, the sender process may first write data to be transmitted to the receiver process into the memory block 0, the memory block 1, and the memory block 2 in sequence. Then, while the sender process writes data into the memory block 3, the receiver process may access the memory block 0 to obtain the data written into the memory block 0 by the sender process. In this way, the process of the sender writes data in sequence according to the sequence of the memory blocks in the circular queue, and the process of the receiver reads the data in sequence according to the sequence of the memory blocks in the circular queue, so that asynchronous work of the process of the sender and the process of the receiver is realized, and the communication efficiency is improved. In addition, because a plurality of memory blocks in the shared memory are organized into a ring queue, the process of the sending party can write data into the ring queue circularly, thereby realizing the cyclic utilization of the shared memory and saving the communication overhead.

Alternatively, after the processor executes the instruction that the process requests to write data or read data, the processor may update the write pointer or the read pointer in the descriptor so that the processor can return a valid address to the process when the process requests an address of the shared memory.

For example, in a case that the first process is a sender process, after executing the second instruction requesting to write data, the processor updates the write pointer in the descriptor to update a location, in the ring queue, of a memory chunk to be written in the multiple memory chunks. Meanwhile, when the write pointer is updated, the sender virtual address corresponding to the write pointer is also updated accordingly.

When the first process is a receiver process, after executing the second instruction requesting to read data, the processor updates the read pointer in the descriptor to update a position of a memory block to be read in the plurality of memory blocks in the ring queue. At the same time, in the case of an update of the read pointer, the virtual address of the receiver corresponding to the read pointer is also updated accordingly.

Taking fig. 7 as an example, the sender process requests to obtain the address of the shared memory, and the processor returns the address of the memory block 3 to the sender process according to the content of the descriptor; then, the processor acquires a data write instruction from the sender process, and writes data into the memory block 3 according to the data write instruction. After the processor finishes executing the data writing instruction, the processor updates the write pointer in the descriptor, and points the write pointer to the location of the memory block 4, that is, the memory block to which data is currently written in the circular queue is indicated as the memory block 4.

For another example, the receiver process requests to obtain the address of the shared memory, and the processor returns the address of the memory block 0 to the receiver process according to the content of the descriptor; then, the processor obtains a data reading instruction from the receiving process, and reads the data in the memory block 0 according to the data reading instruction. After the processor finishes executing the data reading instruction, the processor updates the reading pointer in the descriptor, and points the reading pointer to the location of the memory block 1, that is, the memory block to be currently read in the ring queue is indicated as the memory block 1.

In this way, when a process requests an address of the shared memory, the processor returns a corresponding address according to the write pointer or the read pointer in the descriptor, and updates the write pointer or the read pointer in the descriptor after the data write instruction or the data read instruction is executed, so that the process can be guaranteed to write data or read data in the multiple memory blocks of the ring queue in order.

Optionally, since a process may establish communication with multiple other processes at the same time, the process is allocated multiple different shared memories, and each shared memory has a corresponding descriptor. Therefore, in order to manage multiple descriptors corresponding to the same process, the present embodiment may store addresses of multiple descriptors corresponding to the same process through the descriptor table.

For example, the processor may generate a descriptor table for a first process when the first process first establishes communication with other processes. Thus, when the first process establishes communication with any process, the processor adds the address of the descriptor of the shared memory corresponding to the first process and the process to the descriptor table. In addition, the descriptor table may further include a corresponding relationship between the descriptor and the identifier of the shared memory, so that a subsequent processor can determine the corresponding descriptor according to the identifier of the shared memory.

For example, when the processor acquires a fourth instruction from the first process, the processor generates a descriptor corresponding to the shared memory according to the fourth instruction, and adds an address of the descriptor to a descriptor table corresponding to the first process. The method is used for requesting to allocate the memory for inter-process communication. After the processor allocates the shared memory to the first process according to the fourth instruction, the processor may further add the identifier of the shared memory to the descriptor table to establish a correspondence between the address of the descriptor and the identifier of the shared memory.

When the processor acquires a first instruction including an identifier of a shared memory, the processor may acquire, according to the identifier in the first instruction, an address of a descriptor corresponding to the identifier in a descriptor table corresponding to a first process, where the descriptor table is used to store addresses of one or more descriptors corresponding to the first process. Then, the processor acquires the descriptor according to the address of the descriptor.

For example, 4 descriptors, namely descriptor 0, descriptor 1, descriptor 2 and descriptor 3, are included in the descriptor table corresponding to the first process; the identifiers of the shared memory corresponding to the descriptor 0, the descriptor 1, the descriptor 2 and the descriptor 3 are the identifier 0, the identifier 1, the identifier 2 and the identifier 3, respectively. Then, when the processor fetches the first instruction including identification 2 from the first process, the processor may then determine the address of descriptor 2 in the descriptor table according to identification 2, and thus fetch descriptor 2.

The above details describe that the access control of the process is realized by adding the address of the shared memory requested by the process to the filter table, and deleting the address of the shared memory in the filter table after the process has accessed the shared memory. For ease of understanding, the following describes in detail how the addition and deletion of the shared memory addresses to and from the filter table is triggered by instructions from the perspective of the sender process and the receiver process.

In the embodiment, the communication among the processes is supported by introducing four new instructions in the process of process communication, so that the behavior of the processes accessing the shared memory can be controlled, and the processes in the communication cannot access the memory segments in use by other processes, thereby avoiding the phenomenon that the system is down due to the fact that data in the shared memory is damaged.

Referring to fig. 8, fig. 8 is a flowchart illustrating an inter-process communication method 800 according to an embodiment of the present disclosure. As shown in FIG. 8, the inter-process communication method 800 includes the following steps 801-806.

In step 801, the sender process generates a request (Acquire) instruction.

After the processor allocates the shared memory to the sender process and the receiver process, the sender process generates an Acquire instruction to request to Acquire an address of the shared memory.

After the processor acquires the Acquire instruction, the processor returns the address of the idle memory block in the shared memory to the sender process, and adds the address of the memory block to the filter table corresponding to the sender process. That is to say, the sender process generates an Acquire instruction to trigger the addition of the address of the memory block to be accessed by the sender into the filter table, so as to give the sender process the authority to access the address of the memory block.

In the above embodiment, when the first process is a sender process, the Acquire instruction may be, for example, the first instruction described in the above embodiment.

Step 802, the sender process generates a data write command.

After the address of the memory block returned by the processor is acquired, the sender process generates a data write instruction including the address of the memory block to instruct to write data to be transmitted to the receiver process into the memory block.

And after the processor acquires the data writing instruction, the processor triggers and queries the filter table according to the address in the data writing instruction as the address of the shared memory. And the processor executes the data writing instruction according to the position of the address in the data writing instruction in the filter table, so that the data is written into the memory block.

In the above embodiment, when the first process is a sender process, the data write instruction may be, for example, the second instruction described in the above embodiment.

At step 803, the sender process generates a Push (Push) instruction.

After the data writing instruction is executed, the data transmitted by the sender process is successfully written into the memory block of the shared memory, so that the sender process generates a Push instruction to indicate that the access authority of the sender process to the memory block is revoked.

And the processor deletes the address of the memory block in the filter table corresponding to the sender process according to the Push instruction, so as to revoke the access authority of the sender process to the memory block.

In the above embodiment, when the first process is a sender process, the Push instruction may be, for example, the fifth instruction described in the above embodiment.

At step 804, the receiver process generates a Pop (Pop) instruction.

After the sender process writes data into the memory block of the shared memory, the receiver process generates a Pop instruction to request to acquire the address of the shared memory.

After the processor acquires the Pop instruction, the processor returns the address of the memory block, in which the data has been written, in the shared memory to the receiver process, and adds the address of the memory block to the filter table corresponding to the receiver process. That is, the Pop instruction is generated by the receiver process to trigger the address of the memory block to be accessed by the receiver to be added to the filter table, so as to give the receiver process the authority to access the address of the memory block.

In the above embodiment, when the first process is a receiver process, the Pop instruction may be, for example, the first instruction described in the above embodiment.

In step 805, the recipient process generates a data read instruction.

After acquiring the address of the memory block returned by the processor, the receiving process generates a data read instruction including the address of the memory block to indicate to read the data written by the sending process in the memory block.

After the processor acquires the data reading instruction, the processor triggers and queries the filter table according to the address in the data reading instruction as the address of the shared memory. And the processor executes the data reading instruction according to the address in the data reading instruction in the filter table, so as to read the data in the memory block and return the read data to the process of the receiving party.

In the above embodiment, when the first process is a receiver process, the data reading instruction may be, for example, the second instruction described in the above embodiment.

At step 806, the recipient process generates a Release (Release) instruction.

After the data reading instruction is executed, the receiver process successfully reads the data in the memory block of the shared memory, so that the receiver process generates a Release instruction to indicate that the access authority of the receiver process to the memory block is revoked.

And the processor deletes the address of the memory block in the filter table corresponding to the receiver process according to the Release instruction, so as to revoke the access authority of the receiver process to the memory block.

In the above embodiment, when the first process is a receiver process, the Release instruction may be, for example, the fifth instruction described in the above embodiment.

In summary, for the sender process, in this embodiment, the authority of the sender process to access the memory block in the shared memory is given by the Acquire instruction, and the access authority of the sender process is revoked by the Push instruction. For the process of the receiving party, in this embodiment, the authority of the process of the receiving party to access the memory block in the shared memory is given by the Pop instruction, and the access authority of the process of the receiving party is revoked by the Release instruction.

Referring to fig. 9, fig. 9 is a schematic diagram illustrating a state change of a memory block in a shared memory according to an embodiment of the present disclosure. As shown in fig. 9, when data is not written to the memory block in the shared memory, the state of the memory block is an idle (Free) state.

After the sender process generates the Acquire instruction, it indicates that the sender process is about to write data into the memory block, and therefore the state of the memory block is changed to a transmission active (TxActive) state.

When the sending party process generates the Push instruction, the data is successfully written into the memory block by the sending party process, and the data which needs to be transmitted to the receiving party process by the sending party process is stored in the memory block, so that the state of the memory block is changed into a Busy (Busy) state.

When the receiving process generates the Pop instruction, the receiving process indicates that the receiving process wants to read the data in the memory block, so the state of the memory block is changed to a receiving active (RxActive) state.

When the receiver process generates the Release instruction, it indicates that the receiver process has successfully read the data in the memory block, and the data stored in the memory block has been successfully transmitted to the receiver process, so the state of the memory block changes to an idle (Free) state.

That is, after the state of the memory block changes to the idle state again, the sending process may continue to write the data to be transmitted into the memory block, and the receiving process reads the data in the memory block, so as to implement communication between processes in a loop.

For convenience of understanding, the interprocess communication method provided by the embodiment of the present application will be described in detail below with reference to specific examples.

Referring to fig. 10, fig. 10 is a schematic diagram of a system architecture of interprocess communication according to an embodiment of the present disclosure.

In a hardware configuration, a processor for processing a process includes two registers and a Memory Management Unit (MMU), and the MMU includes a filter.

One register in the processor is used for storing the address of the descriptor table in the memory, and the processor can acquire the descriptor table stored in the memory based on the value of the register; the other register is used for storing the address of the filter table in the memory, and the processor can acquire the filter table stored in the memory based on the value of the register.

An MMU is the computer hardware responsible for processing memory access requests by a processor. The MMU functions primarily include virtual to physical address translation, i.e., translating a virtual address requested for access by a process to a physical address in memory. And the filter in the MMU is used for determining whether the process has the authority of accessing the address in the shared memory according to the address in the filter table when the shared memory access request from the process is acquired. If the process has the authority of accessing the address in the shared memory, executing the shared memory access request of the process; and if the process does not have the authority of accessing the address in the shared memory, refusing to execute the shared memory access request of the process, and reporting the exception.

In the memory, a descriptor table, a filter table and a descriptor corresponding to each process are stored, and a shared memory for process communication is allocated. Each process corresponds to a descriptor table, and the descriptor table is used for storing the addresses of all descriptors corresponding to the process; each process may be established with one or more communications, each with a corresponding descriptor, i.e. each process has one or more descriptors corresponding to it. Also, two processes in communication correspond to the same descriptor. Each process also corresponds to a filter table, and the filter table records the addresses of the shared memory which can be accessed by the process.

For example, referring to fig. 11A, fig. 11A is a schematic structural diagram of a descriptor table according to an embodiment of the present application. As shown in FIG. 11A, the descriptor table register 1 stores the address of the descriptor table of process A, and the processor can obtain the descriptor table of process A based on the value of the descriptor table register 1. The descriptor table register 2 stores the address of the descriptor table of process B, and the processor can acquire the descriptor table of process B based on the value of the descriptor table register 2.

In the descriptor table of process a, the addresses of a plurality of descriptors corresponding to process a are recorded. In addition, among the plurality of descriptors corresponding to the process a, the process may be a process that is a sender in communication or a process that is a receiver in communication. For example, the 0 th descriptor address in the descriptor table of process a indicates the descriptor for the communication between process a and process B.

In the descriptor table of process B, the addresses of multiple descriptors corresponding to process B are also recorded. In addition, among the plurality of descriptors corresponding to the process B, the process may be a process that is a sender in communication or a process that is a receiver in communication. For example, the 2 nd descriptor address in the descriptor table of process B indicates the descriptor for the communication between process a and process B.

Referring to fig. 11B, fig. 11B is a schematic structural diagram of a descriptor provided in the embodiment of the present application. As shown in fig. 11A, a plurality of virtual addresses, for example, virtual address 1, virtual address 2, and virtual address 3, are recorded in the filter table. Each virtual address indicates a space range of the virtual address, that is, indicates an address range corresponding to a segment of memory.

Specifically, the system architecture in the smart driving scenario will be described below. Referring to fig. 12, fig. 12 is a schematic diagram of a system architecture in an intelligent driving scenario according to an embodiment of the present application.

As shown in fig. 12, the system architecture of the intelligent driving scenario includes a sender processor, a receiver processor, and a physical memory. The processor of the sender refers to a processor for running the process of the sender, and the processor of the receiver refers to a processor for running the process of the receiver.

In the sending processor, MMU1, register 1, and register 2 are included. The MMU1 is responsible for translating virtual addresses in data write requests from sender processes to physical addresses. The register 1 stores the address of the descriptor table 1 corresponding to the sender process in the physical memory. The register 2 stores the address of the filter table 1 corresponding to the sender process in the physical memory.

In the recipient processor, MMU2, register 3, and register 4 are included. The MMU2 is responsible for translating virtual addresses in data read requests from the recipient process to physical addresses. The register 3 stores the address of the descriptor table 2 corresponding to the process of the receiving party in the physical memory. The register 4 stores the address of the filter table 2 corresponding to the process of the receiving party in the physical memory.

In the physical memory, a descriptor table 1 and a filter table 1 corresponding to the sender process, a descriptor table 2 and a filter table 2 corresponding to the receiver process, and a shared memory and a descriptor corresponding to the sender process and the receiver process are respectively stored. Wherein, the descriptor table 1 and the descriptor table 2 both indicate the address of the descriptor. The descriptor records the usage of multiple memory blocks in the shared memory.

Referring to fig. 13, fig. 13 is a flowchart illustrating an inter-process communication method 1300 according to an embodiment of the present disclosure. As shown in FIG. 13, the inter-process communication method 1300 includes the following steps 1301-1316.

In step 1301, the sender processor obtains an Acquire instruction from the sender process.

After the sender processor allocates the shared memory to the sender process, the sender processor stores the identifier of the shared memory in the source register 1. The sender process may generate an Acquire instruction based on the identification of the shared memory in source register 1. The Acquire instruction includes an identifier of a shared memory, and the Acquire instruction is used for requesting to Acquire an address in the shared memory.

In step 1302, the sender processor returns the address of the target memory block in the shared memory to the sender process.

And the processor of the sending party acquires the physical address of the descriptor table according to the descriptor table register so as to acquire the descriptor table corresponding to the progress of the sending party. And then, the sender process determines the address of the corresponding descriptor in the descriptor table according to the identifier of the shared memory in the Acquire instruction so as to obtain the descriptor corresponding to the sender process. And the sender process determines the address of the target memory block according to the write pointer in the descriptor, and stores the address of the target memory block in the target register so as to realize the purpose of returning the address of the target memory block in the shared memory to the sender process. The target memory block is a memory block to which data is to be written in the shared memory.

In step 1303, the sender processor adds the address of the target memory block to the filter table 1.

And the sender processor acquires the physical address of the filter table 1 according to the filter table register, so as to acquire the filter table 1 corresponding to the sender process. The sender processor then adds the address of the target memory block to the filter table 1.

In step 1304, the sender processor obtains a data write command from the sender process, where the data write command includes an address of the target memory block and data to be written.

Step 1305, the sending processor triggers to query the filtering table 1 according to the address in the data write command being the address of the shared memory, and confirms that the address in the data write command is located in the filtering table 1.

When the sender processor allocates the shared memory for the sender process, the sender processor sets the reserved position in the page table entry corresponding to the address of the shared memory in the sender process to indicate that the address of the shared memory is specially used for inter-process communication. Therefore, the sender processor may determine that the address in the data write instruction is the address of the shared memory according to the setting of the page table entry corresponding to the address in the data write instruction, thereby triggering the query of the filter table 1. Also, the sender processor may confirm that the address in the data write command is located in the filter table 1.

In step 1306, the sending processor executes the data write command to write data into the target memory block in the shared memory.

In step 1307, the sender processor obtains a Push instruction from the sender process.

After the data write-in instruction is executed, the data transmitted by the sender process is successfully written into the memory block of the shared memory, so that the sender process generates a Push instruction to indicate that the access authority of the sender process to the target memory block is revoked.

In step 1308, the sender processor deletes the address of the target memory block in the filter table 1.

In addition, the sending processor updates the write pointer in the descriptor such that the write pointer points to the memory block next to the target memory block.

At step 1309, the receiver processor obtains the Pop instruction from the receiver process.

After allocating the shared memory for the sender process and the receiver process, the receiver processor stores the identification of the shared memory in the source register 2. The recipient process may generate a Pop instruction based on the identity of the shared memory in source register 2. The Pop instruction includes an identifier of the shared memory, and the Pop instruction is used for requesting to obtain an address in the shared memory.

In step 1310, the receiving processor returns the address of the target memory block in the shared memory to the receiving process.

And the processor of the receiving party acquires the physical address of the descriptor table according to the descriptor table register so as to acquire the descriptor table corresponding to the progress of the receiving party. And then, the process of the receiving party determines the address of the corresponding descriptor in the descriptor table according to the identifier of the shared memory in the Pop instruction so as to acquire the descriptor corresponding to the process of the receiving party. And the process of the receiver determines the address of the target memory block according to the reading pointer in the descriptor, and stores the address of the target memory block in the target register so as to realize the return of the address of the target memory block in the shared memory to the process of the receiver. The target memory block is a memory block of the shared memory from which data is to be read.

In step 1311, the receiving processor adds the address of the target memory block to the filter table 2.

And the processor of the receiving party acquires the physical address of the filter table 2 according to the filter table register, thereby acquiring the filter table 2 corresponding to the process of the receiving party. The recipient processor then adds the address of the target memory block to the filter table 2.

In step 1312, the receiving processor obtains a data read command from the receiving process, where the data read command includes an address of the target memory block.

In step 1313, the receiving-side processor triggers querying of the filter table 2 according to the address in the data reading instruction being the address of the shared memory, and determines that the address in the data reading instruction is located in the filter table 2.

When the receiver processor allocates the shared memory for the receiver process, the receiver processor sets the reserved position in the page table entry corresponding to the shared memory address in the receiver process to indicate that the shared memory address is specially used for inter-process communication. Therefore, the receiver processor may determine that the address in the data reading instruction is the address of the shared memory according to the setting of the page table entry corresponding to the address in the data writing instruction, so as to trigger the query of the filtering table 2. Also, the recipient processor may confirm that the address in the data read instruction is in filter table 2.

At step 1314, the receiving processor executes the data reading instruction to read data in the target memory block in the shared memory.

At step 1315, the receiver processor obtains a Release instruction from the receiver process.

After the data reading instruction is executed, the receiver process has successfully read the data in the memory block of the shared memory, so that the receiver process generates a Push instruction to indicate that the access authority of the receiver process to the target memory block is revoked.

In step 1316, the receiving processor deletes the address of the target memory block in the filter table 2.

In addition, the receiving processor updates the read pointer in the descriptor such that the read pointer points to the next memory block of the target memory block.

On the basis of the embodiments corresponding to fig. 1 to fig. 13, in order to better implement the above-mentioned scheme of the embodiments of the present application, the following also provides related equipment for implementing the above-mentioned scheme.

Specifically, referring to fig. 14, fig. 14 is a schematic structural diagram of an electronic device 1400 provided in the embodiment of the present application, where the electronic device 1400 includes: an acquisition unit 1401, a processing unit 1402, and a transmission unit 1403; the obtaining unit 1401 is configured to obtain a first instruction from a first process, where the first instruction is used to request to obtain an address of a shared memory, and the shared memory is used for inter-process communication; the sending unit 1403 is configured to return a first address to the first process according to the first instruction, and add the first address to a filter table corresponding to the first process, where the first address is an address in the shared memory, and the filter table is used to store an address of the shared memory that can be accessed by the first process; the obtaining unit 1401 is further configured to obtain a second instruction from the first process, where the second instruction includes the first address, and the second instruction is used to request to use a storage space corresponding to the first address; the processing unit 1402, configured to trigger query of the filter table based on that a first address in the second instruction is an address of a shared memory, and execute the second instruction according to that the first address is located in the filter table; the processing unit 1402 is further configured to delete the first address from the filter table after the second instruction is executed.

In a possible implementation manner, the second instruction further includes first data, where the second instruction is used to instruct to write the first data into a storage space corresponding to the first address, and the first data is data to be transmitted to a second process; the processing unit 1402 is specifically configured to write the first data into the storage space corresponding to the first address.

In a possible implementation manner, the second instruction is used to instruct to read second data in a storage space corresponding to the first address, where the second data is data transmitted from a second process to the first process; the processing unit 1402 is specifically configured to read the second data in the storage space corresponding to the first address, and return the second data to the first process.

In a possible implementation manner, the obtaining unit 1401 is further configured to obtain a third instruction from the first process, where the third instruction includes a second address, the third instruction is configured to request to use a storage space corresponding to the second address, and the second address is an address in the shared memory; the processing unit 1402 is specifically configured to trigger query of the filter table based on the second address in the third instruction being an address of the shared memory, and refuse to execute the third instruction according to the second address not being located in the filter table.

In a possible implementation manner, the processing unit 1402 is further configured to add a mark in a page table entry corresponding to the first process, where the mark is used to indicate that the first address is an address used for inter-process communication, the page table entry is used to indicate a mapping relationship between the first address and a physical address corresponding to the first address, and the first address is a virtual address; the processing unit 1402 is specifically configured to: looking up the page table entry based on a first address in the second instruction; and determining that the first address in the second instruction is the address of the shared memory according to the mark in the page table entry.

In a possible implementation manner, the first instruction includes an identifier of the shared memory; the processing unit 1402 is specifically configured to obtain a descriptor according to the identifier, where the descriptor is used to record a use condition of the shared memory; the sending unit 1403 is specifically configured to determine the first address according to the descriptor, and return the first address to the first process, where a storage space corresponding to the first address is a storage space to be written in or read from the shared memory.

In a possible implementation manner, the processing unit 1402 is specifically configured to: according to the identification, obtaining the address of the descriptor corresponding to the identification in a descriptor table corresponding to a first process, wherein the descriptor table is used for storing the addresses of one or more descriptors corresponding to the first process; and acquiring the descriptor according to the address of the descriptor.

In a possible implementation manner, the processing unit 1402 is specifically configured to: after the second instruction is executed, updating the write pointer in the descriptor to update a location, in the circular queue, of a memory block to be written in the plurality of memory blocks; or after the second instruction is executed, the read pointer in the descriptor is updated to update the position of the memory block to be read in the circular queue among the plurality of memory blocks.

In a possible implementation manner, the obtaining unit 1401 is further configured to obtain a fourth instruction from the first process, where the fourth instruction is used to request to allocate a memory for inter-process communication; the processing unit 1402 is further configured to allocate the shared memory to the first process according to the fourth instruction, and return an identifier of the shared memory to the first process.

In a possible implementation manner, the processing unit 1402 is further configured to generate a descriptor corresponding to the shared memory according to the fourth instruction, and add an address of the descriptor to a descriptor table corresponding to the first process.

In a possible implementation manner, the obtaining unit 1401 is further configured to obtain a fifth instruction from the first process, where the fifth instruction is used to indicate that the storage space corresponding to the first address is used up; the processing unit 1402 is further configured to delete the first address in the filter table according to the fifth instruction.

The interprocess communication method provided by the embodiment of the application can be specifically executed by a chip in the electronic equipment, wherein the chip comprises: a processing unit, which may be, for example, a processor, and a communication unit, which may be, for example, an input/output interface, a pin or a circuit, etc. The processing unit may execute the computer execution instructions stored in the storage unit to make the chip in the electronic device execute the inter-process communication method described in the embodiments shown in fig. 1 to 13. Optionally, the storage unit is a storage unit in the chip, such as a register, a cache, and the like, and the storage unit may also be a storage unit located outside the chip in the wireless access device, such as a read-only memory (ROM) or another type of static storage device that can store static information and instructions, a Random Access Memory (RAM), and the like.

The present application also provides a computer-readable storage medium, which can be referenced by fig. 15, and in some embodiments, the method disclosed in fig. 5 above can be implemented as computer program instructions encoded on the computer-readable storage medium in a machine-readable format or on other non-transitory media or articles of manufacture.

Fig. 15 schematically illustrates a conceptual partial view of an example computer-readable storage medium comprising a computer program for executing a computer process on a computing device, arranged in accordance with at least some embodiments presented herein.

In one embodiment, the computer-readable storage medium 1500 is provided using a signal bearing medium 1501. The signal bearing medium 1501 may include one or more program instructions 1502, which when executed by one or more processors may provide the functions or portions of the functions described above with respect to fig. 5. Thus, for example, referring to the embodiment shown in FIG. 5, one or more features of steps 501-505 may be undertaken by one or more instructions associated with the signal bearing medium 1501. Further, program instructions 1502 in FIG. 15 also describe example instructions.

In some examples, the signal bearing medium 1501 may include a computer readable medium 1503 such as, but not limited to, a hard disk drive, a Compact Disc (CD), a Digital Video Disc (DVD), a digital tape, a memory, a ROM or RAM, and so forth.

In some implementations, the signal bearing medium 1501 may include a computer recordable medium 1504 such as, but not limited to, memory, read/write (R/W) CD, R/W DVD, and the like. In some implementations, signal bearing medium 1501 may include a communication medium 1505 such as, but not limited to, digital and/or analog communication media (e.g., fiber optic cables, waveguides, wired communications links, wireless communications links, etc.). Thus, for example, signal bearing medium 1501 may be conveyed by a wireless form of communication medium 1505 (e.g., a wireless communication medium conforming to the IEEE 802.15 standard or other transmission protocol).

The one or more program instructions 1502 may be, for example, computer-executable instructions or logic-implemented instructions. In some examples, a computing device of the computing device may be configured to provide various operations, functions, or actions in response to program instructions 1502 communicated to the computing device by one or more of computer-readable media 1503, computer-recordable media 1504, and/or communication media 1505.

It should be understood that the arrangements described herein are for illustrative purposes only. Thus, those skilled in the art will appreciate that other arrangements and other elements (e.g., machines, interfaces, functions, orders, and groupings of functions, etc.) can be used instead, and that some elements may be omitted altogether depending upon the desired results. In addition, many of the described elements are functional entities that may be implemented as discrete or distributed components or in conjunction with other components, in any suitable combination and location.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application, which are essential or part of the technical solutions contributing to the prior art, or all or part of the technical solutions, may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: u disk, removable hard disk, read only memory, random access memory, magnetic disk or optical disk, etc. for storing program codes.

Claims

1. An interprocess communication method, comprising:

acquiring a first instruction from a first process, wherein the first instruction is used for requesting to acquire an address of a shared memory, and the shared memory is used for interprocess communication;

returning a first address to the first process according to the first instruction, and adding the first address to a filter table corresponding to the first process, wherein the first address is an address in the shared memory, and the filter table is used for storing addresses of the shared memory which can be accessed by the first process;

acquiring a second instruction from the first process, wherein the second instruction comprises the first address, and the second instruction is used for requesting to use a storage space corresponding to the first address;

triggering and inquiring the filter table based on the fact that a first address in the second instruction is an address of a shared memory, and executing the second instruction according to the fact that the first address is located in the filter table;

deleting the first address in the filter table after executing the second instruction.

2. The method according to claim 1, wherein the second instruction further includes first data, the second instruction is used to instruct to write the first data into a storage space corresponding to the first address, and the first data is data to be transmitted to a second process;

the executing the second instruction comprises:

and writing the first data into a storage space corresponding to the first address.

3. The method according to claim 1, wherein the second instruction is used to instruct to read second data in the storage space corresponding to the first address, where the second data is data transmitted by a second process to the first process;

the executing the second instruction comprises:

and reading second data in the storage space corresponding to the first address, and returning the second data to the first process.

4. The method according to any one of claims 1-3, further comprising:

obtaining a third instruction from the first process, where the third instruction includes a second address, the third instruction is used to request to use a storage space corresponding to the second address, and the second address is an address in the shared memory;

and triggering and inquiring the filter table based on the second address in the third instruction as the address of the shared memory, and refusing to execute the third instruction according to the condition that the second address is not located in the filter table.

5. The method according to any one of claims 1-4, further comprising:

adding a mark in a page table entry corresponding to the first process, wherein the mark is used for indicating that the first address is an address used for inter-process communication, the page table entry is used for indicating a mapping relation between the first address and a physical address corresponding to the first address, and the first address is a virtual address;

the step of setting the first address in the second instruction as the address of the shared memory includes:

searching the page table entry based on the first address in the second instruction;

and determining that the first address in the second instruction is the address of the shared memory according to the mark in the page table entry.

6. The method of any of claims 1-5, wherein the first instruction comprises an identification of the shared memory;

the returning a first address to the first process according to the first instruction includes:

obtaining a descriptor according to the identifier, wherein the descriptor is used for recording the use condition of the shared memory;

and determining the first address according to the descriptor, and returning the first address to the first process, wherein the storage space corresponding to the first address is a storage space to be written in or read from the shared memory.

7. The method of claim 6, wherein obtaining the descriptor according to the identity comprises:

according to the identification, obtaining the address of the descriptor corresponding to the identification in a descriptor table corresponding to a first process, wherein the descriptor table is used for storing the addresses of one or more descriptors corresponding to the first process;

and acquiring the descriptor according to the address of the descriptor.

8. The method according to claim 6 or 7, wherein the shared memory comprises a plurality of memory blocks, and the plurality of memory blocks form a circular queue for a process to read and write;

the descriptor includes a write pointer and a read pointer, where the write pointer is used to indicate a location of a memory block to be written in the plurality of memory blocks in the circular queue, and the read pointer is used to indicate a location of a memory block to be read in the plurality of memory blocks in the circular queue.

9. The method of claim 8, further comprising:

after the second instruction is executed, updating the write pointer in the descriptor to update a location, in the circular queue, of a memory block to be written in the plurality of memory blocks;

or after the second instruction is executed, the read pointer in the descriptor is updated, so as to update a position of a memory block to be read in the multiple memory blocks in the circular queue.

10. The method according to any one of claims 6-9, further comprising:

acquiring a fourth instruction from the first process, wherein the fourth instruction is used for requesting allocation of a memory for inter-process communication;

and allocating the shared memory to the first process according to the fourth instruction, and returning the identifier of the shared memory to the first process.

11. The method of claim 10, further comprising: and generating a descriptor corresponding to the shared memory according to the fourth instruction, and adding the address of the descriptor to a descriptor table corresponding to the first process.

12. The method according to any of claims 1-11, wherein deleting the first address in the filter table after executing the second instruction comprises:

acquiring a fifth instruction from the first process, wherein the fifth instruction is used for indicating that the storage space corresponding to the first address is used up;

and deleting the first address in the filter table according to the fifth instruction.

13. An electronic device comprising a memory and a processor; the memory stores code, the processor is configured to execute the code, and when executed, the electronic device performs the method of any of claims 1-12.

14. A computer readable storage medium comprising computer readable instructions which, when run on a computer, cause the computer to perform the method of any of claims 1 to 12.

15. A computer program product comprising computer readable instructions which, when run on a computer, cause the computer to perform the method of any one of claims 1 to 12.