CN115865301A - Timing synchronization method for resisting large code bias and low power consumption in satellite communication - Google Patents
Timing synchronization method for resisting large code bias and low power consumption in satellite communication Download PDFInfo
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Abstract
The invention relates to a timing synchronization method with large code bias and low power consumption in satellite communication, which comprises the following steps: step 1, inputting a digital baseband signal subjected to digital down-conversion as an input signal by adopting a feedback algorithm based on a digital phase-locked loop, wherein the ratio Fs/Fd of the sampling rate of the input signal to the code element rate is an arbitrary value which is more than or equal to 4; step 2, carrying out interpolation calculation on the input signal by using an interpolation filter to obtain an optimal sampling point; step 3, reducing intersymbol interference by using a matched filter to be matched with a forming filter of a transmitting end; step 4, calculating a timing error by adopting a timing error detector, and inputting the timing error into a loop filter to reduce timing error jitter for the detected timing error; step 5, performing timing error calibration operation, calibrating the timing error by estimating the timing error change rate, and compensating the data deviation caused by calculating the delay; and 6, calculating the position of the interpolation data by using a numerically controlled oscillator NCO, and further obtaining an interpolation base point mk and a decimal interval uk required by interpolation.
Description
Technical Field
The invention belongs to the technical field of satellite communication, and mainly relates to a timing synchronization method for a digital demodulator in a satellite communication system.
Background
The remote sensing satellite in China develops rapidly in recent years, the application field is increased day by day, and the data transmission rate of the satellite is correspondingly increased; meanwhile, with the rapid development of digital devices and digital signal processing technologies, various digital circuits and digital chips have been widely applied to communication devices, so that high speed and full digital signals have become the main trend of demodulator development.
In a digital demodulator, timing synchronization is a very important link, the quality of the timing synchronization directly affects the quality of a communication system, and any communication system needs a stable and accurate timing synchronization technology.
The timing synchronization method commonly used in the communication system mainly comprises two components: a feedback-based phase-locked loop approach and a feedforward-based compensation approach. The synchronization speed of the feedback-based compensation mode is low, and the locking precision is high; the synchronous speed of the compensation method based on feedforward is very fast, but the locking precision is not as good as that of a phase-locked loop.
Parallel processing is a common approach in high-speed digital demodulators. The synchronous algorithm based on feedforward is complex in calculation and large in operation amount (generally, operations such as FFT (fast Fourier transform) and autocorrelation are needed to be taken for hundreds of points), and if the synchronous algorithm is used for parallel processing, the requirement on hardware resources is relatively high. Therefore, the invention mainly researches a feedback-based synchronization algorithm, the calculation amount of the algorithm is very small, and the algorithm has no high requirement on hardware resources when being used for parallel processing.
The timing synchronization method based on feedback gradually enables the phase-locked loop to gradually converge according to the trend of parameter estimation through feedback, and finally locking is achieved. Once the phase-locked loop is locked, the locking error is very small, thereby realizing the timing synchronization function with high precision.
However, because the method is based on a feedback algorithm, the relevance between data of each link is strong, and if the data deviation of a certain link is large, a loop error may be caused, so that the phase-locked loop cannot be converged. When the algorithm is implemented in hardware such as a digital demodulator FPGA (field programmable gate array), due to the existence of large calculation delay, certain deviation exists between feedback data obtained by calculation and a theoretical value, when a system code is large in deviation, the feedback deviation is obviously increased, timing synchronization performance is influenced, and even a phase-locked loop is unlocked, so that the algorithm is invalid.
Disclosure of Invention
In order to solve the technical problems, the technical scheme of the invention is as follows:
a timing synchronization method for resisting large code deviation and low power consumption in satellite communication comprises the following steps:
step 3, reducing intersymbol interference by using a matched filter to be matched with a forming filter of a transmitting end;
step 4, calculating a timing error by adopting a timing error detector, and inputting the timing error into a loop filter to reduce timing error jitter for the detected timing error;
step 5, performing timing error calibration operation, calibrating the timing error by estimating the timing error change rate, and compensating the data deviation caused by calculating the delay;
and 6, calculating the position of the interpolation data by using a numerically controlled oscillator NCO, and further obtaining an interpolation base point mk and a decimal interval uk required by interpolation. Digital interpolation filter rootm k Determining the position of the input sample sequence corresponding to the interpolation point, and obtaining the sample sequence data corresponding to the positionu k The interpolation results are jointly calculated.
Introducing timing error change rate in feedback operationeTo compensate for the difference in time delayeThe variation of the timing error in 1 clock cycle is obtained by counting the average value of the variation rate of the timing error in a plurality of cycles, so as to obtain the expected timing synchronization effect.
Furthermore, the interpolation filter performs interpolation calculation on the input signal by using an interpolation technology to obtain an optimal sampling point.
Further, the timing error calibration operation calibrates the timing error by estimating a timing error change rate, compensating for a data deviation caused by the calculated delay.
Further, the square root raised cosine roll-off filter selected by the shaping filter.
Further, the ratio Fs/Fd of the input signal sampling rate to the symbol rate is an arbitrary value equal to or greater than 4.
Has the beneficial effects that:
when the feedback algorithm is realized in a digital device with the calculation delay, the method can compensate the deviation caused by the delay, correctly realize the algorithm function, not only be applied to the realization of the timing synchronization algorithm, but also be referred to in other algorithm realization parts.
In a satellite communication system, the system code bias is usually large and can generally reach 0.3% under the influence of external factors such as channels, hardware performance and the like, and the method can effectively resist the influence of the large code bias and correctly realize a timing synchronization function.
The invention adopts a timing synchronization method based on feedback, improves on the basis of the existing method, adds a timing error calibration operation, has very small calculation amount of the whole loop (each link only needs to complete multiplication or addition and subtraction operation of a plurality of points or more than ten points, and does not need large calculation amount operation such as FFT (fast Fourier transform) and the like), and has no high requirement on hardware resources when being used for high-speed parallel processing. The invention has wide application range, is not only applied to BPSK/QPSK demodulation systems, but also is mostly applied to timing synchronization parts in QAM demodulation systems.
Drawings
FIG. 1 is a block diagram of an overall timing synchronization process;
FIG. 2 a loop filter structure;
FIG. 3 a digitally controlled oscillator structure;
FIG. 4 is a schematic diagram of a feedback loop without delay;
FIG. 5 is a schematic diagram of a delayed feedback loop;
fig. 6 code bias =0.3%, feedback delay =0, timing synchronization result, (a) constellation, (b) convergence curve;
fig. 7, code offset =0.3%, delay =22, improves the timing synchronization result before the algorithm; (a) constellation, (b) convergence curve;
fig. 8 shows that the code offset =0.3% and the delay =22, and the timing synchronization result after the algorithm is improved, (a) a constellation diagram, and (b) a convergence curve; (c) a convergence curve;
FIG. 9 is a schematic diagram of the interpolation principle;
fig. 10 is a block diagram of an implementation of a piecewise parabolic interpolation filter.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments, and all other embodiments obtained by a person skilled in the art based on the embodiments of the present invention belong to the protection scope of the present invention without creative efforts.
The scheme provided by the invention is a timing synchronization method with large code bias resistance and low power consumption in satellite communication, as shown in figure 1, a feedback algorithm based on a digital phase-locked loop is adopted, an input signal is a digital baseband signal after digital down-conversion, and the ratio Fs/Fd of the sampling rate of the input signal to the code element rate can be any value more than or equal to 4.
In fig. 1, the interpolation filter performs interpolation calculation on an input signal by using an interpolation technique to obtain an optimal sampling point;
the matched filter is used for being matched with the shaping filter at the transmitting end to reduce intersymbol interference;
a timing error detector for calculating a timing error; the loop filter is used for reducing timing error jitter, filtering high-frequency noise and reducing interference; the timing error calibration operation calibrates the timing error by estimating the timing error change rate and compensates the data deviation caused by the calculation delay; the numerically controlled oscillator NCO is used for calculating an interpolation data position, and further an interpolation base point mk and a decimal interval uk required by interpolation are obtained. The shaping filter is adopted to eliminate intersymbol interference and meet the Nyquist characteristic without intersymbol interference. And secondly, smoothing the waveform to accelerate the out-of-band attenuation of the frequency spectrum of the modulation signal and improve the utilization rate of the frequency band, which is the basic requirement of the filter in the modulation system. In practical application, the square root raised cosine roll-off filter selected by the shaping filter.
The timing error detector is mainly used for calculating the timing error in the timing synchronization and provides the timing error to the numerical control oscillator after loop filtering for controlling the operation of the interpolation filter. The present invention employs a Gardner timing error detection algorithm. The algorithm can calculate the timing error by using continuous 3 sampling values, and the timing error calculation formula is as follows:
wherein, the superscripts i and q respectively represent real and imaginary parts,x k represents the best point of view of the current symbol,x k-1 represents the best observation point of the previous symbol, andx k-1/2 the next best observation point between two adjacent symbols.
The loop filter filters the timing error signal to reduce jitter of the timing error signal and reduce the influence of high-frequency noise. Fig. 2 shows a specific structural block diagram of the loop filter, and the calculation formula of the loop filter output can be seen from fig. 2 above:
y (n )=c1 *[x (n )-x (n -1)]+c2 *x (n)
wherein c1 and c2 are loop filter coefficients, and c1=0.0313 and c2=0.0039 are taken in the invention.
Numerically controlled oscillator NCO design is as follows: the timing error signal enters a numerical control oscillator after high-frequency noise is filtered by a filter, and an interpolation point position Pos (n) is iteratively calculated to generate an interpolation base point mk and a decimal interval uk which can control the operation of an interpolation filter. Fig. 3 is a block diagram of a digitally controlled oscillator configuration.
In the invention, the calculation formula for iteratively calculating the position of the interpolation point by the numerical control oscillator is as follows:
Pos(n)=Pos(n－1)+ω(n)
wherein ω (n) =T i /T s +err(n)， errAnd (n) is the filtered and calibrated timing error value.
From Posm k Andu k ，m k is an integer part of the Pos number,u k fractional part of Pos:
m k =int(Pos)
u k =Pos－m k
for example, in an ideal case, the timing error err (n) is 0, assuming that the initial value of Pos is 1.5,T i /T s =4, then the interpolation position for each time is:
Pos=1.5 mk=1，uk=0.5；
Pos=5.5 mk=5，uk=0.5；
Pos=9.5 mk=9，uk=0.5；
……
according to the embodiment of the invention, the timing error value obtained after loop filtering is not directly input into an NCO module of a numerically controlled oscillator (VCO) but is added with a timing error calibration operation to compensate data deviation brought by calculation delay, so that a correct timing synchronization function is realized.
The timing synchronization of the invention adopts a feedback algorithm based on a digital phase-locked loop, and the total processing process of the closed-loop algorithm is to use the timing error value of the previous moment and the input data of the current moment to carry out operation to obtain the timing synchronization interpolation result of the current moment, as shown in figure 4. In the figure, a data operation part A comprises a numerical control oscillator NCO and interpolation calculation, and an error operation part B comprises timing error detection and loop filtering.
Can be expressed as follows:
wherein t =1, 2, 3, 4 … …,x(t) The data is input for the present moment of time,e(t-1) is precedingThe result of the timing error calculation at a time,y(t) For the timing synchronization interpolation result at the current time,f() Is a data operation part a.
The operation process is easy to realize when software such as MATLAB is used for simulation, and the expected effect can be achieved; however, when the process is implemented by using hardware devices such as an FPGA, due to the implementation of a certain delay, the timing error calculation result at the previous time cannot be immediately used for the synchronous interpolation operation at the current time, and what actually participates in the synchronous interpolation operation is the timing error result of the current input data and the previous N time. As shown in fig. 5, the data operation part a is delayed by D1, the error operation part is delayed by D2, and the total delay of the entire loop is D1+ D2= N.
The delay in the specific implementation is about 22 clock cycles, i.e., N =22, when (1) becomes:
the timing error e (t) is proportional to the code bias, and as can be seen from the above equation, when the code bias is small, the timing error does not greatly differ over 22 clock cycles, i.e., the timing error is not greatly differente(t－23) ≈ e(t-1) this slight deviation does not affect the convergence of the feedback loop, which can work properly, when the timing synchronization can get the correct result. When the code offset is large, however, the timing error before and after 22 clock cycles is very different,e(t－23) ≠e(t-1) which can affect the convergence of the feedback loop or even render it ineffective, in which case the performance of the timing synchronization will be poor or even erroneous.
The working process of the feedback loop is a process of gradually converging through calculation of each part, if a large deviation occurs in the calculation result of a certain part, the convergence of the feedback loop is influenced, even the loop cannot converge, and therefore the whole timing synchronization function is invalid.
Aiming at the problems, the invention provides a solution that the timing error change rate is introduced in the feedback operationeTo compensate for the difference in time delayeIs 1 clock cycleThe variable quantity of the middle timing error ise=e(t)－e(t-1) thene(t－1)=e(t－23)+22∆eIn this case, equation (2) can be modified as follows:
the formula (3) is equivalent to the formula (1), so the expected timing synchronization effect can be obtained by the method, whereineThis can be found by taking the average of the rates of change of timing errors over hundreds of cycles.
The invention counts the average value of the timing error change rate of 256 clock periods to obtain the ΔeThen is toe= (e (t) -e (t-256))/256, here ΔeInstead of a fixed value, it is a time-varying quantity that participates in the operation throughout the feedback loop, gradually converging with the feedback loop, and finally converging to a stable value. As shown in fig. 8 (b).
After compensating data deviation caused by calculation delay, the NCO is used for calculating interpolation data positions to further obtain interpolation base points mk and decimal intervals uk required by interpolation, an interpolation filter calculates correct interpolation values, corresponding timing errors are calculated according to the interpolation values, high-frequency noise is filtered through loop filtering, the whole system works repeatedly according to the rule, feedback adjustment is carried out continuously, correct timing synchronization information is obtained finally, and a stable state is achieved.
The interpolation filter interpolation basic principle is schematically shown in fig. 9, and the sequence on the time axis in fig. 9 is the original sample data x (m)T s ) At a sampling interval ofT s (ii) a The sequence below the time axis is interpolated data y (k)T i ) With a sampling time interval ofT i ；m k In order to interpolate the base points,u k at fractional intervals, the following are defined:
m k =int(kT i /T s )
u k =kT i /T s －m k
digital interpolation filter based onm k Determining the original sampling sequence position corresponding to the interpolation point, and obtaining the sampling sequence data corresponding to the position andu k the interpolation results are jointly calculated. Interpolation base pointm k And decimal intervalu k Are calculated by a numerically controlled oscillator.
In a specific implementation, the invention selects a piecewise parabolic polynomial interpolation filter, and fig. 10 shows an implementation block diagram of the piecewise parabolic polynomial interpolation filter. The interpolation filter uses four successive input signals x (nearest to the optimal interpolation instant)m k －1)、x(m k )、x(m k +1)、x(m k + 2) and fractional interpolation positionu k To calculate the interpolated value y [ () (m k +u k )T s ]. Interpolation base pointm k And decimal intervalu k Are calculated from Numerically Controlled Oscillators (NCO).
The following 3 sets of diagrams are simulation results for the above discussion, fig. 6 is a timing synchronization result when the code offset =0.3% and the feedback delay =0, and (a) shows that the timing synchronization constellation is good, and (b) shows that the timing synchronization can be stably converged; fig. 7 shows the timing synchronization result before the algorithm is improved when the code offset =0.3% and the feedback delay =22, where (a) shows that the timing synchronization constellation is not distinguishable, and (b) shows that the timing synchronization is not converged; fig. 8 shows the timing synchronization result after the algorithm is improved when the code offset =0.3% and the feedback delay =22, and it can be seen from (a) that the timing synchronization constellation can achieve the same good effect as fig. 6 (a) at this time, and it can be seen from (b) and (c) that the timing synchronization can be stably converged, but the convergence speed is slower, but the performance index requirement can be satisfied.
Although illustrative embodiments of the present invention have been described above to facilitate the understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, but various changes may be apparent to those skilled in the art, and it is intended that all inventive concepts utilizing the inventive concepts set forth herein be protected without departing from the spirit and scope of the present invention as defined and limited by the appended claims.
Claims (6)
1. A timing synchronization method with large code bias resistance and low power consumption in satellite communication is characterized by comprising the following steps:
step 1, inputting a digital baseband signal subjected to digital down-conversion as an input signal in a feedback loop based on a digital phase-locked loop;
step 2, carrying out interpolation calculation on the input signal by using an interpolation filter to obtain an optimal sampling point, and outputting and connecting the optimal sampling point to a matched filter;
step 3, reducing intersymbol interference by using a matched filter to be matched with a forming filter of a transmitting end;
step 4, connecting a timing error detector to the output end of the matched filter, calculating a timing error, and inputting the timing error into the loop filter to reduce the timing error jitter for the detected timing error;
step 5, performing timing error calibration operation on the output signal of the loop filter, calibrating the timing error by estimating the change rate of the timing error, and compensating the data deviation caused by calculating the delay;
and 6, inputting the data after timing error calibration into a numerically-controlled oscillator NCO, calculating the position of the interpolated data, further obtaining an interpolated base point mk and a decimal interval uk required by interpolation, and feeding back the interpolated base point mk and the decimal interval uk obtained by the numerically-controlled oscillator to an interpolation filter.
2. The timing synchronization method of claim 1, wherein the timing error rate is introduced into the feedback operationeTo compensate for the difference in time delayeThe variation of the timing error in 1 clock cycle is obtained by counting the average value of the variation rate of the timing error in a plurality of cycles, so as to obtain the expected timing synchronization effect.
3. The method according to claim 1, wherein the interpolation filter is used for performing interpolation calculation on the input signal to obtain the optimal sampling point.
4. The method of claim 1, wherein the timing error calibration operation calibrates the timing error by estimating a rate of change of the timing error to compensate for a data bias caused by a computation delay.
5. The method of claim 1, wherein the square root raised cosine roll-off filter selected by the shaping filter is used for timing synchronization with high code bias resistance and low power consumption in satellite communication.
6. The method of claim 1, wherein the ratio of the input signal sampling rate to the symbol rate Fs/Fd is any value greater than or equal to 4.
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