CN115840484A - Linear voltage-stabilized power supply and power supply system - Google Patents
Linear voltage-stabilized power supply and power supply system Download PDFInfo
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Abstract
The application discloses linear voltage-stabilized power supply, linear voltage-stabilized power supply include unusual control module, start module, regulation module and output module. The abnormal control module is respectively connected with the voltage input end, the voltage output end and the starting module, the starting module is respectively connected with the first enabling signal end, the voltage input end and the first node, the regulating module is respectively connected with the voltage input end, the reference voltage end, the first node, the second node and the output module, and the output module is respectively connected with the second node, the voltage input end and the voltage output end. In the linear voltage-stabilized power supply of this application, detect input voltage and output voltage through setting up unusual control module to provide reset signal to the start module according to the relation between input voltage and the output voltage, thereby adjust first node voltage, second node voltage and output voltage, so, avoided linear voltage-stabilized power supply voltage output end the condition of overshoot to appear under unusual operating condition, be favorable to protecting voltage output end's safety.
Description
Technical Field
The application relates to the technical field of electronics, in particular to a linear voltage-stabilized power supply and a power supply system.
Background
In recent charging electronic devices, power is supplied through an integrated PMIC (Power Management IC), and thus a high demand is placed on a transient overshoot voltage of a system voltage. When the battery voltage is at the full charge voltage, the overshoot of the system transient cannot exceed 100 mv, i.e. the overshoot does not exceed 2.3%, and if the overshoot exceeds the value, the system chip may be damaged or burnt out.
For the above situation, transient overshoot is easily generated in the charging chip adopting the conventional voltage mode control manner and the conventional current mode control manner, which may cause great influence or even burnout on the operation of the PMIC of the mobile intelligent terminal.
Disclosure of Invention
The present application is directed to solving at least one of the problems in the prior art. Therefore, the application provides a linear voltage-stabilized power supply and a power supply system.
The embodiment of the application provides a linear voltage-stabilized power supply which is characterized by comprising an abnormal control module, a starting module, a regulating module and an output module;
the abnormal control module is respectively connected with a voltage input end, a voltage output end and the starting module, and is used for providing a reset signal for the starting module according to the input voltage of the voltage input end and the output voltage of the voltage output end;
the starting module is respectively connected with a first enabling signal end, the voltage input end and a first node, and is used for adjusting the voltage of the first node according to a first enabling signal of the first enabling signal end and the input voltage of the voltage input end and setting the voltage of the first node to zero according to the reset signal;
the adjusting module is respectively connected with the voltage input end, the reference voltage end, the first node, the second node and the output module, and is used for adjusting the voltage of the second node according to the voltage of the first node, the reference voltage of the reference voltage end and the input voltage of the voltage input end;
the output module is respectively connected with the second node, the voltage input end and the voltage output end, and the output module is used for providing the output voltage for the voltage output end according to the voltage of the second node and the input voltage of the voltage input end.
In certain embodiments, the anomaly control module comprises:
the first input end and the second input end of the comparator are respectively connected with the voltage input end and the voltage output end;
and a first pole and a second pole of the first transistor are respectively connected with the starting module and the grounding terminal, and a third pole of the first transistor is connected with the output end of the comparator.
In some embodiments, the initiation module comprises:
a first end of the starting capacitor is connected with the abnormal control module and the first node, and a second end of the starting capacitor is connected with a grounding end;
a first current mirror unit connected to the voltage input terminal and the first node, respectively;
and the first switch control unit is respectively connected with the first current mirror unit, the second enabling signal end, the grounding end and the first node.
In some embodiments, the first current mirror unit includes:
a second transistor having a first pole connected to the voltage input terminal and a second pole connected to the first and third switch control units;
a third transistor having a first pole connected to the voltage input terminal, a second pole connected to the first node, and a third pole connected to the third pole of the second transistor;
a fourth transistor, a first pole of the fourth transistor being connected to the voltage input terminal, a second pole of the fourth transistor being connected to the regulation module, and a third pole of the fourth transistor being connected to the second pole of the second transistor.
In some embodiments, the first switch control unit comprises:
a fifth transistor, a first pole of which is connected to the first current mirror unit, a second pole of which is connected to the ground terminal, and a third pole of which is connected to the second enable signal terminal;
and a sixth transistor, a first pole of which is connected to the first node, a second pole of which is connected to the ground terminal, and a third pole of which is connected to the second enable signal terminal.
In certain embodiments, the adjustment module comprises:
the error amplification unit is respectively connected with the first node, the reference voltage end, the first current mirror unit, the output module and a third node;
the active load unit is connected with the error amplification unit, the third node and a grounding end;
and the second-stage amplification unit is respectively connected with the voltage input end, the second node, the third node and the grounding end.
In some embodiments, the error amplification unit includes:
a seventh transistor, a first pole of which is connected to the voltage input terminal, a second pole of which is connected to the active load unit, and a third pole of which is connected to the first node;
an eighth transistor having a first electrode connected to the voltage input terminal, a second electrode connected to the active load unit, and a third electrode connected to the reference voltage terminal;
and a ninth transistor, a first pole of which is connected to the voltage input terminal, a second pole of which is connected to the third node, and a third pole of which is connected to the output module.
In some embodiments, the active load unit comprises:
a tenth transistor having a first electrode connected to the error amplifying unit, a second electrode connected to the ground, and a third electrode connected to the first electrode;
and an eleventh transistor having a first pole connected to the third node, a second pole connected to the ground, and a third pole connected to the tenth transistor.
In some embodiments, the two-stage amplification unit comprises:
a twelfth transistor having a first pole connected to the voltage input terminal, and second and third poles connected to the second node;
and a thirteenth transistor, wherein a first pole of the thirteenth transistor is connected to the second pole of the twelfth transistor, a second pole of the thirteenth transistor is connected to the ground, and a third pole of the thirteenth transistor is connected to the third node.
In some embodiments, the output module comprises:
a fourteenth transistor, a first pole of which is connected to the voltage input terminal, a second pole of which is connected to the output terminal, and a third pole of which is connected to the second node;
a first resistor, one end of which is connected to the second pole of the fourteenth transistor and the other end of which is connected to the error amplification unit;
one end of the second resistor is connected with the first resistor and the error amplification unit, and the other end of the second resistor is connected with a grounding terminal;
and the filter capacitor is respectively connected with the output end and the grounding end.
In certain embodiments, the anomaly control module further comprises:
the second current mirror unit is connected with the voltage input end, the fourth node and the grounding end;
the control unit is respectively connected with the fourth node, the voltage output end, the grounding end and the fifth node;
and the output unit is respectively connected with the fifth node, the starting module and the grounding terminal.
In some embodiments, the linear regulated power supply further comprises:
and the voltage reduction module is respectively connected with the voltage input end and the starting module.
In some embodiments, the second current mirror unit includes:
a fifteenth transistor, a first pole of which is connected to the voltage input terminal, and a second pole of which is connected to a third pole;
a sixteenth transistor having a first pole connected to the voltage input terminal and a third pole connected to the second pole of the fifteenth transistor;
a seventeenth transistor having a first pole connected to the second pole of the fifteenth transistor and a second pole connected to the third pole;
an eighteenth transistor having a first pole connected to the second pole of the sixteenth transistor, a second pole connected to the fourth node, and a third pole connected to the third pole of the seventeenth transistor;
and a nineteenth transistor, wherein a first pole of the nineteenth transistor is connected to a second pole of the seventeenth transistor, a second pole of the nineteenth transistor is connected to the ground terminal, and a third pole of the nineteenth transistor is connected to the step-down module.
In certain embodiments, the control unit comprises:
a twentieth transistor, a first pole of which is connected to the fourth node, a second pole of which is connected to the ground terminal, and a third pole of which is connected to the voltage output terminal;
a twenty-first transistor, a first pole of which is connected to the fourth node and a second pole of which is connected to the fifth node;
a twenty-second transistor, a first pole of the twenty-second transistor being connected to the voltage output terminal, a second pole of the twenty-second transistor being connected to the ground terminal, and a third pole of the twenty-first transistor being connected to the ground terminal.
In some embodiments, the output unit includes:
the voltage inverter is connected with the fifth node;
and a twenty-third transistor, wherein a first pole of the twenty-third transistor is connected to the first node, a second pole of the twenty-third transistor is connected to a ground terminal, and a third pole of the twenty-third transistor is connected to the voltage inverter.
In certain embodiments, the anomaly control module further comprises:
and the second switch control unit is respectively connected with the second enabling signal end, the voltage reduction module, the grounding end and the control unit.
In some embodiments, the second switch control unit comprises:
a twenty-fourth transistor, a first pole of which is connected to the buck module, a second pole of which is connected to the ground terminal, and a third pole of which is connected to a second enable signal terminal;
and a twenty-fifth transistor, a first pole of which is connected to the voltage-reducing module, a second pole of which is connected to the ground terminal, and a third pole of which is connected to the first pole and the control unit.
The application provides a power supply system comprising the linear voltage-stabilized power supply.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
Drawings
The above and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a schematic diagram of a linear regulated power supply of an embodiment of the present application;
FIG. 2 is a schematic diagram of a linear regulated power supply according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a linear regulated power supply of an embodiment of the present application;
fig. 4 is a schematic diagram of a power supply system according to an embodiment of the present application.
Description of the main element symbols:
<xnotran> 1000, 100, 10, 11, T1, 13, T15, T16, T17, T18, T19, 14, T20, T21, T22, 15, 151, T23, 16, T24, T25, 20, C1, 22, T2, T3, T4, 23, T5, T6, 30, 31, T7, T8, T9, 32, T10, T11, 33, T12, T13, 40, T14, R1, R2, C2, 50, VIN, VOUT, D1, D2, D3, D4, D5, E2, GND, VREF. </xnotran>
Detailed Description
Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative and are only for the purpose of explaining the present application and are not to be construed as limiting the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it should be noted that, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, a fixed connection, a detachable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the recitation of a first feature "on" or "under" a second feature may include the recitation of the first and second features being in direct contact, and may also include the recitation of the first and second features not being in direct contact, but being in contact with another feature between them. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Further, the present application may repeat reference numerals and/or reference letters in the various examples for simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or arrangements discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
At present, in order to avoid the risk of damage to the electronic device due to overshoot phenomenon occurring in the process of supplying power to the electronic device by the power supply system, an overshoot protection circuit is usually added into the power supply system, and the overshoot protection circuit can slowly increase the output voltage of the power supply system, so as to avoid the occurrence of the output overshoot phenomenon.
However, the conventional overshoot protection circuit only plays a role in slowing down the output process in the starting process, and if the input power is continuously turned on or off at the moment due to sudden poor contact or other specific conditions in practical application, the overshoot protection circuit still generates the output overshoot phenomenon, so that the electronic equipment is damaged.
Referring to fig. 1, the present application provides a linear regulator 100, wherein the linear regulator 100 includes an abnormality control module 10, a start-up module 20, a regulation module 30, and an output module 40.
The abnormality control module 10 is connected to the voltage input terminal VIN, the voltage output terminal VOUT, and the start module 20, respectively, and the abnormality control module 10 is configured to provide a reset signal to the start module 20 according to an input voltage of the voltage input terminal VIN and an output voltage of the voltage output terminal VOUT.
The start module 20 is respectively connected to a first enable signal terminal (not shown), a voltage input terminal VIN, and a first node D1, and the start module 20 is configured to adjust a voltage of the first node D1 according to the first enable signal of the first enable signal terminal and an input voltage of the voltage input terminal VIN, and set a voltage of the first node D1 to zero according to a reset signal.
The adjusting module 30 is respectively connected to the voltage input terminal VIN, the reference voltage terminal VREF, the first node D1, the second node D2, and the output module 40, and the adjusting module 30 is configured to adjust the voltage of the second node D2 according to the voltage of the first node D1, the reference voltage of the reference voltage terminal VREF, and the input voltage of the voltage input terminal VIN.
The output module 40 is connected to the second node D2, the voltage input terminal VIN, and the voltage output terminal VOUT, respectively, and the output module 40 is configured to provide an output voltage to the voltage output terminal VOUT according to the voltage of the second node D2 and the input voltage of the voltage input terminal VIN.
In linear constant voltage power supply 100 of this application, through setting up unusual control module 10 and detecting input voltage and output voltage to provide reset signal to start-up module 20 according to the relation between input voltage and the output voltage, thereby adjust first node D1 voltage, second node D2 voltage and output voltage, so, the condition that voltage output terminal VOUT appears overshooting under linear constant voltage power supply 100 unusual operating condition has been avoided, be favorable to protecting voltage output terminal VOUT's safety.
Specifically, the abnormality control module 10 is connected to the voltage input terminal VIN and the voltage output terminal VOUT, respectively, and the abnormality control module 10 is capable of detecting an input voltage of the voltage input terminal VIN and an output voltage of the voltage output terminal VOUT to determine whether the input voltage of the voltage input terminal VIN is abnormal, and generating a reset signal when the input voltage is abnormal, and transmitting the reset signal to the start module 20. For example, in the present application, when it is detected that the input voltage is greater than the output voltage, it is determined that the input voltage is normal, and the abnormal control module 10 does not provide the reset signal to the start module 20. When the abnormality control module 10 detects that the input voltage is less than the output voltage, it may be confirmed that the input voltage is in an abnormal state, and the abnormality control module 10 generates a reset signal and transmits the reset signal to the start module 20.
The start module 20 is respectively connected to the first node D1, a first enable signal terminal and a voltage input terminal VIN, where the first enable signal terminal is an enable signal input terminal and can control input of an enable signal, and in a normal case, the first enable signal terminal is active at high level, that is, the first enable signal terminal can send a first enable signal to the start module 20 in an EN =1, EN _b =0 state, it should be noted that the enable signal may be an enable signal, that is, when the start module 20 receives the first enable signal, the start module 20 may start, so that the input voltage of the voltage input terminal VIN is transmitted to the adjusting module 30 from the first node D1.
The adjusting module 30 is connected to the voltage input terminal VIN, the reference voltage terminal VREF, the first node D1, and the second node D2, respectively, so that the adjusting module 30 can adjust the voltage of the second node D2 according to the voltage of the first node D1 and the reference voltage of the reference voltage terminal VREF, where the reference voltage of the reference voltage terminal VREF is calibrated when leaving a factory, and the reference voltage terminal VREF can be configured according to specific conditions, which is not limited herein. When the first enable signal is at a high level, that is, when the start module 20 is turned on, and the voltage of the first node D1 is less than the reference voltage of the reference voltage terminal VREF, the adjusting module 30 may adjust the voltage of the first node D1 and the voltage of the second node D2, that is, the voltage of the second node D2 is increased slowly along with the voltage of the first node D1. During the operation of the starting module 20, the voltage of the first node D1 continuously increases, when the voltage of the first node D1 is greater than the reference voltage, the starting module 20 enters a failure state, and the regulating module 30 may start regulating the voltage of the reference voltage and the voltage of the second node D2 until the voltage of the second node D2 is stabilized. The output module 40 is connected to the second node D2, the voltage input terminal VIN, and the voltage output terminal VOUT, respectively, and the output module 40 can provide an output voltage to the voltage output terminal VOUT according to the input voltage and the voltage of the second node D2.
In some examples, when the first enable signal is at a high level, that is, when the start module 20 is turned on, and when the abnormal control module 10 determines that the circuit is in a normal state, that is, when the abnormal control module 10 detects that the input voltage is greater than the output voltage, the start module 20 operates normally, the adjusting module 30 may adjust the reference voltage of the reference voltage terminal VREF and the voltage of the output module 40, and the voltage of the output module 40 rises slowly, so that the output voltage VOUT rises slowly, and an output overcharge condition is avoided. When the abnormal control module 10 confirms that the circuit is in an abnormal state, that is, when the abnormal control module 10 detects that the input voltage is less than the output voltage, the abnormal control module 10 may send a reset signal to the start module 20, the start module 20 is connected to the first node D1, the start module 20 may set the voltage of the first node D1 to zero according to the reset signal, and adjust the voltage of the first node D1 and the voltage of the second node D2 through the adjustment module 30, so as to reduce the voltage of the second node D2, thereby reducing the output voltage of the output module 40. When the input voltage returns to normal, that is, the input voltage is greater than the output voltage, the voltage of the first node D1 rises slowly, and the voltage of the second node D2 rises slowly under the action of the regulating module 30, so as to increase the output voltage of the output module 40 slowly.
Referring to fig. 2, in some embodiments, the abnormality control module 10 includes a comparator 11 and a first transistor T1, a first input terminal and a second input terminal of the comparator 11 are respectively connected to the voltage input terminal VIN and the voltage output terminal VOUT, a first pole and a second pole of the first transistor T1 are respectively connected to the start module 20 and the ground terminal GND, and a third pole is connected to the output terminal of the comparator 11.
Specifically, the comparator 11 includes a first input terminal, a second input terminal, and an output terminal, and the comparator 11 is an electronic component that outputs different voltage results at the output terminal by comparing the voltage levels of the first input terminal and the second input terminal. The first transistor T1 includes a first pole, a second pole, and a third pole, and the transistors can be divided into N-type and P-type transistors according to the characteristics of the transistors, in the embodiment disclosed in the present application, the first transistor T1N-type transistor is described as an example, that is, in the embodiment of the present application, when the gate of the first transistor T1 receives a high level signal, the first pole and the second pole of the first transistor T1 are turned on.
Further, the comparator 11 may detect an input voltage of the voltage input terminal VIN and an output voltage of the voltage output terminal VOUT, when the input voltage is less than the output voltage, the abnormal control module 10 may confirm that the circuit is in an abnormal state, and send a reset signal to the start module 20, so that the voltage of the first node D1 is reduced to 0V, and meanwhile, the gate of the first transistor T1 receives a high level signal, that is, the third pole of the first transistor T1 receives the high level signal, the first pole and the second pole are turned on, the first pole is connected to the start module 20, the second pole is connected to the ground terminal GND, and the remaining power of the start module 20 may be discharged, so that the voltage of the first node D1 is 0.
In the embodiments of the present application, the transistors used may be thin film transistors, field effect transistors, or other switching devices having the same characteristics. The source and drain of the transistor used herein may be symmetrical in structure, so that there may be no difference in structure between the source and drain. In the embodiments of the present disclosure, in order to distinguish two poles of a transistor except for a gate, one of them is directly described as a first pole, and the other is directly described as a second pole, so that the source and the drain of all or part of the transistors in the embodiments of the present disclosure may be interchanged as necessary.
Thus, on the one hand, the abnormality control module 10 can be connected to the voltage input terminal VIN and the voltage output terminal VOUT by providing the comparator 11, and output different voltages, so as to control the on/off of the first transistor T1, and on the other hand, by providing the first transistor T1, the first pole is connected to the start module 20, and the second pole is connected to the ground terminal GND, so as to discharge the remaining power of the start module 20 when the circuit is abnormal.
Referring to fig. 2, in some embodiments, the starting module 20 includes a starting capacitor C1, a first current mirror unit 22 and a first switch control unit 23. The first end of the start capacitor C1 is connected to the abnormal control module 10 and the first node D1, the second end is connected to the ground terminal GND, the first current mirror unit 22 is connected to the voltage input terminal VIN and the first node D1, and the first switch control unit 23 is connected to the first current mirror unit 22, the second enable signal terminal E2, the ground terminal GND and the first node D1.
Specifically, the start capacitor C1 may be slowly charged by a current in the circuit, a first end of the start capacitor C1 is connected to the first transistor T1 and the first node D1, and a second end is connected to the ground GND. Under the condition that the starting module 20 normally operates, the starting capacitor C1 is slowly charged, the rising speed of the voltage of the first node D1 can be slowed down, and under the condition that the starting module 20 is in an abnormal state, the first transistor T1 is connected to the ground terminal GND, so that the electric quantity of the starting capacitor C1 can be discharged, and the voltage of the first node D1 is set to zero.
The first current mirror unit 22 may comprise a plurality of transistors, that is, a plurality of transistors may form the first current mirror unit 22, and the current mirror is a standard component commonly existing in an analog integrated circuit, and its controlled current is equal to the input reference current, that is, the input-output current transfer ratio is equal to 1, and is characterized in that the output current is a "copy" of the input current in a certain proportion, and is used for generating the bias current and serving as an active load. The first current mirror unit 22 is respectively connected to the voltage input terminal VIN and the first node D1, and it can be understood that the current output by the first current mirror unit 22 passes through the first node D1 to the starting capacitor C1, so that the starting capacitor C1 can be slowly charged.
The first switch control unit 23 may include a plurality of transistors, the first switch control unit 23 is respectively connected to the first current mirror unit 22, the second enable signal terminal E2, the ground terminal GND and the first node D1, and the first switch control unit 23 may control a current to flow to the ground terminal GND according to the enable signal to form a loop.
Therefore, the starting module 20 can slow down the rising speed of the voltage of the first node D1 by setting the starting capacitor C1, avoid circuit damage caused by sudden power-on, generate bias current and serve as an active load by setting the first current mirror unit 22, so that each circuit obtains the same current, and control the current flowing direction of the starting module 20 according to the enabling signal by setting the first switch control unit 23, thereby forming a current loop.
Referring to fig. 2, in some embodiments, the first current mirror unit 22 includes a second transistor T2, a third transistor T3 and a fourth transistor T4, a first pole of the second transistor T2 is connected to the voltage input terminal VIN, a second pole of the second transistor T2 is connected to the first switch control unit 23 and the third pole of the first transistor T3, a first pole of the third transistor T3 is connected to the voltage input terminal VIN, a second pole of the third transistor T3 is connected to the first node D1, a third pole of the third transistor T2 is connected to the third pole of the second transistor T2, a first pole of the fourth transistor T4 is connected to the voltage input terminal VIN, a second pole of the fourth transistor T4 is connected to the adjusting module 30, and a third pole of the fourth transistor T2 is connected to the second pole of the second transistor T2.
Specifically, the second transistor T2, the third transistor T3, and the fourth transistor T4 in this application may be transistors of the same type, the voltage input terminal VIN is respectively connected to the first pole of the second transistor T2, the first pole of the third transistor T3, and the first pole of the fourth transistor T4, and the second pole of the second transistor T2 is respectively connected to the third pole of the second transistor T2, the third pole of the third transistor T3, and the third pole of the fourth transistor T4, so that the three transistors can be turned on and off simultaneously. The second transistor T2 is connected to the first switch control unit 23, the third transistor T3 is connected to the first node D1, and the fourth transistor T4 is connected to the adjusting module 30, so that the first current mirror unit 22 can make the first switch control unit 23, the first node D1, and the adjusting module 30 form a current loop at the same time and obtain the same current.
Referring to fig. 2, in some embodiments, the first switch control unit 23 includes a fifth transistor T5 and a sixth transistor T6, a first pole of the fifth transistor T5 is connected to the first current mirror unit 22, a second pole of the fifth transistor T5 is connected to the ground terminal GND, a third pole of the fifth transistor T is connected to the second enable signal terminal E2, a first pole of the sixth transistor T6 is connected to the first node D1, a second pole of the sixth transistor T6 is connected to the ground terminal GND, and a third pole of the sixth transistor T6 is connected to the second enable signal terminal E2.
Specifically, the fifth transistor T5 may be a P-type transistor, a gate of the fifth transistor T5 is connected to the second enable signal terminal E2, that is, a third pole of the fifth transistor T5 is connected to the second enable signal terminal E2, a first pole of the fifth transistor T5 is connected to the first current mirror unit 22, a second pole of the fifth transistor T5 is connected to the ground terminal GND, and the on/off of the fifth transistor T5 may be controlled according to the second enable signal, so as to control the on/off of the current loop of the start module 20.
The sixth transistor T6 may be an N-type transistor, a first pole and a second pole of the sixth transistor T6 are respectively connected to the first node D1 and the ground GND, so as to form a loop with the start capacitor C1, a third pole of the sixth transistor T6 is connected to the second enable signal terminal E2, and the sixth transistor T6 may control on/off of the loop formed by the start capacitor C1 and the sixth transistor T6 according to the second enable signal.
It should be noted that the second enable signal terminal E2 of the present application is provided with an inverter so that the second enable signal is opposite to the first enable signal.
It is understood that the fifth transistor T5 is a P-type transistor, the sixth transistor T6 is an N-type transistor, and the fifth transistor T5 and the sixth transistor T6 are controlled to be turned on and off by the second enable signal in this application. When the second enable signal is EN =0 and EN _b =1, the fifth transistor T5 is connected, the sixth transistor T6 is disconnected, and the start module 20 is enabled by the current loop flowing through the start module 20. In the case that the second enable signal is EN =1, EN _b =0, the fifth transistor T5 is turned off, the current loop of the start module 20 is turned off, the sixth transistor T6 is turned on, and the start capacitor C1 may form a loop with the ground GND through the sixth transistor T6, so that the power of the start capacitor C1 may be discharged. Based on the description and the teaching of the present disclosure that the fifth transistor T5 is a P-type transistor and the sixth transistor T6 is an N-type transistor, a person skilled in the art can easily think of the implementation of the present disclosure that the fifth transistor T5 is an N-type transistor and the sixth transistor T6 is an N-type transistor without making creative work, and therefore, these implementations are also within the protection scope of the present disclosure.
In this way, by providing the fifth transistor T5 and the sixth transistor T6 in the first switch control unit 23, on one hand, the on/off of the fifth transistor T5 can be controlled according to the second enable signal, so as to control the on/off of the current loop of the starting module 20, and on the other hand, the on/off of the sixth transistor T6 can be controlled according to the second enable signal, so as to discharge the electric quantity of the starting capacitor C1 when the starting module 20 is turned off, thereby improving the safety and the service life of the circuit.
Referring to fig. 2, in some embodiments, the adjusting module 30 includes an error amplifying unit 31, an active load unit 32 and a secondary amplifying unit 33, the error amplifying unit 31 is respectively connected to the first node D1, the reference voltage terminal VREF, the first current mirror unit 22, the output module 40 and the third node D3, the active load unit 32 is connected to the error amplifying unit 31, the third node D3 and the ground terminal GND, and the secondary amplifying unit 33 is respectively connected to the voltage input terminal VIN, the second node D2, the third node D3 and the ground terminal GND.
Specifically, the error amplifying unit 31 is connected to the first current mirror unit 22 and the active load unit 32, the active load unit 32 is connected to the ground GND to form a current loop of the adjusting module 30, the error amplifying unit 31 is further connected to the first node D1, the output module 40 and the reference voltage terminal VREF, when the starting module 20 is started, the reference voltage of the reference voltage terminal VREF is already established, the error amplifying unit 31 can compensate the voltage of the first node D1 and the voltage of the output module 40, that is, the voltage of the output module 40 is slowly increased along with the voltage of the first node D1.
The active load unit 32 may be an output part of the first current mirror unit 22, and may be represented as a current source in an idealized manner, that is, when the voltage of the active load unit 32 varies, the output current remains unchanged. The active load unit 32 includes tenth and eleventh transistors T10 and T11. The first pole of the tenth transistor T10 is connected to the error amplifying unit 31, the second pole is connected to the ground terminal GND, the third pole is connected to the first pole, the first pole of the eleventh transistor T11 is connected to the third node, the second pole is connected to the ground terminal GND, and the third pole is connected to the third pole of the tenth transistor T10.
The secondary amplification unit 33 is connected to the voltage input terminal VIN and the ground terminal GND to form a current loop, the secondary amplification unit 33 is connected to the second node D2 and the third node D3, the second node D2 is connected to the output module 40, and in the process that the error amplification unit 31 compensates the voltage of the first node D1, the voltage of the third node D3 is slowly increased, so that the voltage of the second node D2 is increased along with the voltage of the third node D3, and the voltage of the output module 40 can be slowly increased. Further, the two-stage amplifying unit 33 includes a twelfth transistor T12 and a thirteenth transistor T13, a first pole of the twelfth transistor T12 is connected to the voltage input terminal VIN, a second pole and a third pole are connected to the second node D2, a first pole of the thirteenth transistor T13 is connected to the second pole of the twelfth transistor T12, the second pole is connected to the ground terminal GND, and the third pole is connected to the third node D3.
Thus, the regulating module 30 can compensate the voltage of the first node D1 and the voltage of the output module 40 by providing the error amplifying unit 31, the active load and the secondary amplifying unit 33, so that the voltage of the output module 40 is slowly increased, the overshoot of the voltage of the output module 40 is avoided, and the safety of the voltage output terminal VOUT is protected.
Referring to fig. 2, in some embodiments, the error amplifying unit 31 includes a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9.
A first electrode of the seventh transistor T7 is connected to the voltage input terminal VIN, a second electrode is connected to the active load unit 32, a third electrode is connected to the first node D1, a first electrode of the eighth transistor T8 is connected to the voltage input terminal VIN, a second electrode is connected to the active load unit 32, a third electrode is connected to the reference voltage terminal VREF, a first electrode of the ninth transistor T9 is connected to the voltage input terminal VIN, a second electrode is connected to the third node D3, and a third electrode is connected to the output module 40.
Specifically, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 may be P-type transistors of the same type, that is, in the case where the voltage of the first node D1 is less than the input voltage, the seventh transistor T7 is turned on. In case the reference voltage is smaller than the input voltage, the eighth transistor T8 is turned on. In case the output module 40 voltage is less than the input voltage, the ninth transistor T9 is turned on.
In this way, by providing the seventh transistor, the eighth transistor T8 and the ninth transistor T9 to form the error amplifying unit 31, the voltage of the first node D1 and the voltage of the output module 40 can be compensated, and the ninth transistor T9 is turned off when the voltage of the output module 40 is overcharged, so that the voltage of the output module 40 can be prevented from overshooting.
Referring to fig. 2, in some embodiments, the output module 40 includes a fourteenth transistor T14, a first resistor R1, a second resistor R2, and a filter capacitor C2. The first pole of the fourteenth transistor T14 is connected to the voltage input terminal VIN, the second pole is connected to the output terminal, the third pole is connected to the second node D2, one end of the first resistor R1 is connected to the second pole of the fourteenth transistor T14, the other end of the first resistor R1 is connected to the error amplification unit 31, one end of the second resistor R2 is connected to the first resistor R1 and the error amplification unit 31, the other end of the second resistor R2 is connected to the ground terminal GND, and the filter capacitor C2 is connected to the output terminal and the ground terminal GND, respectively.
Specifically, under the condition that the input voltage is less than the output voltage, the first transistor T1 is connected, the starting capacitor C1 and the ground terminal GND form a loop, the electric quantity of the starting capacitor C1 is discharged, the voltage of the first node D1 is set to zero, the seventh transistor T7 is connected and then short-circuits the eighth transistor T8, the error amplification unit 31 compensates the voltage difference between the voltage of the first node D1 and the voltage of the output module 40, because the voltage of the first node D1 is less than the voltage of the output module 40, the voltage of the third node D3 is pulled down to zero, the thirteenth transistor T13 is disconnected, the twelfth transistor T12 has no current flowing, the fourteenth transistor T14 is disconnected, and it is possible to avoid that when the input voltage is suddenly increased, a large amount of current passes through the fourteenth transistor T14 to cause the output terminal to be overcharged.
Further, under the condition that the input voltage is greater than the output voltage, the starting module 20 starts, the voltage of the first node D1 rises slowly, and the voltage of the third node D3 also rises slowly, so that the voltage of the second node D2 decreases slowly, and meanwhile, the fourteenth transistor T14 obtains a slowly increasing charging current and flows to the output terminal.
The first resistor R1 and the second resistor R2 may be feedback resistors for providing a feedback signal to the circuit, the feedback signal may be a voltage, a current, etc., and the circuit may adjust the input voltage according to the feedback signal of the first resistor R1 and the second resistor R2.
The filter capacitor C2 is connected in parallel to the output end of the circuit, and the filter capacitor C2 may be an energy storage device for reducing the ripple coefficient of the alternating current and smoothing the direct current output. The filter capacitor C2 can make the direct current output of the power supply smooth and stable, reduce the influence of alternating pulsating current on the circuit, and simultaneously can absorb the current fluctuation generated in the working process of the circuit and the interference of the alternating current power supply in series, so that the working performance of the circuit is more stable.
Therefore, the fourteenth transistor T14 can be used for controlling the voltage of the output end to slowly rise, so as to avoid the situation that the output end is overcharged, and the feedback signal of the circuit of the output module 40 can be obtained by setting the first resistor R1 and the second resistor R2, so as to adjust the input voltage according to the feedback signal, and the like, and by setting the filter capacitor C2, the influence of the alternating pulsating current on the circuit is reduced, and the stability of the working performance of the circuit can be improved.
Referring to fig. 2 and 3, in some embodiments, the abnormality control module 10 further includes a second current mirror unit 13, a control unit 14 and an output unit 15, the second current mirror unit 13 is connected to the voltage input terminal VIN, the fourth node D4 and the ground terminal GND, the control unit 14 is connected to the fourth node D4, the voltage output terminal VOUT, the ground terminal GND and the fifth node D5, and the output unit 15 is connected to the fifth node D5, the start module 20 and the ground terminal GND.
In some embodiments, linear regulated power supply 100 further includes a voltage step-down module 50, and voltage step-down module 50 is connected to voltage input terminal VIN and start-up module 20, respectively.
Specifically, the second current mirror unit 13 includes a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18 and a nineteenth transistor T19, a first pole of the fifteenth transistor T15 is connected to the voltage input terminal VIN, a second pole is connected to the third pole, a first pole of the sixteenth transistor T16 is connected to the voltage input terminal VIN, a third pole is connected to the second pole of the fifteenth transistor T15, a first pole of the seventeenth transistor T17 is connected to the second pole of the fifteenth transistor T15, a second pole is connected to the third pole, a first pole of the eighteenth transistor T18 is connected to the second pole of the sixteenth transistor T16, a second pole is connected to the fourth node D4, a third pole is connected to the third pole of the seventeenth transistor T17, a first pole of the nineteenth transistor T19 is connected to the second pole of the seventeenth transistor T17, a third pole is connected to the ground terminal GND, and a third pole is connected to the voltage-dropping module 50. Among them, the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17, and the eighteenth transistor T18 may be P-type transistors, the nineteenth transistor T19 may be N-type transistors, and the eighteenth transistor T18 and the nineteenth transistor T19 may function to withstand high voltage. It can be understood that the specific features of the second current mirror unit 13 are substantially the same as those of the first current mirror unit 22, and are not described herein again.
The control unit 14 includes a twentieth transistor T20, a twenty-first transistor T21, and a twenty-second transistor T22, the first pole of the twentieth transistor T20 is connected to the fourth node D4, the second pole is connected to the ground terminal GND, the third pole is connected to the voltage output terminal VOUT, the first pole of the twenty-first transistor T21 is connected to the fourth node D4, the second pole is connected to the fifth node D5, the first pole of the twenty-second transistor T22 is connected to the voltage output terminal VOUT, the second pole is connected to the ground terminal GND, and the third pole is connected to the third pole and the ground terminal GND of the twenty-first transistor T21. The twentieth transistor T20, the twenty-first transistor T21, and the twenty-second transistor T22 may be P-type transistors.
The output unit 15 includes a voltage inverter 151 and a twenty-third transistor T23, the voltage inverter 151 is connected to the fifth node D5, a first pole of the twenty-third transistor T23 is connected to the first node D1, a second pole is connected to the ground terminal GND, and a third pole is connected to the voltage inverter 151. The voltage inverter 151 may reversely output the voltage signal, that is, when the voltage signal is at a high level, the voltage signal is output as a low level through the voltage inverter 151, and when the voltage signal is at a low level, the voltage signal is output as a high level through the voltage inverter 151. The twenty-third transistor T23 may be an N-type transistor.
When the input voltage is high, the buck module 50 may convert the input voltage to an internally powered low voltage, and the buck module 50 may include a voltage regulator that may cause a transistor or fet operating in a saturation region to subtract excess voltage from the applied input voltage to produce a regulated output voltage.
Further, in a case that the input voltage is less than the output voltage, that is, when the voltage of the fourth node D4 is less than the output voltage, the voltage of the fifth node D5 is lowered, the voltage signal of the fifth node D5 is converted to a high level through the voltage inverter 151 and is output to the twenty-third transistor T23, so that the twenty-third transistor T23 is connected, the voltage of the first node D1 is set to zero, the error amplifying unit 31 compensates for a voltage difference between the first node D1 and the output module 40, and the twelfth transistor T12 is turned off, so that no current flows to the voltage output terminal VOUT through the fourteenth transistor T14. When the input voltage is restored to be greater than the output voltage, the voltage of the fifth node D5 slowly increases along with the voltage of the fourth node D4, and the voltage signal of the fifth node D5 is converted to a low level through the voltage inverter 151, so that the twenty-third transistor T23 is turned off, and the start module 20 operates normally.
In this way, by providing the second current mirror unit 13, the control unit 14, the output unit 15 and the voltage reduction module 50, when the input voltage is a high voltage, the low voltage of the input voltage for supplying power to the inside can be reduced by the voltage reduction module 50, and the current of the circuit of the abnormal control module 10 can be controlled by the second current mirror unit 13, the control unit 14 controls the on/off of the current, and the output module 40 provides a reset signal for the start unit, so that the linear regulated power supply 100 is suitable for the case where the input voltage is a high voltage, and it is ensured that the voltage output terminal VOUT of the linear regulated power supply 100 does not overshoot in the abnormal operating state.
Referring to fig. 2 and fig. 3, in some embodiments, the abnormal control module 10 further includes a second switch control unit 16, and the second switch control unit 16 is respectively connected to the second enable signal terminal E2, the voltage-reducing module 50, the ground terminal GND and the control unit 14.
Specifically, the second switch control unit 16 includes a twenty-fourth transistor T24 and a twenty-fifth transistor T25, a first pole of the twenty-fourth transistor T24 is connected to the voltage-reducing module 50, a second pole is connected to the ground terminal GND, a third pole is connected to the second enable signal terminal E2, a first pole of the twenty-fifth transistor T25 is connected to the voltage-reducing module 50, a second pole is connected to the ground terminal GND, and a third pole is connected to the first pole and the control unit 14.
Further, the twenty-fourth transistor T24 and the twenty-fifth transistor T25 may be N-type transistors, and in a case where the second enable signal is EN =0, EN _b =1, the twenty-fourth transistor T24 is turned off, the current flowing out of the voltage dropping module 50 acts on the twenty-fifth transistor T25, and the on/off of the circuit of the control unit 14 is controlled by the twenty-fifth transistor T25. When the second enable signal is EN =1, EN _b =0, the twenty-fourth transistor T24 is turned on, and the current flowing out of the voltage step-down module 50 enters the ground GND through the twenty-fourth transistor T24, thereby forming a loop.
In this way, by providing the second switch control unit 16 and connecting the second enable signal terminal E2, the voltage reduction module 50, the ground terminal GND and the control unit 14 respectively, on the one hand, the second switch control unit 16 can control the on/off of the circuit of the control unit 14, and on the other hand, the on/off of the twenty-fourth transistor T24 can be controlled according to the second enable signal, so that the voltage reduction module 50 is connected to the ground terminal GND when the start module 20 is turned off, thereby improving the safety and the service life of the circuit.
Referring to fig. 4, the present application further provides a power supply system 1000, wherein the power supply system 1000 includes a linear regulator 100.
In the power supply system 1000 of the present application, the linear voltage-stabilized power supply 100 detects the input voltage and the output voltage by setting the abnormal control module 10, and provides the reset signal to the start module 20 according to the relationship between the input voltage and the output voltage, thereby adjusting the voltage of the first node D1, the voltage of the second node D2, and the output voltage, so that the overshoot condition of the voltage output terminal VOUT of the linear voltage-stabilized power supply 100 in the abnormal working state is not generated, and the safety of the voltage output terminal VOUT is protected.
In the description herein, references to the description of the terms "one embodiment," "certain embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present application have been shown and described, it will be understood by those of ordinary skill in the art that: numerous changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the application, the scope of which is defined by the claims and their equivalents.
Claims (18)
1. A linear voltage-stabilized power supply is characterized by comprising an abnormal control module, a starting module, a regulating module and an output module;
the abnormality control module is respectively connected with a voltage input end, a voltage output end and the starting module, and is used for providing a reset signal for the starting module according to the input voltage of the voltage input end and the output voltage of the voltage output end;
the starting module is respectively connected with a first enabling signal end, the voltage input end and a first node, and is used for adjusting the voltage of the first node according to a first enabling signal of the first enabling signal end and the input voltage of the voltage input end and setting the voltage of the first node to zero according to the reset signal;
the adjusting module is respectively connected with the voltage input end, the reference voltage end, the first node, the second node and the output module, and is used for adjusting the voltage of the second node according to the voltage of the first node, the reference voltage of the reference voltage end and the input voltage of the voltage input end;
the output module is respectively connected with the second node, the voltage input end and the voltage output end, and the output module is used for providing the output voltage for the voltage output end according to the voltage of the second node and the input voltage of the voltage input end.
2. The linear regulated power supply of claim 1, wherein the exception control module comprises:
the first input end and the second input end of the comparator are respectively connected with the voltage input end and the voltage output end;
and a first pole and a second pole of the first transistor are respectively connected with the starting module and the grounding terminal, and a third pole of the first transistor is connected with the output end of the comparator.
3. The linear regulated power supply of claim 1, wherein the start module comprises:
a first end of the starting capacitor is connected with the abnormal control module and the first node, and a second end of the starting capacitor is connected with a grounding end;
a first current mirror unit connected to the voltage input terminal and the first node, respectively;
and the first switch control unit is respectively connected with the first current mirror unit, the second enabling signal end, the grounding end and the first node.
4. The linear regulated power supply of claim 3, wherein the first current mirror unit comprises:
a second transistor having a first pole connected to the voltage input terminal and a second pole connected to the first and third switch control units;
a third transistor having a first pole connected to the voltage input terminal, a second pole connected to the first node, and a third pole connected to the third pole of the second transistor;
a fourth transistor, a first pole of the fourth transistor being connected to the voltage input terminal, a second pole of the fourth transistor being connected to the regulation module, and a third pole of the fourth transistor being connected to the second pole of the second transistor.
5. The linear regulated power supply of claim 3, wherein the first switch control unit comprises:
a fifth transistor, a first pole of which is connected to the first current mirror unit, a second pole of which is connected to the ground terminal, and a third pole of which is connected to the second enable signal terminal;
and a sixth transistor, a first pole of which is connected to the first node, a second pole of which is connected to the ground terminal, and a third pole of which is connected to the second enable signal terminal.
6. The linear regulated power supply of claim 3, wherein the regulation module comprises:
the error amplification unit is respectively connected with the first node, the reference voltage end, the first current mirror unit, the output module and a third node;
the active load unit is connected with the error amplification unit, the third node and a grounding end;
and the second-stage amplification unit is respectively connected with the voltage input end, the second node, the third node and the grounding end.
7. The linear regulated power supply of claim 6, wherein the error amplification unit comprises:
a seventh transistor having a first electrode connected to the voltage input terminal, a second electrode connected to the active load unit, and a third electrode connected to the first node;
an eighth transistor having a first electrode connected to the voltage input terminal, a second electrode connected to the active load unit, and a third electrode connected to the reference voltage terminal;
and a ninth transistor, a first pole of which is connected to the voltage input terminal, a second pole of which is connected to the third node, and a third pole of which is connected to the output module.
8. The linear regulated power supply of claim 6, wherein the active load unit comprises:
a tenth transistor, a first pole of which is connected to the error amplifying unit, a second pole of which is connected to the ground terminal, and a third pole of which is connected to the first pole;
and an eleventh transistor having a first pole connected to the third node, a second pole connected to the ground, and a third pole connected to the tenth transistor.
9. The linear regulated power supply of claim 6, wherein the secondary amplification unit comprises:
a twelfth transistor having a first pole connected to the voltage input terminal, and second and third poles connected to the second node;
and a thirteenth transistor, wherein a first pole of the thirteenth transistor is connected to a second pole of the twelfth transistor, a second pole of the thirteenth transistor is connected to the ground, and a third pole of the thirteenth transistor is connected to the third node.
10. The linear regulated power supply of claim 6, wherein the output module comprises:
a fourteenth transistor, a first pole of which is connected to the voltage input terminal, a second pole of which is connected to the output terminal, and a third pole of which is connected to the second node;
a first resistor, one end of which is connected to the second pole of the fourteenth transistor and the other end of which is connected to the error amplification unit;
one end of the second resistor is connected with the first resistor and the error amplification unit, and the other end of the second resistor is connected with a grounding end;
and the filter capacitor is respectively connected with the output end and the grounding end.
11. The linear regulated power supply of claim 1, wherein the exception control module further comprises:
the second current mirror unit is connected with the voltage input end, the fourth node and the grounding end;
the control unit is respectively connected with the fourth node, the voltage output end, the grounding end and the fifth node;
and the output unit is respectively connected with the fifth node, the starting module and the grounding terminal.
12. The linear regulated power supply of claim 11, further comprising:
and the voltage reduction module is respectively connected with the voltage input end and the starting module.
13. The linear regulated power supply of claim 12, wherein the second current mirror unit comprises:
a fifteenth transistor, a first pole of which is connected to the voltage input terminal, and a second pole of which is connected to a third pole;
a sixteenth transistor, wherein a first pole of the sixteenth transistor is connected to the voltage input terminal, and a third pole of the sixteenth transistor is connected to the second pole of the fifteenth transistor;
a seventeenth transistor having a first pole connected to the second pole of the fifteenth transistor and a second pole connected to the third pole;
an eighteenth transistor having a first pole connected to the second pole of the sixteenth transistor, a second pole connected to the fourth node, and a third pole connected to the third pole of the seventeenth transistor;
and a nineteenth transistor, wherein a first pole of the nineteenth transistor is connected to a second pole of the seventeenth transistor, a second pole of the nineteenth transistor is connected to the ground terminal, and a third pole of the nineteenth transistor is connected to the step-down module.
14. The linear regulated power supply of claim 12, wherein the control unit comprises:
a twentieth transistor, a first pole of which is connected to the fourth node, a second pole of which is connected to the ground terminal, and a third pole of which is connected to the voltage output terminal;
a twenty-first transistor, a first pole of which is connected to the fourth node and a second pole of which is connected to the fifth node;
a twenty-second transistor, wherein a first pole of the twenty-second transistor is connected to the voltage output terminal, a second pole of the twenty-second transistor is connected to the ground terminal, and a third pole of the twenty-first transistor is connected to the third pole of the twenty-first transistor and the ground terminal.
15. The linear regulated power supply of claim 12, wherein the output unit comprises:
the voltage inverter is connected with the fifth node;
and a twenty-third transistor, wherein a first pole of the twenty-third transistor is connected to the first node, a second pole of the twenty-third transistor is connected to a ground terminal, and a third pole of the twenty-third transistor is connected to the voltage inverter.
16. The linear regulated power supply of claim 12, wherein the exception control module further comprises:
and the second switch control unit is respectively connected with the second enabling signal end, the voltage reduction module, the grounding end and the control unit.
17. The linear regulated power supply of claim 16, wherein the second switch control unit comprises:
a twenty-fourth transistor, a first pole of which is connected to the buck module, a second pole of which is connected to the ground terminal, and a third pole of which is connected to a second enable signal terminal;
and a twenty-fifth transistor, a first pole of which is connected to the voltage-reducing module, a second pole of which is connected to the ground terminal, and a third pole of which is connected to the first pole and the control unit.
18. A power supply system comprising a linear regulated power supply according to any one of claims 1 to 17.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117392951A (en) * | 2023-12-05 | 2024-01-12 | 上海视涯技术有限公司 | Power supply detection circuit, silicon-based display panel and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117392951A (en) * | 2023-12-05 | 2024-01-12 | 上海视涯技术有限公司 | Power supply detection circuit, silicon-based display panel and display device |
| CN117392951B (en) * | 2023-12-05 | 2024-03-19 | 上海视涯技术有限公司 | Power supply detection circuit, silicon-based display panel and display device |
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