CN115827502A - Memory access system, method and medium - Google Patents
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Abstract
The application provides a memory access system, method and medium, relate to the technical field of data processing, the system includes: at least one processor configured to send a memory access request to access a memory larger than a physical address space accessible by the processor; the memory manager is connected with the at least one processor and used for converting the virtual address in the received memory access request into a corresponding physical address of the memory to be accessed; and the storage system is connected with the memory manager through a bus and used for receiving a memory access request which is sent by the memory manager and carries a physical address, acquiring data corresponding to the physical address from a memory to be accessed and sending the data to the memory manager. The system can utilize the memory manager mounted under the processor to map the virtual address and the physical address, so that the 32-bit CPU with a specific structure can access the memory space higher than 4G.
Description
Technical Field
The present application relates to the field of data processing technologies, and in particular, to a memory access system, method, and medium.
Background
A System on Chip (SoC) is a System or product formed by combining a plurality of integrated circuits with specific functions on one Chip, and has a space in which a 32-bit Central Processing Unit (CPU) and a 64-bit CPU coexist, and the memory space is usually larger than 4G. Of these, 64-bit CPUs can access all memory spaces using physical addresses, but 32-bit CPUs can access only 4G-sized memory spaces using physical addresses.
The prior art solution to the above problem can only solve the problem that part of 32-bit CPUs access a memory space higher than 4G, and cannot be applied to all 32-bit CPUs. Therefore, the 32-bit CPU with a current part of specific architecture still cannot access the memory space higher than 4G.
Disclosure of Invention
The application provides a memory access system, a method and a medium, wherein a memory manager is mounted under a processor, and a virtual address of the processor is converted into a physical address of a memory to be accessed by the memory manager, so that a 32-bit CPU with a specific architecture can access a memory space higher than 4G.
In a first aspect, an embodiment of the present application provides a memory access system, including: at least one processor, configured to send a memory access request to access a memory larger than a physical address space accessible to the processor, where the memory access request includes a virtual address and identification information corresponding to the processor; the memory manager is connected with the at least one processor and used for determining a target translation page table corresponding to any processor according to identification information in a memory access request sent by any processor, and converting a virtual address in the received memory access request into a corresponding physical address of a memory to be accessed according to the target translation page table, wherein the virtual address space corresponding to the virtual address of the processor is smaller than the physical address space corresponding to the physical address of the memory to be accessed; and the storage system is connected with the memory manager through a bus and used for receiving a memory access request which is sent by the memory manager and carries a physical address, acquiring data corresponding to the physical address from a memory to be accessed and sending the data to the memory manager.
According to the memory access system, the virtual address in the memory access request is converted into the physical address corresponding to the memory to be accessed through the memory manager, so that the effect of accessing the memory space higher than 4G by using the 32-bit processor is achieved.
In an optional implementation manner, the memory manager includes a Translation Control Unit (TCU), at least one Translation Buffer Unit (TBU), and a Distributed Transmission Interface (DTI) corresponding to each Translation Buffer Unit and connecting the Translation Buffer Unit and the Translation control Unit; wherein each processor is connected with at least one translation buffer unit, and each translation buffer unit is connected with a unique processor; each Translation Buffer unit is configured to receive a memory access request sent by a processor connected to the Translation Buffer unit, convert a virtual address in the memory access request sent by the processor into a physical address corresponding to a memory to be accessed in the storage system according to a target Translation page Table in a flow Table Entry when determining that the flow Table Entry (STE) corresponding to the processor exists in a Translation Lookaside Buffer (TLB), and send the physical address to the storage system; the translation control unit is configured to, when any translation buffer unit determines that a flow entry corresponding to the processor does not exist in the page table buffer, search a flow entry corresponding to the processor from a flow entry storage area of the storage system, and send the searched flow entry to any translation control unit.
An optional implementation manner is that the identification information includes first identification information for identifying a processor that sends the memory access request; the translation buffer unit is configured to: receiving a memory access request sent by a processor connected with the translation buffer unit, and searching a flow entry corresponding to the processor from a page table buffer area; acquiring a flow entry corresponding to the processor from the translation control unit when it is determined that the flow entry corresponding to the processor is not searched in the page table buffer; when determining that the flow table entry corresponding to the processor is found from the page table buffer area, determining an address conversion mode corresponding to the processor according to the found flow table entry, and determining a target translation page table corresponding to the processor according to the address conversion mode.
In an optional implementation manner, the translation control unit is configured to: receiving a flow table entry acquisition request sent by any translation cache unit, and searching a flow table entry corresponding to the processor from a flow table entry storage area of the storage system according to first identification information carried in the flow table entry acquisition request; and when the flow table entry corresponding to the processor is found, sending the found flow table entry to any translation cache unit.
An optional implementation manner is that, when the address conversion mode is the first conversion mode, the identification information further includes second identification information used for determining a target Context Descriptor (CD) corresponding to the processor, and the translation buffer unit is specifically configured to: determining a target context descriptor corresponding to the processor from among a plurality of context descriptors stored in the flow entry, based on the second identification information; and determining a target translation page table corresponding to the processor according to the pointer in the target context descriptor.
An optional implementation manner is that, when the address conversion mode is the second conversion mode, the translation buffer unit is specifically configured to: determining a target base address of a target translation page table corresponding to the processor from the flow table entry; and determining a target translation page table corresponding to the processor according to the target base address.
In an optional implementation manner, when the address conversion mode is a third conversion mode, the identification information further includes second identification information for determining a target context descriptor corresponding to the processor, and the target translation page table includes a first translation page table for converting a virtual address of the processor into an intermediate address and a second translation page table for converting the intermediate address corresponding to the processor into a physical address of a memory to be accessed; the translation buffer unit is specifically configured to: determining a target context descriptor corresponding to the processor from among a plurality of context descriptors stored in the flow entry, based on the second identification information; determining a first translation page table corresponding to the processor according to the pointer in the target context descriptor; determining a target base address of a second translation page table corresponding to the processor from the flow table entry; and determining a second translation page table corresponding to the processor according to the target base address.
In a second aspect, an embodiment of the present application provides a memory access method, which is applied to a memory manager in the memory access system, and the method includes: receiving a memory access request sent by a target processor, wherein the memory access request comprises a virtual address and identification information corresponding to the target processor; searching a target translation page table corresponding to the target processor from a translation page table set according to the identification information; the translation page table set stores a mapping relation between a virtual address of at least one processor and a physical address of a corresponding memory to be accessed, wherein a virtual address space corresponding to the virtual address of the at least one processor is smaller than a physical address space corresponding to the physical address of the corresponding memory to be accessed; converting the virtual address in the memory access request into a physical address of a memory to be accessed according to the mapping relation in the target translation page table; and sending a memory access request carrying the physical address of the memory to be accessed to the storage system, so that the storage system acquires data corresponding to the physical address in the memory to be accessed according to the physical address of the memory to be accessed and sends the data to the memory manager.
The method is used for solving the problem that a 32-bit CPU of a part of specific architecture cannot access a space higher than 4G at present, the memory manager is mounted under the processor, the high-bit physical address is mapped to a virtual address lower than 4GB by configuring the mapping relation between the virtual address and the physical address, the virtual address in the memory access request of the part of 32-bit processor is converted into a physical address corresponding to a memory to be accessed, the processor can access the high-bit address only by accessing the virtual address, and the 32-bit processor of the specific architecture can access the space higher than 4G.
An optional implementation manner is that, before receiving a memory access request sent by a target processor, the method further includes: receiving an instruction for refreshing a target translation page table corresponding to the target processor, wherein the instruction comprises a first mapping relation between a virtual address corresponding to the target processor and a physical address of a corresponding memory to be accessed; and refreshing the mapping relation in the target translation page table corresponding to the processor in the translation page table set by using the first mapping relation.
According to the method, before the memory access request is received, the current target translation page table is refreshed according to the mapping relation carried by the target translation page table refreshing indication corresponding to the target processor, and the accuracy of the address conversion result in the subsequent memory access process is guaranteed.
In a third aspect, an embodiment of the present application provides a memory access apparatus, including: a receiving unit, configured to receive a memory access request sent by a target processor, where the memory access request includes a virtual address and identification information corresponding to the target processor; a determining unit, configured to search a target translation page table corresponding to the target processor from a translation page table set according to the identification information; the translation page table set stores a mapping relation between a virtual address of at least one processor and a physical address of a corresponding memory to be accessed, wherein a virtual address space corresponding to the virtual address of the at least one processor is smaller than a physical address space corresponding to the physical address of the corresponding memory to be accessed; a conversion unit, configured to convert a virtual address in the memory access request into a physical address of a memory to be accessed according to a mapping relationship in the target translation page table; and the sending unit is used for sending the memory access request carrying the physical address of the memory to be accessed to the storage system, so that the storage system obtains the data corresponding to the physical address in the memory to be accessed according to the physical address of the memory to be accessed and sends the data to the memory manager.
In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which computer program instructions are stored, and when the computer program instructions are executed by a processor, the computer program instructions implement any step of the memory access method in the second aspect.
In a fifth aspect, an embodiment of the present application provides a computer program product, including a computer program, where the computer program is stored in a computer-readable storage medium; when the processor of the memory access device reads the computer program from the computer-readable storage medium, the processor executes the computer program, so that the memory access device performs any one of the steps of the memory access method in the second aspect described above.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present application, and it is obvious for those skilled in the art that other drawings may be obtained according to these drawings without inventive labor.
FIG. 1 is a diagram illustrating a processor access scope according to an embodiment of the present application;
fig. 2 is a schematic diagram of a memory access system according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram illustrating an effect of a memory access method according to an embodiment of the present application;
fig. 4 is a schematic flowchart of a memory access method according to an embodiment of the present application;
fig. 5 is a schematic diagram of a memory manager pre-configuration process according to an embodiment of the present disclosure;
fig. 6 is a schematic flowchart of a page table refreshing method according to an embodiment of the present application;
fig. 7 is a schematic diagram of a memory access device according to an embodiment of the present application;
fig. 8 is a schematic view of an electronic device according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more clear, the present application will be further described in detail with reference to the accompanying drawings.
The application scenario described in the embodiment of the present application is for more clearly illustrating the technical solution of the embodiment of the present application, and does not form a limitation on the technical solution provided in the embodiment of the present application, and it can be known by a person skilled in the art that with the occurrence of a new application scenario, the technical solution provided in the embodiment of the present application is also applicable to similar technical problems. In the description of the present application, the term "plurality" means two or more unless otherwise specified.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Fig. 1 is a schematic diagram of a processor access scope according to an embodiment of the present application. As shown in fig. 1, in the SoC space, a 32-bit CPU coexists with a 64-bit CPU, and the 64-bit CPU can access a 36G-sized space using a physical address, whereas the 32-bit CPU can access a 4G-sized memory space using only a physical address. Since memory space is typically larger than 4G, a 32-bit CPU typically cannot access the entire memory space using physical addresses.
In chip design, bootrom is used as a boot program, generally burned in ROM in the form of firmware, and operated in a 32-bit CPU. Since the CPU running the Bootrom boot program can only access the 4G space corresponding to the 32-bit address width and cannot access other spaces in the memory space, a new design scheme is required to re-plan the mapping of the address.
Based on the foregoing problems, at least one embodiment of the present application provides a Memory access system, a method, and a medium, where for a CPU with a specific architecture, for example, a 32-bit CPU without a Memory Management Unit (MMU), an extra Memory manager is mounted under a processor to reconstruct a mapping relationship between a virtual address and a physical address, so that a virtual address carried in a Memory access request sent by the processor can be converted into a physical address of a Memory to be accessed by using an address conversion function from the virtual address to the physical address of the newly-added Memory manager, thereby achieving an effect of accessing a high-bit Memory space by using a low-bit processor.
Fig. 2 is a schematic diagram of a memory access system according to an embodiment of the present disclosure, and as shown in fig. 2, the memory access system according to the embodiment of the present disclosure includes at least one processor 201, a memory manager 202, and a storage system 203.
At least one processor 201, configured to send a memory access request to access a memory larger than a physical address space accessible by the processor 201, where the memory access request includes a virtual address and identification information corresponding to the processor 201. The processor includes, but is not limited to, a CPU.
The memory manager 202 is connected to at least one processor 201, and configured to determine a target translation page table corresponding to any processor according to identification information in a memory access request sent by any processor 201, and convert a virtual address in the received memory access request into a corresponding physical address of the memory to be accessed according to the target translation page table, where a virtual address space corresponding to a virtual address of the processor is smaller than a physical address space corresponding to a physical address of the memory to be accessed.
In an alternative embodiment, the memory manager 202 is disposed between the processor and the bus, and implements the conversion from the virtual address to the physical address. In performing address translation, address translation from an input address to an output address is described as a stage (stage) of address translation, which may be specifically configured with the following address translation modes: bypass (bypass) mode: in this mode, no conversion is performed, and the input address is directly accessed as a physical address. Stage one (stage 1) mode: the input virtual address is translated to a physical address or an Intermediate Physical Address (IPA). Stage two (stage 2) mode: converting the input virtual address or the intermediate physical address into a physical address. Stage one and stage two (stage 1 and stage 2) modes: the virtual address is converted into an intermediate physical address at Stage1, and then the intermediate physical address is used as the input of Stage2 and is converted into an actual physical address.
The storage system 203 is connected to the memory manager 202 through the bus 204, and is configured to receive a memory access request carrying a physical address sent by the memory manager 202, obtain data corresponding to the physical address from a memory to be accessed, and send the data to the memory manager 202.
The working principle of the memory access system in the embodiment of the present application is described below by taking a possible form of a memory manager as an example.
In some optional embodiments, as shown in fig. 2, the memory manager 202 includes a translation control unit 2023, at least one translation buffer unit 2021, and a distributed transmission interface 2022 corresponding to each translation buffer unit 2021 and connecting the translation buffer unit 2021 and the translation control unit 2023;
wherein, each processor 201 is connected with at least one translation buffer unit 2021, and each translation buffer unit 2021 is connected with a unique processor 201; that is, each translation buffer unit 2021 corresponds to a unique processor 201, but one processor 201 may be connected to a plurality of translation buffer units 2021.
Each translation buffer unit 2021 is configured to receive a memory access request sent by the processor 201 connected to the translation buffer unit 2021, and when determining that a flow table entry (used for storing a page table file, that is, a translation table from a virtual address VA to a physical address PA) corresponding to the processor 201 exists in a page table buffer, convert the virtual address in the memory access request sent by the processor 201 into a physical address corresponding to a memory to be accessed in the storage system according to a target translation page table in the flow table entry, and send the physical address to the storage system 203 through the bus 204.
Specifically, each translation buffer unit 2021 in the Memory manager 202 is connected to a bus interface in the processor, such as a bus interface SP1 (System bus interface 1) shown in fig. 2, each translation buffer unit 2021 and the translation control unit 2023 in the Memory manager 202 are respectively connected to the bus, and the bus is connected to the storage System, in a specific implementation, the processor sends a virtual address to the Memory manager 202 through a Direct Memory Access (DMA) request, converts the virtual address into a physical address of the Memory to be accessed through the Memory manager 202, and accesses a Memory space corresponding to the physical address in the storage System through the bus.
The above direct memory access is an interface technology for directly exchanging data with a system memory without a processor, and since the DMA cannot realize the conversion of a virtual address, the DMA needs a real physical address, and when a continuous memory is needed, the DMA also needs an actual continuous physical address.
When there is a need for the processor 201 to access the memory, a memory access request is sent to the memory manager 202, and in some possible embodiments, the memory access request may be a DMA request, and a virtual address corresponding to a physical address of the memory to be accessed and identification information corresponding to the processor are carried in the request.
In some optional embodiments, the identification information includes first identification information for identifying a processor that sends the memory access request, and in some optional embodiments, the first identification information is a SID (Stream ID, stream ID number).
After the memory manager 202 receives the memory access request, it may determine the processor corresponding to the memory access request according to the first identification information, for example, assuming that there are 3 processors, i.e., processor 1, processor 2, and processor 3, and after the memory manager 202 receives the memory access request sent by processor 1, it may determine the processor sending the request as processor 1 according to the identification information in the memory access request.
The translation buffer unit 2021 is configured to receive a memory access request sent by the processor 201 connected thereto, determine whether a page table buffer area has a flow entry corresponding to the processor 201, and determine a target translation page table according to the flow entry. Specifically, a memory access request sent by a processor connected to the translation buffer unit is received, and a flow entry corresponding to the processor is searched from a page table buffer; acquiring a flow entry corresponding to the processor from the translation control unit when it is determined that the flow entry corresponding to the processor is not searched from the page table buffer; when determining that the flow entry corresponding to the processor is searched from the page table buffer area, determining an address conversion mode corresponding to the processor according to the searched flow entry, and determining a target translation page table corresponding to the processor according to the address conversion mode.
The page table buffer of the translation buffer unit 2021 is used to cache a page table file, in which a flow table entry corresponding to the processor connected to the translation buffer unit 2021 is cached, so that, after the translation buffer unit 2021 receives the memory access request, it is first determined whether an STE corresponding to the first identification information exists in the TLB, and when the STE is found, the address conversion mode corresponding to the processor can be determined from the STE.
The translation control unit 2023 is connected to the storage system 203 through the bus 204, and is configured to, when any translation cache unit 2021 determines that no flow entry corresponding to the processor exists in the page table buffer, look up a flow entry corresponding to the processor from a flow entry storage area of the storage system 203, and send the found flow entry to any translation control unit 2023. Specifically, a flow entry acquisition request sent by any translation cache unit 2021 is received, and a flow entry corresponding to the processor 201 is searched in a flow entry storage area of the storage system 203 according to first identification information carried in the flow entry acquisition request; when the flow entry corresponding to the processor 201 is found, the found flow entry is sent to any translation cache unit 2021.
In some embodiments, when the translation cache unit determines whether a flow entry corresponding to the processor exists in the page table buffer, and determines that the flow entry corresponding to the processor is not searched in the page table buffer, the translation cache unit sends a flow entry acquisition request to the translation control unit, where the flow entry acquisition request carries first identification information, and the translation control unit receives the flow entry acquisition request and searches a flow entry corresponding to the first identification information from a flow entry storage area in the storage system; the flow table entry storage area in the storage system stores preset flow table entries corresponding to each processor. And after the flow table entry corresponding to the first identification information is found, the flow table entry is sent to a translation cache unit, so that the translation cache unit stores the flow table entry into a page table buffer area, and an address conversion mode corresponding to the processor is determined according to the flow table entry.
It should be noted that the address translation mode corresponding to the processor is predefined in the initialization configuration process of the memory manager 202, and specifically, the address translation mode corresponding to the target processor is defined by the definition of the config field in the flow table entry.
In the embodiment of the present application, the address conversion modes include four address conversion modes, which are a first address conversion mode (i.e., the stage1 mode), a second address conversion mode (i.e., the stage2 mode), a third address conversion mode (i.e., the stage1 and the stage2 mode), and a fourth address conversion mode (i.e., the bypass mode).
In a specific implementation, the address translation mode corresponding to the processor is determined according to an address space of a memory to be accessed, and when the memory space accessed by the processor is outside a range corresponding to a physical address of the processor, the address translation mode corresponding to the processor is set to be a first address translation mode, a second translation mode, or a third translation mode (which may be specifically set as required).
For example, when a 32-bit processor accesses an address space within more than 4G of address space, such as a 64-bit address, the processor may access the virtual address by configuring the memory manager 202 to map the high address to a virtual address below 4GB in the first address translation mode, the second translation mode, or the third translation mode, as shown in fig. 3. When a 32-bit processor access employs an address space less than 4G, the first four translation mode may be employed without requiring page table lookups and address translation by the memory manager 202.
In the system, aiming at the problem that a 32-bit processor with a specific architecture cannot access a space higher than 4G, a memory manager is mounted under the processor, the memory manager is used for reconstructing an address mapping relation, the memory manager is configured to map a high address to a virtual address lower than 4GB of the 32-bit processor with the specific architecture, and the processor only accesses the virtual address; after receiving a memory access request from a processor, the memory manager performs page table lookup and translation on a virtual address to complete access to a high address space, so that the effect of accessing a space higher than 4G by using the 32-bit processor with the specific architecture is achieved.
In the embodiment of the present application, a process of the translation buffer unit converting the virtual address in the memory access request into the physical address of the memory to be accessed in the first conversion mode, the second conversion mode, the third conversion mode, and the fourth conversion mode is described in detail below.
When the address conversion mode is the first conversion mode, the identification information further includes second identification information for determining a target context descriptor corresponding to the processor, and in some optional embodiments, the second identification information may be an SSID (Substream ID) for determining a CD corresponding to the processor from among the CDs stored in the STE.
In implementation, the translation buffer unit determines a target translation page table corresponding to the processor according to the address conversion mode, specifically: determining a target context descriptor corresponding to the processor from a plurality of context descriptors stored in the flow table entry according to the second identification information; and determining a target translation page table corresponding to the processor according to the pointer in the target context descriptor.
It should be noted that, there may be one CD or a plurality of CDs in the STE, and when there is only one CD, the CD is directly determined as the corresponding CD without using the second identification information.
And determining a target translation page table corresponding to the processor according to the determined pointer in the CD, and determining a physical address corresponding to the virtual address according to a mapping relation between the virtual address of the processor and the physical address of the memory to be accessed, which is stored in the target translation page table.
The CD is a data structure with a specific format, and includes a base address pointer pointing to a stage1 address translation page table, and a target translation page table corresponding to the processor is determined according to the base address pointer, and a mapping relationship between a virtual address and a physical address is stored in the target translation page table.
In a specific implementation, in the stage1 (first conversion mode) address translation stage, firstly, the SID indexes to the STE, and then the SSID indexes to the CD, where the CD contains page table base address information and the like required in the stage1 address translation process. In the stage1 translation process, a plurality of CDs correspond to the address translations of a plurality of stages 1, a corresponding stage1 address translation page table is determined through SSID, and address translation is carried out according to the mapping relation between the virtual address and the physical address stored in the translation page table.
When the address conversion mode is the second conversion mode, the translation buffer unit is used for determining a target translation page table corresponding to the processor according to the address conversion mode. Specifically, a target base address of a target translation page table corresponding to the processor is determined from the flow table entry; and determining a target translation page table corresponding to the processor according to the target base address.
After the target translation page table is determined, a physical address corresponding to the virtual address is determined according to the mapping relation between the virtual address of the processor stored in the translation page table and the physical address of the memory to be accessed.
In a specific implementation, in the stage2 (second conversion mode) address translation stage, the STE includes information such as a translation page table base address of the stage2 address translation, after the STE corresponding to the processor is determined, a translation page table corresponding to the STE is determined according to the information of the translation page table base address, and address conversion is performed according to the mapping relationship between the virtual address and the physical address stored in the translation page table.
When the address conversion mode is a third conversion mode, the identification information further comprises second identification information used for determining a target context descriptor corresponding to the processor, and the target translation page table comprises a first translation page table used for converting a virtual address of the processor into an intermediate address and a second translation page table used for converting the intermediate address corresponding to the processor into a physical address of the memory to be accessed.
In an implementation, the translation buffer unit is configured to determine, according to the address translation mode, a target translation page table corresponding to the processor, and specifically, determine, according to the second identification information, a target context descriptor corresponding to the processor from among a plurality of context descriptors stored in the flow table entry; determining a first translation page table corresponding to the processor according to a pointer in the target context descriptor; determining a target base address of a second translation page table corresponding to the processor from the flow table entry; and determining a second translation page table corresponding to the processor according to the target base address.
In a specific implementation, at the stage of address translation of stage1 and stage2 (the third conversion mode), the virtual address is first converted into the intermediate address by using the stage1 method, and then the intermediate address is converted into the physical address by using the stage2 method, and the specific conversion process can refer to the conversion processes of stage1 (the first conversion mode) and stage2 (the second conversion mode), which are not described herein again.
When the address conversion mode is a fourth conversion mode, the translation buffer unit is configured to convert the virtual address in the memory access request into a physical address of the memory to be accessed according to the address conversion mode, and specifically, the translation buffer unit directly determines the virtual address in the memory access request as the physical address of the memory to be accessed.
Namely, bypass mode is adopted for direct communication, page table lookup and address translation are not needed to be carried out through the memory manager 202, and the virtual address is directly used as the physical address of the memory to be accessed to access the memory to be accessed.
It should be noted that, when the fourth translation mode is adopted, it is not necessary to determine a target translation page table corresponding to the target processor, that is, it is not necessary to convert the virtual address of the target processor, and it is directly used as the physical address of the memory to be accessed.
Fig. 4 is a schematic flowchart of a memory access method according to an embodiment of the present disclosure; as shown in fig. 4, an embodiment of the present application provides a memory access method, which is applied to a memory manager of the memory access system, and specifically includes:
For the specific steps of the memory access method, reference is made to the description of the working principle of the memory access system, and details are not repeated here.
Before using the memory manager 202 to perform address translation, the memory access method provided in the embodiment of the present application further needs to perform a process shown in fig. 5, which specifically includes: defining a software interface 501, performing memory manager configuration 502 and updating a page table 503.
For the portion 501 defining the software interface, some data structures and some function interfaces need to be declared first; in the memory manager configuration stage, a register is required to be configured according to user requirements, wherein the register comprises a memory manager base address, a page table space base address, streamID, safety and the like; the page table updating is a process of updating a mapping relationship in a page table for implementing virtual address to physical address translation according to the configuration of the memory manager and the address translation requirement of the processor, and detailed descriptions of related operations are respectively described below.
When defining a software interface, first declaring relevant data structures, including: non-secure and secure registers, command and event queues, page table space, etc., where the registers are used to configure the memory manager, and the STE (STE contains a pointer to the stage2 address translation table and a pointer to the CD) and the CD are related to the page table lookup process, where the page table base address and the configuration of the translation process (whether stage1 and stage2 are enabled or not) are stored; secondly, defining a series of configuration function interfaces for calling in the subsequent configuration of the memory manager, and mainly comprising read-write operation of a relevant register, initialization of STE and CD, operation of a command and event queue, a page table establishing process and the like.
When configuring the memory manager, the purpose of the configuration stage is to initialize the memory manager, specifically including setting the base address and range of the data structure defined by the software interface, and setting the developed memory attributes, and finally enabling the memory manager.
The configuration process of the memory manager is described as an embodiment.
When the memory manager is configured, firstly setting a base address of the memory manager, and then interrupting initialization; then setting the base addresses and sizes of the STE, the event queue and the command queue; then setting the buffer attributes of the table and the queue, including: a shared attribute, an internal cache attribute, and an external cache attribute; sending a command to enable all TLBs in the memory manager to be invalid; then enabling the event queue and the command queue; and finally enabling the memory manager to be in a non-secure mode.
Before the above page table update is executed before the memory manager receives the memory access request sent by the target processor, as shown in fig. 6, the method specifically includes:
601, receiving an instruction for refreshing a target translation page table corresponding to a target processor, where the instruction includes a first mapping relationship between a virtual address corresponding to the target processor and a physical address of a memory to be accessed;
the specific content of the mapping relation contained in the indication is determined by a set address conversion mode, and if the set address conversion mode is a first address conversion mode or a second address conversion mode, the mapping relation is the mapping relation between the virtual address of the target processor and the physical address of the memory to be accessed; if the set address conversion mode is the third address conversion mode, the mapping relationship comprises: the mapping relation between the virtual address and the intermediate address of the target processor and the mapping relation between the intermediate address of the target processor and the physical address of the memory to be accessed.
The page table flush procedure is described in detail below using an example of 32-bit processor mapping 8G space addresses, where the page table address mapping scheme is shown in table 1 below:
TABLE 1 Page Table mapping
SRC (source) represents the source operand, and as can be seen from the above table, the virtual address ranges in SRC0 and SRC1 are identical, but the corresponding actual physical addresses are completely different. In actual use, when accessing data of SRC0 or SRC1, the corresponding page table needs to be loaded to TLB in advance, so as to ensure correct access, for example: when accessing the data corresponding to the SRC0, replacing the mapping relationship in the current translation page table with the mapping relationship in the SRC0 in advance to ensure the correctness of the subsequent address translation, that is, to be equivalent to a page table refreshing process.
By the memory access method, the access to any physical space can be completed theoretically by using a 32-bit virtual address, in the system, the access to the memory by a 32-bit processor can be mapped by a memory manager, virtual address variables SRC 0-SRC 15 are set, each variable is used as a starting virtual address to be respectively mapped to the actual physical address of 1G, and before accessing a target area, a corresponding page table is refreshed, so that the access to the memory space of 16G by the 32-bit processor and a 64-bit processor can be realized.
Based on the same disclosure concept, the embodiment of the present application further provides a memory access device, and since the device is a device in the method in the embodiment of the present application, and the principle of the device to solve the problem is similar to that of the method, the implementation of the device may refer to the implementation of the method, and repeated details are not repeated.
Fig. 7 is a schematic diagram of a memory access device according to an embodiment of the present application, please refer to fig. 8, in which an embodiment of the present application provides a memory access device, including:
a receiving unit 701, configured to receive a memory access request sent by a target processor, where the memory access request includes a virtual address and identification information corresponding to the target processor;
a determining unit 702, configured to search, according to the identification information, a target translation page table corresponding to the target processor from a set of translation page tables; the translation page table set stores a mapping relation between a virtual address of at least one processor and a physical address of a corresponding memory to be accessed, wherein a virtual address space corresponding to the virtual address of the at least one processor is smaller than a physical address space corresponding to the physical address of the corresponding memory to be accessed;
a converting unit 703, configured to convert a virtual address in the memory access request into a physical address of a memory to be accessed according to a mapping relationship in the target translation page table;
a sending unit 704, configured to send a memory access request carrying the physical address of the memory to be accessed to the storage system, so that the storage system obtains, according to the physical address of the memory to be accessed, data corresponding to the physical address in the memory to be accessed, and sends the data to the memory manager.
Optionally, before the receiving unit 701 is configured to receive the memory access request sent by the target processor, it is further configured to: receiving an instruction for refreshing a target translation page table corresponding to a target processor, wherein the instruction comprises a first mapping relation between a virtual address corresponding to the target processor and a physical address of a memory to be accessed; and refreshing the mapping relation in the target translation page table corresponding to the processor in the translation page table set by using the first mapping relation.
Based on the same disclosure concept, the embodiment of the present application further provides a memory manager, and since the device is a device in the method in the embodiment of the present application, and the principle of the device to solve the problem is similar to that of the method, the implementation of the device may refer to the implementation of the method, and repeated details are not repeated.
As will be appreciated by one skilled in the art, aspects of the present application may be embodied as a system, method or program product. Accordingly, various aspects of the present application may be embodied in the form of: an entirely hardware embodiment, an entirely software embodiment (including firmware, microcode, etc.) or an embodiment combining hardware and software aspects that may all generally be referred to herein as a "circuit," module "or" system.
In some possible embodiments, an apparatus according to the present application may include at least one processor, and at least one memory. The memory stores program code, and when the program code is executed by the processor, the program code causes the processor to execute the steps of the memory access method according to the various exemplary embodiments of the present application described above in the present specification.
An electronic device 800 according to this embodiment of the application is described below with reference to fig. 8. The device 800 shown in fig. 8 is only an example and should not bring any limitations to the functionality or scope of use of the embodiments of the present application.
As shown in fig. 8, the device 800 is in the form of a general purpose device. The components of device 800 may include, but are not limited to: the at least one processor 801, the at least one memory 802, and the bus 803 connecting the various system components (including the memory 802 and the processor 801), wherein the memory stores program code that, when executed by the processor, causes the processor to perform the steps of:
receiving a memory access request sent by a target processor, wherein the memory access request comprises a virtual address and identification information corresponding to the target processor;
searching a target translation page table corresponding to the target processor from a translation page table set according to the identification information; the translation page table set stores a mapping relation between a virtual address of at least one processor and a physical address of a corresponding memory to be accessed, wherein a virtual address space corresponding to the virtual address of the at least one processor is smaller than a physical address space corresponding to the physical address of the corresponding memory to be accessed;
converting the virtual address in the memory access request into a physical address of a memory to be accessed according to the mapping relation in the target translation page table;
and sending a memory access request carrying the physical address of the memory to be accessed to the storage system, so that the storage system acquires data corresponding to the physical address in the memory to be accessed according to the physical address of the memory to be accessed and sends the data to the memory manager.
Bus 803 represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, a processor, or a local bus using any of a variety of bus architectures.
The memory 802 may include readable media in the form of volatile memory, such as Random Access Memory (RAM) 8021 and/or cache memory 8022, and may further include Read Only Memory (ROM) 8023.
Optionally, the processor is further configured to: receiving an instruction for refreshing a target translation page table corresponding to a target processor, wherein the instruction comprises a first mapping relation between a virtual address corresponding to the target processor and a physical address of a memory to be accessed; and refreshing the mapping relation in a target translation page table corresponding to the processor in the translation page table set by utilizing the first mapping relation.
In some possible embodiments, various aspects of a memory access method provided by the present application may also be implemented in the form of a program product including program code for causing a computer device to perform the steps of a memory access method according to various exemplary embodiments of the present application described above in this specification when the program product is run on the computer device.
The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
The program product for monitoring of embodiments of the present application may employ a portable compact disc read only memory (CD-ROM) and include program code, and may be run on a device. However, the program product of the present application is not limited thereto, and in this document, a readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
A readable signal medium may include a propagated data signal with readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A readable signal medium may also be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Program code for carrying out operations of the present application may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user device, partly on the user device, as a stand-alone software package, partly on the user device and partly on a remote device, or entirely on the remote device or server. In the case of remote devices, the remote devices may be connected to the user device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to external devices (e.g., through the internet using an internet service provider).
It should be noted that although several units or sub-units of the apparatus are mentioned in the above detailed description, such division is merely exemplary and not mandatory. Indeed, the features and functions of two or more units described above may be embodied in one unit, according to embodiments of the application. Conversely, the features and functions of one unit described above may be further divided into embodiments by a plurality of units.
Further, while the operations of the methods of the present application are depicted in the drawings in a particular order, this does not require or imply that these operations must be performed in this particular order, or that all of the illustrated operations must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and block diagrams, and combinations of flows and blocks in the flow diagrams and block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and block diagram block or blocks.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (10)
1. A memory access system, comprising:
at least one processor, configured to send a memory access request to access a memory larger than a physical address space accessible by the processor, where the memory access request includes a virtual address and identification information corresponding to the processor;
the memory manager is connected with the at least one processor and used for determining a target translation page table corresponding to any processor according to identification information in a memory access request sent by any processor, and converting a virtual address in the received memory access request into a corresponding physical address of the memory to be accessed according to the target translation page table, wherein the virtual address space corresponding to the virtual address of the processor is smaller than the physical address space corresponding to the physical address of the memory to be accessed;
and the storage system is connected with the memory manager through a bus and used for receiving a memory access request which is sent by the memory manager and carries a physical address, acquiring data corresponding to the physical address from a memory to be accessed and sending the data to the memory manager.
2. The system according to claim 1, wherein the memory manager comprises a translation control unit, at least one translation buffer unit, and a distributed transmission interface corresponding to each translation buffer unit and connecting the translation buffer unit and the translation control unit; each processor is connected with at least one translation buffer unit, and each translation buffer unit is connected with a unique processor;
each translation buffer unit is configured to receive a memory access request sent by a processor connected to the translation buffer unit, convert, according to a target translation page table in a flow table entry when determining that the flow table entry corresponding to the processor exists in a page table buffer, a virtual address in the memory access request sent by the processor into a physical address corresponding to a memory to be accessed in the storage system, and send the physical address to the storage system;
the translation control unit is configured to, when any translation buffer unit determines that a flow entry corresponding to the processor does not exist in a page table buffer, look up a flow entry corresponding to the processor from a flow entry storage area of the storage system, and send the looked-up flow entry to the any translation control unit.
3. The system according to claim 2, wherein the identification information includes first identification information for identifying a processor that sent the memory access request; the translation buffer unit is configured to:
receiving a memory access request sent by a processor connected with the translation buffer unit, and searching a flow table entry corresponding to the processor from a page table buffer area; wherein the content of the first and second substances,
when determining that the flow table entry corresponding to the processor is not searched in the page table buffer, acquiring the flow table entry corresponding to the processor from the translation control unit;
when determining that the flow table entry corresponding to the processor is found from the page table buffer area, determining an address conversion mode corresponding to the processor according to the found flow table entry, and determining a target translation page table corresponding to the processor according to the address conversion mode.
4. The system of claim 3, wherein the translation control unit is to:
receiving a flow table entry acquisition request sent by any translation cache unit, and searching a flow table entry corresponding to the processor from a flow table entry storage area of the storage system according to first identification information carried in the flow table entry acquisition request;
and when the flow table entry corresponding to the processor is found, sending the found flow table entry to any translation cache unit.
5. The system according to claim 3 or 4, wherein when the address conversion mode is the first conversion mode, the identification information further includes second identification information for determining a target context descriptor corresponding to the processor, and the translation buffer unit is specifically configured to:
determining a target context descriptor corresponding to the processor from a plurality of context descriptors stored in the flow table entry according to the second identification information;
and determining a target translation page table corresponding to the processor according to the pointer in the target context descriptor.
6. The system according to claim 3 or 4, wherein when the address conversion mode is the second conversion mode, the translation buffer unit is specifically configured to:
determining a target base address of a target translation page table corresponding to the processor from the flow table entry;
and determining a target translation page table corresponding to the processor according to the target base address.
7. The system according to claim 3 or 4, wherein when the address translation mode is a third translation mode, the identification information further includes second identification information for determining a target context descriptor corresponding to the processor, and the target translation page table includes a first translation page table for converting a virtual address of the processor into an intermediate address and a second translation page table for converting the intermediate address corresponding to the processor into a physical address of the memory to be accessed; the translation buffer unit is specifically configured to:
determining a target context descriptor corresponding to the processor from a plurality of context descriptors stored in the flow entry according to the second identification information;
determining a first translation page table corresponding to the processor according to a pointer in the target context descriptor;
determining a target base address of a second translation page table corresponding to the processor from the flow table entry;
and determining a second translation page table corresponding to the processor according to the target base address.
8. A memory access method applied to a memory manager in the memory access system according to any one of claims 1 to 7, the method comprising:
receiving a memory access request sent by a target processor, wherein the memory access request comprises a virtual address and identification information corresponding to the target processor;
searching a target translation page table corresponding to the target processor from a translation page table set according to the identification information; the translation page table set stores a mapping relation between a virtual address of at least one processor and a physical address of a corresponding memory to be accessed, wherein a virtual address space corresponding to the virtual address of the at least one processor is smaller than a physical address space corresponding to the physical address of the corresponding memory to be accessed;
converting the virtual address in the memory access request into a physical address of the memory to be accessed according to the mapping relation in the target translation page table;
and sending a memory access request carrying the physical address of the memory to be accessed to the storage system, so that the storage system acquires data corresponding to the physical address in the memory to be accessed according to the physical address of the memory to be accessed and sends the data to the memory manager.
9. The method of claim 8, wherein before receiving the memory access request from the target processor, further comprising:
receiving an instruction for refreshing a target translation page table corresponding to the target processor, wherein the instruction comprises a first mapping relation between a virtual address corresponding to the target processor and a physical address of a memory to be accessed;
and refreshing the mapping relation in the target translation page table corresponding to the processor in the translation page table set by using the first mapping relation.
10. A computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, implement the steps of the method of claim 8 or 9.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117851290A (en) * | 2024-03-07 | 2024-04-09 | 北京象帝先计算技术有限公司 | Page table management method, system, electronic component and electronic device |
| CN117851292A (en) * | 2024-03-07 | 2024-04-09 | 北京象帝先计算技术有限公司 | Integrated circuit system, component, equipment and memory management method |
| CN117851289A (en) * | 2024-03-07 | 2024-04-09 | 北京象帝先计算技术有限公司 | Page table acquisition method, system, electronic component and electronic device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117851290A (en) * | 2024-03-07 | 2024-04-09 | 北京象帝先计算技术有限公司 | Page table management method, system, electronic component and electronic device |
| CN117851292A (en) * | 2024-03-07 | 2024-04-09 | 北京象帝先计算技术有限公司 | Integrated circuit system, component, equipment and memory management method |
| CN117851289A (en) * | 2024-03-07 | 2024-04-09 | 北京象帝先计算技术有限公司 | Page table acquisition method, system, electronic component and electronic device |
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