CN115811489A - Exchange chip verification system and method based on UVM and storage medium - Google Patents
Exchange chip verification system and method based on UVM and storage medium Download PDFInfo
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Abstract
The invention relates to the technical field of chips, and particularly discloses a system, a method and a storage medium for verifying a switching chip based on UVM, wherein the system comprises: comprises a data layer, a control layer and an excitation layer; the data layer comprises an exchange chip to be verified, a port input agent, a port output agent, a reference model and a score board; the port input agent is used for converting the data excitation into signal excitation to be loaded to the exchange chip and sending the data excitation to the reference model; the reference model is used for exciting and processing data and then sending the data to the scoring board; the port output agent is used for converting the signal excitation output by the exchange chip into data excitation and sending the data excitation to the scoring board; and the score counting board is used for comparing the data excitation of the port output agent with the data excitation of the reference model after receiving the data excitation of the port output agent, and outputting a score according to a comparison result. By adopting the technical scheme of the invention, the function verification can be carried out on the exchange chip, and the evaluation of key performance indexes such as throughput rate, grouping time delay, throughput and the like of the exchange chip can be carried out.
Description
Technical Field
The invention relates to the technical field of chips, in particular to a system and a method for verifying a switching chip based on UVM and a storage medium.
Background
The switch chip is a key component of a large-scale interconnect network. As port rates and port sizes grow, the design of switch chips becomes more complex. In order to complete the verification of the switch chip more quickly, the verifier needs to build an efficient verification platform to verify and test the function and performance of the switch chip. UVM (Universal Verification Methodology) is currently widely used for building Verification platforms. UVM is a standard reusable programming framework developed based on the System Verilog language, and is also a methodology for chip verification.
When the switch chip is verified, the switch chip serves as a system to be verified (DUT), and a developer needs to design a Reference Model (RM) according to functional characteristics of the DUT to simulate functional behaviors of the switch chip, such as routing computation, arbitration, authorization, and the like. In order to simulate the use scene of the switching chip, an excitation injection module (driver) is required to be established for injecting the excitation (SEQ) simulating various data into the DUT and the RM, and the SQR (sequence) is used for managing the calling of the SEQ and connecting the SEQ and the driver. When the stimulus is injected into the DUT and the RM, the DUT and the RM can make corresponding behaviors according to the stimulus, such as transmission and configuration registers and the like, the behavior of the DUT on the stimulus is intercepted by the monitor, meanwhile, the intercepted behavior is transmitted to an SCB (scoreboard) to wait for behavior comparison, the SCB can simultaneously obtain the behavior of the RM on the same stimulus, and whether the DUT functions are correct is judged by comparing whether the behaviors of the RM and the RM are consistent.
With the increase of the port rate and the port scale of the switch chip, the evaluation of the switching performance is very critical, and if the performance of the switch chip can be evaluated in the early functional verification stage, a quicker improvement basis can be provided for design developers, and the iteration efficiency of the switch chip is improved. In the common working process based on the UVM verification platform, the performance of the switching chip, particularly the throughput rate, the grouping delay, the throughput and other key performance indexes are not evaluated, and the requirement for rapidly and iteratively developing the switching chip is difficult to meet.
An authentication method under DMA communication operation is disclosed in the patent "authentication method of multiple data paths based on UVM authentication platform" (CN 114003527A). The method solves the problems of poor flexibility and reliability of a verification system caused by the fact that the output data of the module to be verified and the data calculated by the verification reference model are automatically inconsistent due to inconsistent sending sequence of the data packets when a plurality of DMA (direct memory access) are triggered simultaneously; however, the patent is difficult to apply to a use scenario with a large communication port, and the expandability is poor, and meanwhile performance evaluation on communication is also lacked.
An authentication method for Router in network on chip is disclosed in the patent "a reusable authentication platform for Router based on UVM" (CN 113626343A). The invention optimizes the scoring process of correct excitation and wrong excitation, and improves the reliability of verification; however, the patent can only be used in a 5-port network-on-chip router scene, and is difficult to meet the requirement of high-order switch chip verification in a large-scale interconnection network, and simultaneously, the excited samples are relatively few, and it is difficult to simulate various flow scenes in a complex large-scale interconnection network.
An authentication platform supporting PCIe and ethernet protocols is disclosed in the patent "authentication platform supporting PCIe gigabit ethernet chip based on UVM" (CN 114826995A). The invention simulates the communication behaviors of two protocols by realizing the pcie and the Ethernet agent module, and has the characteristics of strong portability, strong reusability and high verification efficiency. However, the method is suitable for a verification scene of a single-port network card, the interconnection protocol is relatively fixed, the method is difficult to cope with a complex use scene of a large-scale interconnection network, and meanwhile, the method has no capability of verifying a high-order exchange chip and lacks expandability.
In summary, when the existing UVM-based verification platform performs function verification on a switch chip DUT, it is difficult to effectively evaluate the performance of the switch chip DUT, especially to evaluate key performance indexes such as throughput, packet delay, and throughput. In the face of an application scenario that the function demand of an interconnection network on a switch chip is increasingly complex and the performance demand is rapidly increased, the conventional logic function verification platform of the switch chip is difficult to meet the requirements of developers for rapidly iterating and evaluating the switch chip.
Disclosure of Invention
One of the objectives of the present invention is to provide a UVM-based switch chip verification system, which can perform functional verification on a switch chip and evaluate key performance indicators, such as throughput, packet delay, and throughput, of the switch chip.
In order to solve the technical problem, the present application provides the following technical solutions:
the exchange chip verification system based on the UVM comprises a data layer, a control layer and an excitation layer;
the control layer comprises a parameter processing module and an excitation management module; the excitation layer comprises an excitation library; the data layer comprises an exchange chip to be verified, a port input agent, a port output agent, a reference model and a scoring board;
the parameter processing module is used for receiving and processing the input user parameters;
the excitation library is used for generating test data excitation according to the user parameters;
the excitation management module is used for sending the data excitation to the port input agent;
the port input agent is used for converting the data excitation into signal excitation to be loaded to the exchange chip and sending the data excitation to the reference model;
the reference model is used for exciting and processing data and then sending the data to the scoring board;
the port output agent is used for converting the signal excitation output by the exchange chip into data excitation and sending the data excitation to the scoring board;
and the score board is used for comparing the data excitation of the port output agent with the data excitation of the reference model after receiving the data excitation of the port output agent, and outputting a score according to a comparison result.
Further, the data stimulus includes key fields including one or more of an injection timestamp, an intercept timestamp, packet length information, and an interval time.
Further, the port input agent includes N stimulus drivers and N stimulus management; n is not less than 2 and is an integer;
the excitation driver i is used for obtaining data excitation from the excitation management i, wherein i is more than or equal to 0 and less than or equal to N-1, and i is an integer; after the excitation driver i obtains data excitation, the excitation driver i is used for converting the data into an excitation signal with a corresponding format and loading the excitation signal to a port i of the exchange chip to complete excitation input; meanwhile, the excitation driver i is also used for sending the data excitation to a port i of the reference model;
the reference model is used for forwarding the data excitation to an output port j of the reference model according to a set routing algorithm and a data grouping processing rule after the data excitation is received, wherein j is more than or equal to 0 and less than or equal to N-1, and j is an integer;
the scoring board comprises N expected queues and N interception ports, an output port j of the reference model is connected with an expected queue j of the scoring board, and the expected queue j is used for storing data sent by the output port j;
the port output agent comprises N excitation observation modules; the excitation observation module is used for obtaining output signal excitation from an output port k of the exchange chip, wherein k is more than or equal to 0 and less than or equal to N-1, k is an integer, then converting the signal excitation into data excitation in a corresponding format, and sending the data excitation to an interception port k of the score board;
and the scoring board is used for searching the data excitation matched with the key field of the data excitation in the expected queue k after the data excitation is obtained by the interception port k, and outputting the test score.
Further, the signal stimulus comprises an interface format;
the data stimulus also includes a subclass that signal-integrates the fields of the signal stimulus.
The invention also aims to provide a switching chip verification method based on UVM, which comprises the following steps:
s1, generating test data excitation by an excitation library; the data stimulus comprises one or more of an injection timestamp, an interception timestamp, packet length information and an interval time;
s2, the data excitation enters corresponding excitation management under the control of an excitation management module;
s3, excitation management converts the data excitation sent to the corresponding excitation driver into signal excitation and loads the signal excitation into an input port of the exchange chip, and meanwhile, the excitation driver sends the data excitation to a reference model;
s4, the reference model converts the input data excitation into expected data excitation according to the function of the exchange chip, and sends the expected data excitation to a corresponding expected queue of the scoring board for storage;
s5, converting the signal excitation into result signal excitation after the signal excitation is input into the exchange chip;
s6, after the result signal excitation reaches the output port of the switching chip, the result signal excitation is intercepted and converted into intercepted data excitation by the excitation observation module, and the intercepted data excitation is sent to the scoring board by the excitation observation module;
and S7, after receiving the intercepted data excitation, the scoring board searches for the matched expected data excitation in the corresponding expected queue, and if the matched expected data excitation is matched, the performance statistics is carried out, and the final function score is output.
Further, the step S1 specifically includes the following steps:
s101, analyzing the user parameters by a parameter processing module, and transmitting the user parameters to an incentive library; the user parameters comprise a data packet length range, a flow model and an injection rate;
and S102, the excitation library selects a corresponding excitation generation class according to the flow model, and generates tested data excitation according to the data grouping length range and the injection rate.
Further, the step S3 is as follows:
s301, the corresponding excitation management i transmits data excitation to an excitation drive i;
s302, the excitation driver i judges whether the data excitation is finished or not, and if so, the step S306 is executed; otherwise, executing step S303;
s303, judging whether data excitation is sent to the reference model or not by the excitation driver i, and if so, executing the step S304; otherwise, the excitation driver i sets the sending time t _ send of the data excitation as the current simulation time, sends the current simulation time to the port i of the reference model, marks the data excitation as sent, sets the interval time iter _ cycle = trans _ item. Wherein trans _ item is a data stimulus;
s304, the excitation driver i converts the data excitation into signal excitation, loads the signal excitation on an interface signal of the exchange chip, and executes the step S305;
s305, enabling the driver i to wait for sending the next data excitation, judging whether the waiting time is equal to iter _ cycle, if the waiting time waiting _ cycle = iter _ cycle, sending the next data excitation, and executing the step S302; otherwise, go to step S305;
and S306, finishing data sending.
Further, the step S7 specifically includes the following contents:
s701, the score counting board judges whether the current simulation time reaches the test duration, and if so, the step S709 is executed; otherwise, go to step S702;
s702, the interception port k of the score counting board receives the interception data excitation and executes the step S703;
s703, the score board judges whether the expected queue k is empty, if so, the step S706 is executed; otherwise, executing step S704;
s704, judging whether to search a matched expected data excitation in an expected queue k by taking the key field of the intercepted data excitation as an index, if so, executing a step S705, otherwise, executing a step S706;
s705, judging the function score by the score counting board, and executing the step S707;
s706, judging that the score is not scored by the score counting board, deleting the intercepted data excitation, and executing the step S701;
s707, calculating statistical data according to the following formula, and then executing the step S701;
port i intercepts and captures the total amount of data, pkt _ len _ port [ i ] = pkt _ len _ port [ i ] + exp _ item. Where exp _ item.pke _ len refers to the amount of data that is expected to be data-driven;
the total amount of intercepted data of the port i is pkt _ num _ port [ i ] = pkt _ num _ port [ i ] +1;
the sum of the time consumed by port i data packets, pkt _ delay _ port [ i ] = pkt _ delay _ port [ i ] + act _ item.t _ rcv-exp _ item.t _ snd; wherein act _ item.t _ rcv refers to the capture time of capturing the data stimulus, and exp _ item.t _ snd refers to the injection time of the desired data stimulus;
s709, counting and outputting the final function score, and executing the step S710;
s710, outputting the final performance statistical data according to the following formula, and executing a step S711;
port average bandwidth: avg _ bw _ port [ i ] = pkt _ len _ port [ i ]/t _ sim; wherein t _ sim refers to simulation time;
average throughput of chips: avg _ throughput = pkt _ len _ sum/t _ sim;
port average delay: avg _ lt _ port [ i ] = pkt _ delay _ port [ i ]/pkt _ num _ port [ i ];
average time delay of the chip; avg _ latency = pkt _ delay _ sum/pkt _ num _ port [ i ];
average flux of the chip: avg _ pkt _ prc = pkt _ num _ sum/t _ sim; wherein pkt _ num _ sum refers to the total number of data intercepted by each port;
and S711, completing the test.
It is a further object of the present invention to provide a storage medium storing a computer program which, when executed by a processor, implements the steps of the above method.
The invention has the beneficial effects that: the invention solves the problem that the exchange chip developer evaluates key performance indexes such as throughput rate, grouping time delay, throughput and the like of the exchange chip while carrying out function verification on the exchange chip DUT, accelerates the iteration of the developer and the work period of designing the exchange chip, and simultaneously can accurately calculate the key performance indexes of the exchange chip.
Drawings
FIG. 1 is a logic block diagram of an embodiment of a UVM-based switch chip verification system;
FIG. 2 is a schematic diagram illustrating interaction of a control layer and a stimulus layer in the UVM-based switch chip verification system according to the embodiment;
FIG. 3 is a schematic diagram illustrating data interaction in a data layer of an embodiment of a UVM-based switch chip verification system;
fig. 4 is a flowchart of data injection at step S3 in the UVM-based switch chip verification method according to the embodiment;
fig. 5 is a flowchart illustrating data testing and statistics at step S7 in the UVM-based switch chip verification method according to an embodiment.
Detailed Description
The following is further detailed by way of specific embodiments:
examples
As shown in fig. 1, the UVM-based switch chip verification system of this embodiment includes a data layer, a control layer and an excitation layer.
As shown in fig. 2, the control layer includes a parameter processing module (test _ par) and an incentive management module (v _ SQR).
The parameter processing module (test _ par) is used for receiving and processing user parameters input by the user in the current test, such as a flow model, an injection rate, a data packet length range and the like;
the excitation management module (v _ SQR) is used for managing injection excitation, controlling the ports, time duration and the like of excitation injection.
The incentive layer includes an incentive library (seq _ lib) for generating data incentives satisfying the user parameters parsed by the parameter processing module (test _ par).
Specifically, the excitation library (seq _ lib) includes excitation generation classes seq of various traffic patterns, and each seq can generate a traffic pattern for function test and performance test. seq may generate a data stimulus trans _ item that conforms to the traffic pattern characteristics according to the user parameters. In this embodiment, a source port number and a destination port number of data excitation are generated according to a user-specified traffic model parameter analyzed by a parameter processing module (test _ par), and a pair of the source port number and the destination port number conform to the characteristics of a traffic model; the interval time t _ inter between the data excitations is generated according to the injection rate applied _ load parameter which is analyzed by the parameter processing module (test _ par) and is appointed by the user, 0 < applied _ load is less than or equal to 1,
the calculation method of t _ inter is as follows: t _ inter obeys a probability function distribution with a mean value (pkt _ len/offset _ load-pkt _ len), such as a uniform distribution, an exponential distribution, a poisson distribution, and the like.
As shown in FIG. 3, the data layer includes a switch chip to be verified (DUT), a port input agent (i _ agent), a port output agent (o _ agent), a Reference Model (RM), and a Scoreboard (SCB).
The switching chip is an NXN switching chip, N is the number of ports, N is more than or equal to 2, and N is an integer.
The port input agent (i _ agent) is used for converting the data stimulus into a signal stimulus to be loaded to the exchange chip and simultaneously sending the data stimulus to the Reference Model (RM);
the Reference Model (RM) is used for sending the data excitation to a score board (SCB) after processing the data excitation;
the port output agent (o _ agent) is used for converting the signal excitation output by the exchange chip into data excitation and sending the data excitation to the score board (SCB);
and the score board (SCB) compares the data excitation of the port output agent (o _ agent) with the data excitation of the Reference Model (RM) after obtaining the data excitation of the port output agent (o _ agent), and outputs a score according to a comparison result.
Specifically, the port input agent (i _ agent) comprises N excitation drivers (driver) and N excitation managers (m _ SQR);
the excitation driving driver i obtains data excitation from the excitation management m _ SQR i, wherein i is more than or equal to 0 and less than or equal to N-1, i is an integer, and after the data excitation trans _ item is obtained by the excitation driving driver i, the data is converted into an excitation signal sig _ item with a corresponding format and loaded to a port i of the exchange chip to complete excitation input; meanwhile, an excitation driver i also sends data excitation trans _ item to a port i of the reference model RM;
after receiving the data excitation, the Reference Model (RM) forwards the data excitation to an output port j according to a set routing algorithm and a data grouping processing rule, wherein j is more than or equal to 0 and less than or equal to N-1, and j is an integer;
the scoring board (SCB) is internally provided with N expected queues exp _ q and N interception ports, and an output port j of the Reference Model (RM) is connected with the expected queue j of the scoring board (SCB) and used for storing data sent by the output port j;
the port export agent (o _ agent) comprises N stimulus observation modules (monitor); the excitation observation module monitor k obtains an output signal excitation sig _ item from an output port k of the switching chip, wherein k is more than or equal to 0 and less than or equal to N-1, k is an integer, then the signal excitation sig _ item is converted into a data excitation trans _ item with a corresponding format, and the data excitation trans _ item is sent to an acquisition port k of a score plate (SCB);
after an interception port k of a score board (SCB) obtains a data stimulus trans _ item, a data stimulus matched with a key field of the data stimulus trans _ item is searched in an expected queue k, and a test score is output.
The signal excitation sig _ item contains an interface format conforming to a protocol used by the switch chip, for example, an interface format specified by protocols such as the ethernet protocol, the InfiniBand protocol, and the like.
The data excitation trans _ item comprises the step of integrating signals of fields of a signal excitation sig _ item into a subclass which conforms to a system Verilog syntax specification and UVM _ sequence _ item integrated in a UVM library, and adding an injection timestamp t _ snd, an acquisition timestamp t _ rcv, packet length information pkt _ len, interval time t _ inter and other key fields according to test requirements.
Based on the above system, this embodiment further provides a UVM-based exchanged chip verification method, including the following steps:
s1, generating test data excitation by an excitation library (seq _ lib) of an excitation layer; the data excitation comprises a packet header head and a data load payload which accord with communication protocols, such as Ethernet, infiniBand protocol, PCIE protocol and the like; except for necessary key fields of a protocol, the generated test data excitation carries an additional injection timestamp t _ snd, an interception timestamp t _ rcv, packet length information pkt _ len and interval time t _ inter;
s101, a parameter processing module (test _ par) analyzes user parameters such as a data packet length range pkt _ len _ range, a traffic model traffic _ pattern, an injection rate injection _ rate and the like, and transmits the user parameters to an excitation library (seq _ lib);
s102, selecting a corresponding excitation generation class seq by an excitation library (seq _ lib) according to a traffic model (traffic _ pattern), and generating a tested data excitation trans _ item according to a data packet length range (pkt _ len _ range) and an injection rate (injection _ rate);
s2, enabling the data excitation trans _ item to enter corresponding excitation management (m _ SQR) under the control of an excitation management module (v _ SQR);
s3, excitation management (m _ SQR) is sent to a corresponding excitation driver (driver) to be converted into signal excitation to be loaded into an input port of a switching chip, and meanwhile, the excitation driver (driver) sends the data excitation to a Reference Model (RM); before the excitation driver (driver) sends the data excitation to the Reference Model (RM), the excitation driver (driver) sets the sending time t _ send as the current simulation time;
as shown in fig. 4, the method specifically includes:
s301, the corresponding excitation management i m _ SQR [ i ] transmits data excitation trans _ item to an excitation drive i driver [ i ]; in this embodiment, the incentive management i refers to the ith incentive management; that is, m _ SQR [ i ] refers to the ith m _ SQR;
s302, actuating the driver i [ i ] to judge whether the data actuation trans _ item is sent completely, if so, executing the step S306; otherwise, executing step S303;
s303, judging whether the data excitation trans _ item is sent to a Reference Model (RM) or not by the excitation drive i driver [ i ], and if so, executing a step S304; otherwise, the actuation driver i driver [ i ] sets the sending time t _ send of the data actuation trans _ item to the current simulation time, sends to the port i of the Reference Model (RM), marks the data actuation trans _ item as sent, and sets the interval time between data actuations, namely, the inter-cycle = trans _ item. the item cycle refers to the interval of the last data excitation transmission to the current data excitation transmission; executing the step S303;
s304, an excitation driver i driver [ i ] converts data excitation trans _ item into signal excitation sig _ item, loads the signal excitation sig _ item to an interface signal of a switching chip, and executes the step S305;
s305, actuating the driver i [ i ] to wait for sending the next data actuation trans _ item, judging whether the waiting time waiting _ cycle is equal to the item _ cycle, if the waiting _ cycle = the item _ cycle, sending the next data actuation trans _ item, and executing the step S302; otherwise, go to step S305;
and S306, finishing data sending.
S4, converting the input data stimulus into an expected data stimulus (exp _ item) by the Reference Model (RM) according to the function of the exchange chip, sending the expected data stimulus (exp _ item) to an expected queue k exp _ q [ k ] of a score board (SCB), and storing the expected queue k exp _ q [ k ] in the corresponding expected queue; in this embodiment, the expected queue k refers to the kth expected queue, that is, exp _ q [ k ] refers to the kth exp _ q;
s5, after the signal excitation is input into the exchange chip, the signal excitation is processed according to the design of a developer and converted into result signal excitation;
s6, the result signal excitation reaches an output port of the exchange chip, is intercepted and converted into intercepted data excitation act _ item by an excitation observation module (monitor), and the intercepted data excitation act _ item is sent to an interception port k act _ p [ k ] of a score board (SCB) by the excitation observation module (monitor); wherein an interception timestamp t _ rcv of the intercepted data stimulus (act _ item) is set to the current simulation time;
s7, after receiving the intercepted data stimulus act _ item, a score board (SCB) searches a corresponding expected queue for a matched expected data stimulus exp _ item, and if the match is obtained, performance statistics is carried out, and a final function score is output.
As shown in fig. 5, the method specifically includes:
s701, judging whether the current simulation time reaches the test duration or not by a score board (SCB), and if so, executing a step S709; otherwise, go to step S702;
s702, an interception port k act _ p [ k ] of a score board (SCB) receives interception data excitation act _ item, and step S703 is executed;
s703, judging whether the expected queue k exp _ q [ k ] is empty by a score board (SCB), if so, executing a step S706; otherwise, executing step S704;
s704, judging whether a matched expected data excitation exp _ item is searched in an expected queue k exp _ q [ k ] by taking a key field of the intercepted data excitation act _ item as an index, if so, executing a step S705, otherwise, executing a step S706;
s705, judging the function score by a score board (SCB), and executing a step S707;
s706, judging that the score is not scored by a score board (SCB), deleting the intercepted data stimulus act _ item, and executing the step S701;
s707, calculating statistical data according to the following formula, and then executing the step S701;
port i intercepts the total amount of data: pkt _ len _ port [ i ] = pkt _ len _ port [ i ] + exp _ item.pke _ len; where exp _ item.pke _ len refers to the amount of data that is expected to be data-driven;
port i intercepts the total number of data: pkt _ num _ port [ i ] = pkt _ num _ port [ i ] +1;
sum of time spent on port i data packets: pkt _ delay _ port [ i ] = pkt _ delay _ port [ i ] + act _ item.t _ rcv-exp _ item.t _ snd; wherein act _ item.t _ rcv refers to the capture time of capturing the data stimulus, and exp _ item.t _ snd refers to the injection time of the desired data stimulus;
s709, counting and outputting the final function score, and executing the step S710;
s710, outputting the final performance statistical data according to the following formula, and executing a step S711;
port i average bandwidth: avg _ bw _ port [ i ] = pkt _ len _ port [ i ]/t _ sim; wherein t _ sim refers to simulation time;
average throughput of chips: avg _ through put = pkt _ len _ sum/t _ sim; wherein pkt _ len _ sum refers to the total amount of data intercepted by each port;
port i average latency: avg _ lt _ port [ i ] = pkt _ delay _ port [ i ]/pkt _ num _ port [ i ];
average time delay of the chip; avg _ latency = pkt _ delay _ sum/pkt _ num _ port [ i ];
average flux of the chip: avg _ pkt _ prc = pkt _ num _ sum/t _ sim; the pkt _ num _ sum refers to the total number of data intercepted by each port;
and S711, completing the test.
The above-described UVM-based exchange chip authentication method may be stored in a storage medium if it is implemented in the form of a software functional unit and sold or used as an independent product. Based on such understanding, all or part of the flow in the method according to the above embodiments may be implemented by a computer program, which may be stored in a storage medium and executed by a processor, to instruct related hardware to implement the steps of the above method embodiments. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The readable medium may include: any entity or device capable of carrying the computer program code, recording medium, U.S. disk, removable hard disk, magnetic diskette, optical disk, computer Memory, read-Only Memory (ROM), random Access Memory (RAM), electrical carrier wave signal, telecommunications signal, and software distribution medium, etc.
The scheme of the embodiment can meet the requirement that developers can accurately evaluate the performance of the switch chip while verifying the functions, thereby improving the testing efficiency of the developers and accelerating the development iteration speed of the high-order complex switch chip; meanwhile, the scheme is developed based on a mainstream verification framework UVM and a verification language system Verilog, has good transportability and reusability, and is convenient for developers to learn and use.
The above are only examples of the present invention, and the present invention is not limited to the field related to the embodiments, the general knowledge of the specific structures and characteristics of the embodiments is not described herein, and those skilled in the art can know all the common technical knowledge in the technical field before the application date or the priority date, can know all the prior art in the field, and have the capability of applying the conventional experimental means before the application date, and those skilled in the art can combine the capabilities of themselves to complete and implement the present invention, and some typical known structures or known methods should not become obstacles for those skilled in the art to implement the present application. It should be noted that, for those skilled in the art, without departing from the structure of the present invention, several changes and modifications can be made, which should also be regarded as the protection scope of the present invention, and these will not affect the effect of the implementation of the present invention and the practicability of the patent. The scope of the claims of the present application shall be determined by the contents of the claims, and the description of the embodiments and the like in the specification shall be used to explain the contents of the claims.
Claims (9)
1. The exchange chip verification system based on the UVM is characterized by comprising a data layer, a control layer and an excitation layer;
the control layer comprises a parameter processing module and an excitation management module; the excitation layer comprises an excitation library; the data layer comprises an exchange chip to be verified, a port input agent, a port output agent, a reference model and a score board;
the parameter processing module is used for receiving and processing the input user parameters;
the excitation library is used for generating test data excitation according to the user parameters;
the excitation management module is used for sending the data excitation to the port input agent;
the port input agent is used for converting the data excitation into signal excitation to be loaded to the exchange chip and simultaneously sending the data excitation to the reference model;
the reference model is used for exciting and processing data and then sending the data to the scoring board;
the port output agent is used for converting the signal excitation output by the exchange chip into data excitation and sending the data excitation to the scoring board;
and the score board is used for comparing the data excitation of the port output agent with the data excitation of the reference model after receiving the data excitation of the port output agent, and outputting a score according to a comparison result.
2. The UVM-based switch chip verification system of claim 1, wherein: the data stimulus includes key fields including one or more of an injection timestamp, an intercept timestamp, packet length information, and an interval time.
3. The UVM-based switch chip verification system of claim 2, wherein: the port input agent comprises N stimulus drivers and N stimulus management; n is not less than 2 and is an integer;
the excitation driver i is used for obtaining data excitation from the excitation management i, wherein i is more than or equal to 0 and less than or equal to N-1, and i is an integer; after the excitation driver i obtains the data excitation, the excitation driver i is used for converting the data into an excitation signal with a corresponding format, and loading the excitation signal to a port i of the exchange chip to complete excitation input; meanwhile, the excitation driver i is also used for sending the data excitation to a port i of the reference model;
the reference model is used for forwarding the data excitation to an output port j of the reference model according to a set routing algorithm and a data grouping processing rule after receiving the data excitation, wherein j is more than or equal to 0 and less than or equal to N-1, and j is an integer;
the scoring board comprises N expected queues and N interception ports, an output port j of the reference model is connected with an expected queue j of the scoring board, and the expected queue j is used for storing data sent by the output port j;
the port output agent comprises N excitation observation modules; the excitation observation module is used for obtaining output signal excitation from an output port k of the exchange chip, wherein k is more than or equal to 0 and less than or equal to N-1, k is an integer, then the signal excitation is converted into data excitation in a corresponding format, and the data excitation is sent to an interception port k of the score board;
and the score counting board is used for searching the data excitation matched with the key field of the data excitation in the expected queue k after the data excitation is obtained by the interception port k, and outputting the test score.
4. The UVM-based switch chip verification system of claim 3, wherein: the signal stimulus comprises an interface format;
the data stimulus also includes a subclass that signal-integrates the fields of the signal stimulus.
5. The exchange chip verification method based on UVM is characterized by comprising the following steps:
s1, generating test data excitation by an excitation library; the data stimulus comprises one or more of an injection timestamp, an interception timestamp, packet length information, and an interval time;
s2, the data excitation enters corresponding excitation management under the control of an excitation management module;
s3, the excitation management converts the data excitation sent to the corresponding excitation driver into signal excitation and loads the signal excitation into an input port of the exchange chip, and meanwhile, the excitation driver sends the data excitation to the reference model;
s4, the reference model converts the input data excitation into expected data excitation according to the function of the exchange chip, and sends the expected data excitation to a corresponding expected queue of the scoring board for storage;
s5, converting the signal excitation into result signal excitation after the signal excitation is input into the exchange chip;
s6, the result signal excitation reaches an output port of the exchange chip, is intercepted and captured by the excitation observation module and is converted into intercepted data excitation, and the intercepted data excitation is sent to the scoring board by the excitation observation module;
and S7, after receiving the intercepted data excitation, the scoring board searches for the matched expected data excitation in the corresponding expected queue, and if the matched expected data excitation is obtained, performance statistics is carried out, and the final function score is output.
6. The UVM based switch chip verification method of claim 5, wherein: the step S1 specifically includes the following contents:
s101, analyzing the user parameters by a parameter processing module, and transmitting the user parameters to an incentive library; the user parameters comprise a data packet length range, a flow model and an injection rate;
and S102, selecting a corresponding excitation generation class according to the flow model by the excitation library, and generating the tested data excitation according to the data grouping length range and the injection rate.
7. The UVM based switch chip verification method of claim 6, wherein: the step S3 is specifically as follows:
s301, the corresponding excitation management i transmits data excitation to an excitation drive i;
s302, the excitation driver i judges whether the data excitation is finished or not, and if so, the step S306 is executed; otherwise, executing step S303;
s303, judging whether data excitation is sent to the reference model or not by the excitation driver i, and if so, executing the step S304; otherwise, the excitation driver i sets the sending time t _ send of the data excitation as the current simulation time, sends the current simulation time to the port i of the reference model, marks the data excitation as sent, sets the interval time iter _ cycle = trans _ item. Wherein trans _ item is a data stimulus;
s304, the excitation driver i converts the data excitation into signal excitation, loads the signal excitation on an interface signal of the exchange chip, and executes the step S305;
s305, the excitation driver i waits for sending the next data excitation, judges whether the waiting time is equal to iter _ cycle, and sends the next data excitation if the waiting time waiting _ cycle = iter _ cycle, and executes the step S302; otherwise, go to step S305;
and S306, finishing data sending.
8. The UVM-based switch chip validation method of claim 7, wherein: the step S7 specifically includes the following contents:
s701, the score counting board judges whether the current simulation time reaches the test duration, and if so, the step S709 is executed; otherwise, go to step S702;
s702, the interception port k of the score counting board receives the interception data excitation and executes the step S703;
s703, the score board judges whether the expected queue k is empty, if so, the step S706 is executed; otherwise, executing step S704;
s704, judging whether to search a matched expected data excitation in an expected queue k by taking the key field of the intercepted data excitation as an index, if so, executing a step S705, otherwise, executing a step S706;
s705, judging the function score by the score counting board, and executing the step S707;
s706, judging that the score is not scored by the scoring board, deleting the captured data excitation, and executing the step S701;
s707, calculating statistical data according to the following formula, and then executing the step S701;
port i intercepts and captures the total amount of data, pkt _ len _ port [ i ] = pkt _ len _ port [ i ] + exp _ item. Where exp _ item.pke _ len refers to the amount of data that is expected to be data-driven;
the total amount of intercepted data of the port i is pkt _ num _ port [ i ] = pkt _ num _ port [ i ] +1;
the sum of the consumed time of port i data packets is pkt _ delay _ port [ i ] = pkt _ delay _ port [ i ] + act _ item.t _ rcv-exp _ item.t _ snd; wherein act _ item.t _ rcv refers to the capture time of capturing the data stimulus, and exp _ item.t _ snd refers to the injection time of the desired data stimulus;
s709, counting and outputting the final function score, and executing the step S710;
s710, outputting the final performance statistical data according to the following formula, and executing a step S711;
port average bandwidth: avg _ bw _ port [ i ] = pkt _ len _ port [ i ]/t _ sim; wherein t _ sim refers to simulation time;
average throughput of chips: avg _ throughput = pkt _ len _ sum/t _ sim;
port average delay: avg _ lt _ port [ i ] = pkt _ delay _ port [ i ]/pkt _ num _ port [ i ];
average time delay of the chip; avg _ latency = pkt _ delay _ sum/pkt _ num _ port [ i ];
average flux of the chip: avg _ pkt _ prc = pkt _ num _ sum/t _ sim; the pkt _ num _ sum refers to the total number of data intercepted by each port;
and S711, completing the test.
9. A storage medium, characterized in that the storage medium stores a computer program which, when executed by a processor, carries out the steps of the method according to any one of claims 5-8.
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