CN115691648A

CN115691648A - Memory reliability testing method and device, storage medium and electronic equipment

Info

Publication number: CN115691648A
Application number: CN202211349912.0A
Authority: CN
Inventors: 张建
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-10-31
Filing date: 2022-10-31
Publication date: 2023-02-03

Abstract

The disclosure relates to a method and a device for testing reliability of a memory, a storage medium and an electronic device. The method comprises the following steps: sending a plurality of write command signals to a memory; acquiring a data strobe signal and a clock signal corresponding to the data strobe signal, which are generated after each write command signal is received by a memory; acquiring data gating superposed signals and clock superposed signals under a plurality of write command signals according to the data gating signals generated after each write command signal and the corresponding clock signals; determining a phase difference starting point according to the allowable range of the phase difference between the data strobe signal and the clock signal and the phase difference end point; determining a phase difference maximum value and a phase difference minimum value according to a phase difference end point and a phase difference starting point based on the clock superposition signal and the data gating superposition signal; and comparing the maximum phase difference value and the minimum phase difference value with the allowable phase difference range respectively, and judging whether the memory meets the requirement of data writing reliability. A method of determining the timing parameter tDQSS is provided.

Description

Memory reliability testing method and device, storage medium and electronic equipment

Technical Field

The present disclosure relates to the field of integrated circuit technologies, and in particular, to a method and an apparatus for testing reliability of a memory, a computer-readable storage medium, and an electronic device.

Background

Dynamic Random Access Memory (DRAM) is a semiconductor Memory device commonly used in computers, and has been widely used in the computer field and the electronic industry due to its advantages of simple structure, high density, low power consumption, low price, and the like.

In a DRAM write, the most important timing parameter that cannot be violated is tDQSS (time for data to be input to the first DQS transition edge). tDQSS must be within the protocol specifications. If tDQSS is outside the specified range, erroneous data may be written.

Therefore, the accurate determination of tDQSS is of great significance to data write reliability.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The present disclosure provides a method and an apparatus for testing reliability of a memory, and an electronic device, and provides a method for determining a timing parameter tDQSS.

Additional features and advantages of the disclosure will be set forth in the detailed description which follows, or in part will be obvious from the description, or may be learned by practice of the invention.

According to a first aspect of the present disclosure, there is provided a memory reliability test method, the method comprising: sending a plurality of write command signals to a memory; acquiring a data strobe signal and a clock signal corresponding to the data strobe signal, which are generated after each write command signal is received by the memory; acquiring data gating superposed signals and clock superposed signals under a plurality of write command signals according to the data gating signals generated after each write command signal and the corresponding clock signals; determining a phase difference starting point according to the allowable range of the phase difference between the data strobe signal and the clock signal and the phase difference end point; determining a phase difference maximum value and a phase difference minimum value according to the phase difference end point and the phase difference starting point based on the clock superposition signal and the data gating superposition signal; and comparing the maximum phase difference value and the minimum phase difference value with the allowable phase difference range respectively, and judging whether the memory meets the requirement of data writing reliability.

In an exemplary embodiment of the present disclosure, the determining a phase difference starting point according to a phase difference allowable range of a data strobe signal and a clock signal and a phase difference ending point includes: setting an initial rising edge of the clock superposition signal where the phase difference starting point is located; determining a phase difference average value of the middle position of the initial rising edge from the phase difference end point; judging whether the average phase difference value is within the allowable range of the phase difference; if so, determining the initial rising edge as a target rising edge where the phase difference starting point is located; if not, the initial rising edge is moved forwards or backwards, and the corresponding phase difference average value from the phase difference end point is determined until the target rising edge is determined.

In an exemplary embodiment of the present disclosure, the determining the average value of the phase difference between the middle position of the initial rising edge and the phase difference end point includes: and determining the difference value between the average value of the data strobe signals at the middle position of the rising edge where the phase difference end point is located and the average value of the clock signals at the middle position of the initial rising edge as the average value of the phase difference.

In an exemplary embodiment of the present disclosure, the determining a maximum phase difference value and a minimum phase difference value according to the end phase difference point and the start phase difference point based on the clock superposition signal and the data strobe superposition signal includes: determining a first maximum value and a first minimum value of the middle position of the rising edge where the phase difference end point is located based on the data gating superposition signal; determining a second maximum value and a second minimum value of the middle position of the rising edge where the phase difference starting point is located based on the clock superposition signal; determining the difference value between the first maximum value and the second minimum value as the maximum value of the phase difference; and determining the difference value of the first minimum value and the second maximum value as the phase difference minimum value.

In an exemplary embodiment of the present disclosure, the comparing the maximum phase difference value and the minimum phase difference value with the allowable phase difference range to determine whether the memory meets the data writing reliability requirement includes: if the maximum phase difference value and the minimum phase difference value are both within the phase difference allowable range, determining that the memory meets the requirement of data writing reliability; and if the maximum phase difference value or the minimum phase difference value is not in the allowable range of the phase difference, determining that the memory does not meet the requirement of data writing reliability.

In an exemplary embodiment of the present disclosure, the method further includes: the number of the write command signals transmitted to the memory is greater than a preset number.

In an exemplary embodiment of the present disclosure, the obtaining, according to a data strobe signal generated after each write command signal and a clock signal corresponding to the data strobe signal, a data strobe superimposed signal and a clock superimposed signal under a plurality of write command signals includes: superposing the data gating signals under the plurality of write command signals to obtain the data gating superposed signals; and superposing the clock signals under the plurality of write command signals to obtain the clock superposed signal.

According to a second aspect of the present disclosure, there is provided a memory reliability test apparatus, the apparatus comprising: a command sending module for sending a plurality of write command signals to the memory; the signal acquisition module is used for acquiring a data strobe signal and a clock signal corresponding to the data strobe signal, which are generated after the memory receives each write command signal; the signal superposition module is used for acquiring data gating superposition signals and clock superposition signals under a plurality of write command signals according to the data gating signals generated after each write command signal and the corresponding clock signals; the starting point determining module is used for determining a phase difference starting point on the clock superposition signal according to the phase difference allowable range and the phase difference end point of the data strobe signal and the clock signal; the mode determining module is used for determining the maximum value and the minimum value of the phase difference according to the phase difference end point and the phase difference starting point on the basis of the clock superposition signal and the data gating superposition signal; and the judging module is used for comparing the maximum phase difference value and the minimum phase difference value with the allowable phase difference range respectively and judging whether the memory meets the requirement of data writing reliability.

In an exemplary embodiment of the disclosure, the starting point determining module is configured to set an initial rising edge of the clock superposition signal where the phase difference starting point is located; determining a phase difference average value of the middle position of the initial rising edge from the phase difference end point; judging whether the average phase difference value is within the allowable range of the phase difference; if so, determining the initial rising edge as a target rising edge where the phase difference starting point is located; if not, the initial rising edge is moved forwards or backwards, and the corresponding phase difference average value from the phase difference end point is determined until the target rising edge is determined.

In an exemplary embodiment of the disclosure, the starting point determining module is configured to determine a difference between an average value of the data strobe signal at the middle position of the rising edge where the phase difference ending point is located and an average value of the clock signal at the middle position of the initial rising edge as the average value of the phase difference.

In an exemplary embodiment of the disclosure, the most significant determination module is configured to determine, based on the data strobe overlapping signal, a first maximum value and a first minimum value of a middle position of a rising edge where the phase difference end point is located; determining a second maximum value and a second minimum value of the middle position of the rising edge where the phase difference starting point is located based on the clock superposition signal; determining a difference value between the first maximum value and the second minimum value as the phase difference maximum value; and determining the difference value of the first minimum value and the second maximum value as the phase difference minimum value.

In an exemplary embodiment of the disclosure, the determining module is configured to determine that the memory meets a data write reliability requirement if the maximum phase difference value and the minimum phase difference value are both within the allowable phase difference range; and if the maximum phase difference value or the minimum phase difference value is not in the allowable range of the phase difference, determining that the memory does not meet the requirement of data writing reliability.

In an exemplary embodiment of the present disclosure, the apparatus further includes: the number of the write command signals transmitted to the memory is greater than a preset number.

In an exemplary embodiment of the present disclosure, the signal superimposing module is configured to superimpose the data strobe signals under a plurality of write command signals to obtain the data strobe superimposed signal; and superposing the clock signals under the plurality of write command signals to obtain the clock superposed signal.

According to a third aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored, which computer program, when executed by a processor, implements the above-mentioned memory reliability testing method.

According to a fourth aspect of the present disclosure, there is provided an electronic device comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the memory reliability testing method described above via execution of the executable instructions.

The technical scheme provided by the disclosure can comprise the following beneficial effects:

the method for testing the reliability of the memory, provided by the embodiment of the disclosure, includes the steps of sending a plurality of write command signals to the memory, acquiring a data strobe signal and a corresponding clock signal generated under each write command signal, and acquiring a data strobe superposition signal and a clock superposition signal under the plurality of write command signals according to the data strobe signal and the corresponding clock signal generated under each write command signal; after the phase difference starting point is determined according to the phase difference allowable range and the phase difference end point, the maximum value and the minimum value of the phase difference can be determined according to the phase difference end point and the phase difference starting point on the basis of the clock superposition signal and the data gating superposition signal, and finally, the maximum value and the minimum value of the phase difference are respectively compared with the phase difference allowable range to judge whether the memory meets the data writing reliability requirement, so that a relatively strict test method for the writing reliability of the memory is provided, further, whether the jitter of the signal is overlarge can be judged, and data support is provided for the use reliability of the memory.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty. In the drawings:

FIG. 1 schematically illustrates a partial timing diagram of a DRAM according to an exemplary embodiment of the present disclosure;

FIG. 2 schematically illustrates a flow chart of steps of a method for memory reliability testing, according to an exemplary embodiment of the present disclosure;

FIG. 3 schematically illustrates waveforms of a data strobe signal and its corresponding clock signal generated by a memory device after receiving a write command signal according to an exemplary embodiment of the present disclosure;

FIG. 4 schematically illustrates a data strobe superimposed signal and clock superimposed signal waveform diagram obtained after superimposing according to an exemplary embodiment of the disclosure;

FIG. 5 schematically illustrates two sets of data strobe signals versus clock signals according to an exemplary embodiment of the disclosure;

FIG. 6 schematically shows a flowchart of the steps for determining a phase difference starting point from a superimposed data strobe superimposed signal and a clock superimposed signal according to an exemplary embodiment of the disclosure;

FIG. 7 schematically shows a block diagram of a memory reliability testing apparatus according to an exemplary embodiment of the present disclosure;

fig. 8 schematically shows a module diagram of an electronic device according to an exemplary embodiment of the present disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and a repetitive description thereof will be omitted.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the embodiments of the disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and so forth. In other instances, well-known structures, methods, devices, implementations, materials, or operations are not shown or described in detail to avoid obscuring aspects of the disclosure.

The block diagrams shown in the figures are functional entities only and do not necessarily correspond to physically separate entities. That is, these functional entities may be implemented in software, or in one or more software-hardened modules, or in different networks and/or processor devices and/or microcontroller devices.

DRAM is a data storage device commonly used at present, and the data storage is realized by charging and discharging a capacitor of each memory cell, so as to control a high level or a low level of stored data, corresponding to data 1 or 0. The DRAM generally stores data after receiving a data write command.

DQS (Data Strobe Signal) is used for Signal synchronization between the memory and the memory controller. And a DQ signal transmitting end transmits a DQS data strobe signal, and a signal receiving end triggers the data receiving according to the upper edge and the lower edge of the DQS data strobe signal. Briefly, if the signal is read from the memory, the main board (memory controller) determines when to receive the read data according to the DQS data strobe signal sent from the memory. If a write is made, the memory triggers the receipt of the data based on the DQS issued by the Northbridge, as opposed to just the other.

In general, data is written from the memory control terminal to the DRAM terminal, and after the DRAM receives a write command, the DQS data strobe signal will toggle for a period of time to ensure that the DQS data strobe signal is in a stable state, where the aforementioned time to toggle is called tWPRE, where tWPRE is the first negative pulse parameter (preamble parameter) of the write operation. Referring to FIG. 1, a partial timing diagram of a DRAM is shown, including tWPRE and tDQSS.

After the tWPRE, the DQ data signal starts toggle and starts to transmit data. However, the DQS data strobe signal is synchronized with the clock signal before data is transferred to ensure the correctness of the data transfer. At this time, the phase difference between the DQS data strobe signal and the CK clock signal is referred to as tDQSS. Wherein CK represents the clock signal clock, as shown in FIG. 1.

The most important timing parameter that the DRAM cannot violate when writing data is tDQSS, where tDQSS is also referred to as the time when data is input to the first valid DQS transition edge, i.e., the time difference between the rising edge of the DQS data strobe signal and the corresponding rising edge of the CK clock signal, indicates the relative position of the data valid signal DQS with respect to the clock signal CK. tDQSS is required to be between the allowable ranges specified by the protocol. If tDQSS is outside the specified tolerance, erroneous data may be written.

However, in practical situations, jitter (jitter) of the signal is usually present during transmission, and if the jitter of the signal is too large, the phase difference between the DQS data strobe signal and the CK clock signal, i.e. tDQSS value, may be affected. Specifically, the minimum value or the maximum value of tDQSS may exceed an allowable range defined by a standard, and erroneous data may be written, which may result in deterioration of writing reliability of the memory.

Based on this, the exemplary embodiments of the present disclosure first provide a memory reliability test method for evaluating the write reliability of a memory.

Referring to fig. 2, a flow chart of steps of a method for testing reliability of a memory according to an embodiment of the present disclosure is shown. In a possible implementation, the method for testing reliability of a memory may include:

step S210, sending a plurality of write command signals to a memory;

step S220, acquiring a data strobe signal and a corresponding clock signal which are generated after the memory receives each write command signal;

step S230, acquiring data gating superposed signals and clock superposed signals under a plurality of write command signals according to the data gating signals generated after each write command signal and the corresponding clock signals;

step S240, determining a phase difference starting point according to the allowable range and the end point of the phase difference of the data strobe signal and the clock signal;

step S250, determining a phase difference maximum value and a phase difference minimum value according to a phase difference end point and a phase difference starting point based on the clock superposition signal and the data gating superposition signal;

and step S260, comparing the maximum phase difference value and the minimum phase difference value with the allowable phase difference range respectively, and judging whether the memory meets the requirement of data writing reliability.

The method for testing the reliability of the memory provided by the embodiment of the disclosure comprises the steps of sending a plurality of write command signals to the memory, acquiring a data gating signal and a corresponding clock signal generated under each write command signal, and acquiring a data gating superposed signal and a clock superposed signal under the plurality of write command signals according to the data gating signal and the corresponding clock signal generated under each write command signal; after the phase difference starting point is determined according to the phase difference allowable range and the phase difference ending point, the maximum phase difference value and the minimum phase difference value can be determined according to the phase difference ending point and the phase difference starting point on the basis of the clock superposition signal and the data gating superposition signal, and finally, the maximum phase difference value and the minimum phase difference value are respectively compared with the phase difference allowable range to judge whether the memory meets the data writing reliability requirement, so that a method for strictly testing the writing reliability of the memory is provided, further, whether the jitter of the signal is overlarge can be judged, and data support is provided for the use reliability of the memory.

The following detailed description will be made of a method for testing reliability of a memory according to an embodiment:

in step S210, a plurality of write command signals are sent to the memory.

In practical applications, a write command signal is usually sent to the memory through a Central Processing Unit (CPU), and specifically, the CPU writes the content in the data register into the memory. In the writing operation process, an address register of a CPU firstly puts a memory cell of a memory to be written with data on an address bus, and then selects the memory cell through an address decoder; the CPU then places the contents of the data register on the data bus and the CPU sends a "write" control signal to the memory, under the control of which the contents of the data register are written to the addressed memory cell.

In general, the memory does not transmit data immediately after receiving the write command signal, but the DQS data strobe signal is first toggled for a period of time to ensure that the DQS data strobe signal is in a stable state before the DQ signal begins to toggle to transmit data. The time that the DQS data strobe signal toggles is called the first negative pulse parameter tWPRE for the write operation. The time length of the first negative pulse parameter tWPRE is approximately twice the clock unit, i.e., 2 × tck.

In the exemplary embodiments of the present disclosure, in order to detect the influence of signal jitter on the data strobe signal DQS and the clock signal CK, it is necessary to transmit a plurality of write command signals into the memory to acquire the plurality of pairs of data strobe signals DQS and the clock signal CK under the plurality of write command signals.

In practical application, a plurality of write command signals are sequentially sent to the memory, and after the previous write command signal is executed, the next write command signal is sent and executed. Also, the time interval between two adjacent write command signals may be set according to practical situations, for example, one clock unit or two clock units, and the like.

It should be noted that, in an actual operation process, the plurality of write command signals may write the same data into the same memory cell, may write different data into the same memory cell, or may write different data into different memory cells in the memory, which is not limited in this exemplary embodiment of the disclosure.

In practical applications, the number of the plurality of write command signals sent to the memory may be determined according to practical situations, for example, may be several hundred, may also be several thousand, and the like.

In step S220, a data strobe signal generated by the memory after receiving each write command signal and a corresponding clock signal are obtained.

In practical application, in the process of acquiring the data strobe signal and the clock signal generated by the memory, the data point signal may be acquired, and the corresponding waveform signal may also be acquired. In the exemplary embodiments of the present disclosure, it is preferable to acquire waveform signals of the data strobe signal and the clock signal to facilitate phase difference determination of the data strobe signal and the clock signal.

In the process of actually acquiring the waveform signals of the data strobe signal and the clock signal, there may be a plurality of different capturing modes, for example, a normal capturing mode, a maximum value capturing mode, a mean value capturing mode, a high pixel capturing mode, and the like may be included.

The conventional acquisition mode is to sample the data signals according to the same interval time to establish a waveform, and is suitable for the situation that no special requirement is required for waveform acquisition.

The highest value capture mode is mainly used for collecting the highest value and the minimum value of the sampling interval data signals and is suitable for capturing the burrs of narrow single pulses and high frequencies which are possibly caused.

The mean value capturing mode can align two ends of the collected N sections of waveforms, then carry out mean value calculation on the N sections of waveforms, and finally obtain a section of averaged waveform, so that the method is suitable for reducing random noise in the waveform and improving the resolution of a vertical screen.

The high pixel capture mode selects an oversampling technique to average adjacent points of the sampled waveform, reducing random noise on the input data signal and creating a smoother waveform on the display screen. Specifically, every N points in a segment of waveform are averaged, and the original N sampling points are replaced by an average value point to indicate. The sampling frequency of the digitizer is generally higher than the storage speed of the collecting storage.

In the exemplary embodiment of the present disclosure, in the process of acquiring the waveform signals of the data strobe signal and the clock signal, any one of the above manners may be selected according to actual situations. Referring to fig. 3, a waveform diagram of a data strobe signal and its corresponding clock signal generated after a write command signal is received by a memory according to an exemplary embodiment of the present disclosure is shown.

In step S230, a data strobe superposition signal and a clock superposition signal under a plurality of write command signals are obtained according to the data strobe signal generated after each write command signal and the corresponding clock signal.

In practical applications, the data strobe signals and the corresponding clock signals under the multiple write command signals are superimposed, which means that the multiple data strobe signals under the multiple write command signals are superimposed respectively, and the multiple clock signals under the multiple write command signals are superimposed.

In a specific stacking process, the stacked data strobe signal and the clock signal need to be aligned, and in the alignment process, the alignment may be performed with the received write command signal as a starting point, or the alignment may be performed with other points as starting points, which is not particularly limited in the exemplary embodiment of the present disclosure.

Referring to fig. 4, a data strobe superimposed signal DQS 'and a clock superimposed signal CK' obtained after being superimposed according to the above-described method in the exemplary embodiment of the disclosure are shown, and compared with the data strobe signal DQS and the clock signal CK in fig. 3, the data strobe superimposed signal DQS 'and the clock superimposed signal CK' are significantly thicker than lines of the data strobe signal DQS and the clock signal CK, which illustrates that there may be jitter in the signals during transmission.

In step S240, a phase difference starting point is determined according to the allowable range of the phase difference between the data strobe signal and the clock signal and the phase difference ending point.

Typically, the end point of the data strobe signal out of phase with the clock signal tDQSS, i.e., the phase difference end point, is the middle position of the third rising edge of the data strobe superimposed signal.

However, in practical applications, the starting point of the phase difference tDQSS between the data strobe signal and the clock signal, i.e., the starting point of the phase difference, may not be fixed. For example, as shown in fig. 5, the corresponding phase difference starting point is different according to the difference of the signal frequency, for example, when the frequency of the clock signal CK is low, the phase difference starting point M1 is the 2 nd rising edge of the clock signal CK within the phase difference of the same time; when the frequency of the clock signal CK is high, the phase difference starting point M1 is the 3 rd rising edge of the clock signal CK within the phase difference at the same time.

Therefore, the phase difference starting point needs to be determined according to the phase difference end point and the phase difference allowable range, and specifically, in the determination process, the phase difference starting point may be determined according to the data strobe superimposed signal and the clock superimposed signal after the superimposition, or may be determined according to any one of the data strobe signal and the clock signal before the superimposition.

When the phase difference starting point is determined according to any one of the data strobe signals and the clock signal before superposition, the phase difference end point, namely the middle position of the third rising edge of the data strobe signal, namely the position of 0 point, can be determined; and determining a first clock signal rising edge adjacent to a third rising edge of the data strobe signal forwards from the phase difference end point, calculating a first length from the middle position of the third rising edge of the data strobe signal to the middle position of the first clock signal rising edge, judging whether the first length is within the phase difference allowable range, and if so, determining that the middle position of the first clock signal rising edge is the phase difference starting point.

If not, counting one more clock pulse, determining a second rising edge of the clock signal, calculating a second length from the middle position of the third rising edge of the data strobe signal to the middle position of the second rising edge of the clock signal, judging whether the second length is within the allowable range of the phase difference, and if so, determining that the middle position of the second rising edge of the clock signal is the phase difference starting point. If not, continuing to count a clock pulse forward, and continuing to judge until determining the phase difference starting point.

And if the rising edge of the clock signal meeting the phase difference allowable range is not found in the process of determining the phase difference starting point, directly determining that the data writing reliability problem exists in the memory.

When determining the phase difference starting point according to the superimposed data strobe signal and the clock superimposed signal, referring to fig. 6, the method may include the following steps;

first, proceeding to step S601, an initial rising edge of the clock superposition signal where the phase difference starting point is located may be set, for example, an nth rising edge is set as the phase difference starting point; next, step S602 is performed to determine an average value of the phase difference between the intermediate position of the initial rising edge and the phase difference end point, which is equivalent to determining an average value of the phase difference from the nth rising edge to the phase difference end point; then, step S603 is performed, that is, the determination condition is entered, and it is determined whether the average phase difference value is within the allowable phase difference range; if yes, the process proceeds to step S604, and the nth rising edge is determined as the target rising edge where the phase difference starting point is located, that is, the nth rising edge is determined as the target rising edge; if not, the process proceeds to step S605, where the initial rising edge is moved forward or backward, that is, the nth-1 or N +1 rising edge is determined as the nth rising edge, that is, the phase difference starting point, and then the process proceeds to step S601, that is, the average value of the phase difference between the rising edge and the phase difference ending point is determined, until the target rising edge is determined.

Specifically, in the process of determining the average value of the phase difference between the middle position of the initial rising edge and the phase difference end point, the difference between the average value of the data strobe signal at the middle position of the rising edge where the phase difference end point is located on the data strobe superimposed signal and the average value of the clock signal at the middle position of the initial rising edge on the clock superimposed signal may be determined as the average value of the phase difference.

That is, in the process of determining the average value of the phase difference from the nth rising edge to the phase difference end point, the difference between the average value of the data strobe signal at the middle position of the rising edge where the phase difference end point is located and the average value of the clock signal at the middle position of the nth rising edge on the clock superimposed signal is also determined as the average value of the phase difference on the data strobe superimposed signal.

In step S250, a phase difference maximum value and a phase difference minimum value are determined from the phase difference end point and the phase difference start point based on the clock superimposed signal and the data strobe superimposed signal.

In the exemplary embodiments of the present disclosure, after the phase difference starting point is determined, the maximum phase difference value and the minimum phase difference value of the phase difference between the data strobe signal and the clock signal may be determined according to the phase difference ending point on the data strobe superimposed signal and according to the phase difference starting point on the clock superimposed signal.

As can be seen from fig. 4, due to the jitter, the width of the signal curve corresponding to the superimposed data strobe signal or the signal curve corresponding to the superimposed clock signal is large. Therefore, a certain error exists in the data writing reliability of the memory judged only according to the determined phase difference average value of the phase difference between the data strobe signal and the clock signal, and the final judgment result is influenced.

Therefore, in the exemplary embodiment of the present disclosure, the maximum phase difference value and the minimum phase difference value of the phase difference between the data strobe signal and the clock signal are used to determine the data writing reliability of the memory, so that the influence of the jitter of the signal can be taken into consideration, and the accuracy of determining the data writing reliability of the memory can be improved.

Specifically, there may be a plurality of different determination rules in determining the maximum value and the minimum value of the phase difference between the data strobe signal and the clock signal. For example, the maximum value of the phase difference between the data strobe signal and the clock signal can be determined according to the maximum value of the end point of the phase difference on the width of the curve corresponding to the data strobe superposition signal and the maximum value of the start point of the phase difference on the width of the curve corresponding to the clock superposition signal; and determining the minimum phase difference value of the phase difference between the data gating signal and the clock signal according to the minimum value of the phase difference end point on the width of the curve corresponding to the data gating and overlapping signal and the minimum value of the phase difference start point on the width of the curve corresponding to the clock overlapping signal.

In the exemplary embodiments of the present disclosure, in order to further improve the accuracy of the data writing reliability judgment of the memory, more stringent judgment conditions are set, that is, more stringent determination rules are set in determining the maximum value and the minimum value of the phase difference between the data strobe signal and the clock signal phase difference.

The method specifically comprises the following steps: firstly, based on the superimposed data gating superimposed signal, determining a first maximum value and a first minimum value of a middle position of a rising edge where a phase difference end point is located, that is, determining a maximum value and a minimum value of a curve width at the middle position of the rising edge of the data gating superimposed signal where the phase difference end point is located as the first maximum value and the first minimum value; then, based on the superimposed clock superimposed signal, a second maximum value and a second minimum value of the middle position of the rising edge where the phase difference starting point is located are determined, that is, a maximum value and a minimum value of the width of the curve at the middle position of the rising edge of the clock superimposed signal where the phase difference starting point is located are determined as the second maximum value and the second minimum value.

After determining the first maximum value and the first minimum value on the data strobe superimposed signal and the second maximum value and the second minimum value on the clock superimposed signal, the difference between the first maximum value and the second minimum value may be determined as the maximum value of the phase difference, that is, the maximum value of the phase difference between the data strobe superimposed signal and the clock signal may be determined using the maximum value of the end point of the phase difference on the data strobe superimposed signal and the minimum value of the start point of the phase difference on the clock superimposed signal. Referring to fig. 4, M3 represents a first maximum value, M4 represents a second minimum value, and the difference between M3 and M4 is the maximum value of the phase difference between the data strobe signal and the clock signal, i.e., tDQSS maximum value.

Further, after determining the first maximum value and the first minimum value on the data strobe superimposed signal and the second maximum value and the second minimum value on the clock superimposed signal, the difference between the first minimum value and the second maximum value may be determined as the phase difference minimum value, that is, the minimum value of the phase difference between the data strobe superimposed signal and the clock signal may be determined by using the minimum value of the phase difference end point on the data strobe superimposed signal and the maximum value of the phase difference start point on the clock superimposed signal. Referring to fig. 4, M5 represents a second minimum value, M6 represents a second maximum value, and the difference between M5 and M6 is the minimum value of the phase difference between the data strobe signal and the clock signal, i.e., tDQSS minimum value.

In the exemplary embodiment of the present disclosure, in the process of determining the maximum value and the minimum value of the phase difference between the data strobe signal and the clock signal, the maximum value of the phase difference between the data strobe signal and the clock signal is determined using the maximum value of the phase difference end point on the data strobe superposition signal and the minimum value of the phase difference start point on the clock superposition signal, and the maximum value of the phase difference in a wider range can be determined; the method has the advantages that the minimum value of the phase difference between the data strobe signal and the clock signal is determined by using the minimum value of the phase difference end point on the data strobe superposition signal and the maximum value of the phase difference starting point on the clock superposition signal, the minimum value of the phase difference in a narrower range can be determined, the phase difference range of the determined data strobe signal and the clock signal is larger, the omission of the phase difference value of the data strobe signal and the clock signal can be avoided to the greatest extent, all the values of the phase difference between the data strobe signal and the clock signal can be included as much as possible, the accuracy of determining the phase difference between the data strobe signal and the clock signal is provided, the coverage range is widened as much as possible, and a basis is further provided for the accuracy of subsequently judging the data writing reliability of the memory.

In step S260, the maximum phase difference value and the minimum phase difference value are compared with the allowable phase difference range, respectively, to determine whether the memory meets the data write reliability requirement.

In the exemplary embodiment of the present disclosure, after the maximum value and the minimum value of the phase difference between the data strobe signal and the clock signal are determined according to the method in step S250, the data writing reliability may be judged according to the determined maximum value and the determined minimum value of the phase difference. The phase difference is determined by comparing with the allowable range of the phase difference of the data strobe signal and the clock signal specified in the standard.

Specifically, in the judgment process, if the maximum phase difference value and the minimum phase difference value both fall within the allowable phase difference range, the memory is determined to meet the data writing reliability requirement; and if one of the maximum phase difference value and the minimum phase difference value is not in the allowable range of the phase difference, determining that the memory does not meet the requirement of data writing reliability.

In practical applications, the specific size of the allowable phase difference range may be determined according to practical situations, for example, the allowable phase difference range may be between 0.75 × tck and 1.25 × tck, and the exemplary embodiment of the present disclosure is not particularly limited to the specific size of the allowable phase difference range.

In practical applications, if it is determined that the memory does not satisfy the data writing reliability requirement, the sending of the write command signal to the memory needs to be stopped, and the memory needs to be troubleshooting, so as to determine the reason causing the data writing reliability problem to the memory. The exemplary embodiments of the present disclosure are not described in detail for specific reasons of cause.

In summary, in the method for testing reliability of a memory provided by the embodiment of the present disclosure, on one hand, a plurality of write command signals are sent to the memory, a data strobe signal and a corresponding clock signal generated under each write command signal are obtained, and a data strobe superposition signal and a clock superposition signal under the plurality of write command signals are obtained according to the data strobe signal and the corresponding clock signal generated under each write command signal; after the phase difference starting point is determined according to the phase difference allowable range and the phase difference ending point, the maximum phase difference value and the minimum phase difference value can be determined according to the phase difference ending point and the phase difference starting point on the basis of the clock superposition signal and the data gating superposition signal, and finally, the maximum phase difference value and the minimum phase difference value are respectively compared with the phase difference allowable range to judge whether the memory meets the data writing reliability requirement, so that a method for strictly testing the writing reliability of the memory is provided, further, whether the jitter of the signal is overlarge can be judged, and data support is provided for the use reliability of the memory.

On the other hand, in the exemplary embodiment of the present disclosure, in determining the maximum value and the minimum value of the phase difference between the data strobe signal and the clock signal, the maximum value of the phase difference between the data strobe signal and the clock signal may be determined using the maximum value of the phase difference end point on the data strobe superimposed signal and the minimum value of the phase difference start point on the clock superimposed signal, and the maximum value of the phase difference of the wider range may be determined; the minimum value of the phase difference of the data gating signal and the clock signal is determined by using the minimum value of the phase difference end point on the data gating superposition signal and the maximum value of the phase difference start point on the clock superposition signal, and the minimum value of the phase difference in a narrower range can be determined, so that the determined range of the phase difference of the data gating signal and the clock signal is wider, the omission of the phase difference value of the data gating signal and the clock signal can be avoided to the greatest extent, all values of the phase difference of the data gating signal and the clock signal can be included as much as possible, the accuracy of determining the phase difference of the data gating signal and the clock signal is provided, the coverage range is widened as much as possible, and the accuracy of the data writing reliability of the memory is further improved.

It is noted that although the steps of the methods of the present invention are depicted in the drawings in a particular order, this does not require or imply that the steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken into multiple step executions, etc.

In addition, in the present exemplary embodiment, a memory reliability test apparatus is also provided. Referring to fig. 7, the memory reliability test apparatus 700 may include: a command sending module 710, a signal obtaining module 720, a signal superimposing module 730, a starting point determining module 740, a most value determining module 750, and a determining module 760, wherein:

a command sending module 710 for sending a plurality of write command signals to the memory;

a signal obtaining module 720, configured to obtain a data strobe signal generated after each write command signal is received by the memory and a clock signal corresponding to the data strobe signal;

the signal superposition module 730 is configured to obtain a data gating superposition signal and a clock superposition signal under multiple write command signals according to the data gating signal generated after each write command signal and a clock signal corresponding to the data gating signal;

a starting point determining module 740, configured to determine a phase difference starting point on the clock superposition signal according to the allowable range of the phase difference between the data strobe signal and the clock signal and the phase difference ending point;

a maximum value determining module 750, configured to determine a maximum value and a minimum value of the phase difference according to the phase difference end point and the phase difference start point based on the clock superposition signal and the data gating superposition signal;

the determining module 760 is configured to compare the maximum phase difference value and the minimum phase difference value with the allowable phase difference range, and determine whether the memory meets the requirement of data writing reliability.

In an exemplary embodiment of the disclosure, the starting point determining module 740 is configured to set an initial rising edge of the clock superposition signal where the phase difference starting point is located; determining the average value of the phase difference between the middle position of the initial rising edge and the phase difference end point; judging whether the average value of the phase difference is within the allowable range of the phase difference; if so, determining that the initial rising edge is a target rising edge where the phase difference starting point is located; if not, the initial rising edge is moved forwards or backwards, and the corresponding phase difference average value from the phase difference end point is determined until the target rising edge is determined.

In an exemplary embodiment of the disclosure, the starting point determining module 740 is configured to determine a difference value between an average value of the data strobe signal at a middle position of the rising edge where the phase difference ending point is located and an average value of the clock signal at a middle position of the initial rising edge as the phase difference average value.

In an exemplary embodiment of the present disclosure, the maximum value determining module 750 is configured to determine a first maximum value and a first minimum value of a middle position of a rising edge where the phase difference end point is located, based on the data strobe overlapping signal; determining a second maximum value and a second minimum value of the middle position of the rising edge where the phase difference starting point is located based on the clock superposition signal; determining the difference value between the first maximum value and the second minimum value as the maximum value of the phase difference; and determining the difference value between the first minimum value and the second maximum value as the phase difference minimum value.

In an exemplary embodiment of the disclosure, the determining module 760 is configured to determine that the memory meets the data writing reliability requirement if the maximum phase difference value and the minimum phase difference value are both within the allowable phase difference range; and if the maximum value or the minimum value of the phase difference is not in the phase difference allowable range, determining that the memory does not meet the requirement of data writing reliability.

In an exemplary embodiment of the disclosure, the apparatus further comprises: the number of write command signals sent to the memory is greater than a preset number.

In an exemplary embodiment of the present disclosure, the signal superimposing module 730 is configured to superimpose the data strobe signals under the plurality of write command signals to obtain a data strobe superimposed signal; and superposing the clock signals under the plurality of write command signals to obtain a clock superposed signal.

The details of the virtual module of each memory reliability testing apparatus are described in detail in the corresponding memory reliability testing method, and therefore, are not described herein again.

It should be noted that although several modules or units of the memory reliability test device are mentioned in the above detailed description, such division is not mandatory. Indeed, the features and functions of two or more modules or units described above may be embodied in one module or unit, according to embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units.

In an exemplary embodiment of the present disclosure, an electronic device capable of implementing the above method is also provided.

As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method or program product. Thus, various aspects of the invention may be embodied in the form of: an entirely hardware embodiment, an entirely software embodiment (including firmware, microcode, etc.) or an embodiment combining hardware and software aspects that may all generally be referred to herein as a "circuit," module "or" system.

An electronic device 800 according to this embodiment of the invention is described below with reference to fig. 8. The electronic device 800 shown in fig. 8 is only an example and should not bring any limitations to the function and scope of use of the embodiments of the present invention.

As shown in fig. 8, the electronic device 800 is in the form of a general purpose computing device. The components of the electronic device 800 may include, but are not limited to: the at least one processing unit 810, the at least one memory unit 820, a bus 830 connecting different system components (including the memory unit 820 and the processing unit 810), and a display unit 840.

Wherein the storage unit 820 stores program code that can be executed by the processing unit 810, causing the processing unit 810 to perform the steps according to various exemplary embodiments of the present invention described in the above section "exemplary method" of the present specification. For example, the processing unit 810 may perform step S210 shown in fig. 2, transmitting a plurality of write command signals to a memory; step S220, acquiring a data strobe signal and a corresponding clock signal which are generated after the memory receives each write command signal; step S230, obtaining a data gating superposition signal and a clock superposition signal under a plurality of write command signals according to the data gating signal and the clock signal corresponding to the data gating signal generated after each write command signal; step S240, determining a phase difference starting point according to the allowable range of the phase difference between the data strobe signal and the clock signal and the phase difference end point; step S250, determining a phase difference maximum value and a phase difference minimum value according to a phase difference end point and a phase difference starting point based on the clock superposition signal and the data gating superposition signal; and step S260, comparing the maximum phase difference value and the minimum phase difference value with the allowable phase difference range respectively, and judging whether the memory meets the requirement of data writing reliability.

The storage unit 820 may include readable media in the form of volatile memory units such as a random access memory unit (RAM) 8201 and/or a cache memory unit 8202, and may further include a read only memory unit (ROM) 8203.

Storage unit 820 may also include a program/utility 8204 having a set (at least one) of program modules 8208, such program modules 8208 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination thereof may comprise an implementation of a network environment.

Bus 830 may be any of several types of bus structures including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

The electronic device 800 may also communicate with one or more external devices 870 (e.g., keyboard, pointing device, bluetooth device, etc.), with one or more devices that enable a user to interact with the electronic device 800, and/or with any devices (e.g., router, modem, etc.) that enable the electronic device 800 to communicate with one or more other computing devices. Such communication can occur via an input/output (I/O) interface 880. Also, the electronic device 800 may communicate with one or more networks (e.g., a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network such as the internet) via the network adapter 860. As shown, the network adapter 860 communicates with the other modules of the electronic device 800 via the bus 830. It should be appreciated that although not shown, other hardware and/or software modules may be used in conjunction with the electronic device 800, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, to name a few.

Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein may be implemented by software, or by software in combination with necessary hardware. Therefore, the technical solution according to the embodiments of the present disclosure may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (which may be a CD-ROM, a usb disk, a removable hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which may be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the embodiments of the present disclosure.

In an exemplary embodiment of the present disclosure, there is also provided a computer-readable storage medium having stored thereon a program product capable of implementing the above-described method of the present specification. In some possible embodiments, aspects of the invention may also be implemented in the form of a program product comprising program code means for causing a terminal device to carry out the steps according to various exemplary embodiments of the invention described in the above section "exemplary methods" of the present description, when said program product is run on the terminal device.

The program product for implementing the above method according to the embodiment of the present invention may employ a portable compact disc read only memory (CD-ROM) and include program codes, and may be run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited in this respect, and in this document, a readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

A computer readable signal medium may include a propagated data signal with readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A readable signal medium may also be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., through the internet using an internet service provider).

Furthermore, the above-described figures are merely schematic illustrations of processes involved in methods according to exemplary embodiments of the invention, and are not intended to be limiting. It will be readily appreciated that the processes illustrated in the above figures are not intended to indicate or limit the temporal order of the processes. In addition, it is also readily understood that these processes may be performed synchronously or asynchronously, e.g., in multiple modules.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is to be limited only by the following claims.

Claims

1. A method for testing reliability of a memory, the method comprising:

sending a plurality of write command signals to a memory;

acquiring a data strobe signal and a clock signal corresponding to the data strobe signal, which are generated after each write command signal is received by the memory;

acquiring data gating superposed signals and clock superposed signals under a plurality of write command signals according to the data gating signals generated after each write command signal and the corresponding clock signals;

determining a phase difference starting point according to the allowable range of the phase difference between the data strobe signal and the clock signal and the phase difference end point;

determining a phase difference maximum value and a phase difference minimum value according to the phase difference end point and the phase difference starting point based on the clock superposition signal and the data gating superposition signal;

and comparing the maximum phase difference value and the minimum phase difference value with the allowable phase difference range respectively, and judging whether the memory meets the requirement of data writing reliability.

2. The method of claim 1, wherein determining a phase difference starting point according to the allowable range of the phase difference between the data strobe signal and the clock signal and the phase difference ending point comprises:

setting an initial rising edge of the clock superposition signal where the phase difference starting point is located;

determining a phase difference average value of the middle position of the initial rising edge from the phase difference end point;

judging whether the average phase difference value is within the allowable range of the phase difference;

if so, determining the initial rising edge as a target rising edge where the phase difference starting point is located;

if not, the initial rising edge is moved forwards or backwards, and the corresponding phase difference average value from the phase difference end point is determined until the target rising edge is determined.

3. The method of claim 2, wherein said determining an average value of the phase difference of the intermediate position of the initial rising edge from the phase difference end point comprises:

and determining the difference value between the average value of the data strobe signals at the middle position of the rising edge where the phase difference end point is located and the average value of the clock signals at the middle position of the initial rising edge as the average value of the phase difference.

4. The method of claim 1, wherein determining a phase difference maximum and a phase difference minimum from the phase difference end point and the phase difference start point based on the clock superposition signal and the data strobe superposition signal comprises:

determining a first maximum value and a first minimum value of the middle position of the rising edge where the phase difference end point is located based on the data gating superposition signal;

determining a second maximum value and a second minimum value of the middle position of the rising edge where the phase difference starting point is located based on the clock superposition signal;

determining a difference value between the first maximum value and the second minimum value as the phase difference maximum value;

and determining the difference value of the first minimum value and the second maximum value as the phase difference minimum value.

5. The method according to claim 1 or 4, wherein the comparing the maximum phase difference value and the minimum phase difference value with the allowable phase difference range respectively to determine whether the memory meets the data writing reliability requirement comprises:

if the maximum phase difference value and the minimum phase difference value are both within the phase difference allowable range, determining that the memory meets the requirement of data writing reliability;

and if the maximum value or the minimum value of the phase difference is not within the allowable range of the phase difference, determining that the memory does not meet the requirement of data writing reliability.

6. The method of claim 1, further comprising:

the number of the write command signals transmitted to the memory is greater than a preset number.

7. The method of claim 1, wherein obtaining a data strobe overlap signal and a clock overlap signal under a plurality of write command signals according to a data strobe signal generated after each write command signal and a corresponding clock signal comprises:

superposing the data gating signals under the plurality of write command signals to obtain the data gating superposed signals;

and superposing the clock signals under the plurality of write command signals to obtain the clock superposed signal.

8. A memory reliability testing apparatus, the apparatus comprising:

a command sending module for sending a plurality of write command signals to the memory;

the signal acquisition module is used for acquiring a data strobe signal generated after the memory receives each write command signal and a clock signal corresponding to the data strobe signal;

the signal superposition module is used for acquiring data gating superposition signals and clock superposition signals under a plurality of write command signals according to the data gating signals generated after each write command signal and the corresponding clock signals;

the starting point determining module is used for determining a phase difference starting point on the clock superposition signal according to the phase difference allowable range and the phase difference end point of the data strobe signal and the clock signal;

the mode determining module is used for determining the maximum value and the minimum value of the phase difference according to the phase difference end point and the phase difference starting point on the basis of the clock superposition signal and the data gating superposition signal;

and the judging module is used for comparing the maximum phase difference value and the minimum phase difference value with the allowable phase difference range respectively and judging whether the memory meets the requirement of data writing reliability.

9. The apparatus of claim 8, wherein the starting point determining module is configured to set an initial rising edge of the clock superposition signal where the phase difference starting point is located; determining a phase difference average value of the middle position of the initial rising edge from the phase difference end point; judging whether the average phase difference value is within the allowable phase difference range or not; if so, determining the initial rising edge as a target rising edge where the phase difference starting point is located; if not, the initial rising edge is moved forwards or backwards, and the corresponding phase difference average value from the phase difference end point is determined until the target rising edge is determined.

10. The apparatus of claim 9, wherein the starting point determining module is configured to determine a difference between an average value of the data strobe signal at the middle position of the rising edge where the phase difference ending point is located and an average value of the clock signal at the middle position of the initial rising edge as the average value of the phase difference.

11. The apparatus of claim 8, wherein the most significant determination module is configured to determine a first maximum value and a first minimum value of a middle position of a rising edge where the phase difference end point is located based on the data strobe overlapping signal; determining a second maximum value and a second minimum value of the middle position of the rising edge where the phase difference starting point is located based on the clock superposition signal; determining a difference value between the first maximum value and the second minimum value as the phase difference maximum value; and determining the difference value of the first minimum value and the second maximum value as the phase difference minimum value.

12. The apparatus according to claim 8 or 11, wherein the determining module is configured to determine that the memory meets a data write reliability requirement if the maximum phase difference value and the minimum phase difference value are both within the allowable phase difference range; and if the maximum value or the minimum value of the phase difference is not within the allowable range of the phase difference, determining that the memory does not meet the requirement of data writing reliability.

13. The apparatus of claim 8, further comprising:

14. The apparatus of claim 8, wherein the signal superimposing module is configured to superimpose the data strobe signals under a plurality of write command signals to obtain the data strobe superimposed signal; and superposing the clock signals under the plurality of write command signals to obtain the clock superposed signal.

15. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the method for testing the reliability of a memory according to any one of claims 1 to 7.

16. An electronic device, comprising:

a processor; and

a memory for storing executable instructions of the processor;

wherein the processor is configured to perform the memory reliability testing method of any of claims 1-7 via execution of the executable instructions.