CN115632856A

CN115632856A - Verification system and verification method

Info

Publication number: CN115632856A
Application number: CN202211288430.9A
Authority: CN
Inventors: 赵立敏; 王煜华; 李林岳; 杨笑冰; 李春信; 冯子豪
Original assignee: Xi'an Aixin Yuanzhi Technology Co ltd
Current assignee: Xi'an Aixin Yuanzhi Technology Co ltd
Priority date: 2022-10-20
Filing date: 2022-10-20
Publication date: 2023-01-20
Anticipated expiration: 2042-10-20
Also published as: CN115632856B

Abstract

The application provides a verification system and a verification method, the verification system comprises a control layer, a data transceiving layer and a result comparison layer, the data transceiving layer comprises an auxiliary test component and a storage unit component, after an interface of the auxiliary test component is connected with the test component, the control layer writes original data into the storage unit component, the test component reads the original data of the storage unit component through the auxiliary test component, and the test component writes first result data obtained by calculation according to the original data into the storage unit component through the auxiliary test component. The result comparison layer is used for implanting a reference module, such as an ESL model, and the reference model can obtain second result data according to the calculation of the original data, so that consistency comparison is carried out according to the first result data and the second result data, and a verification result is output after the comparison is finished. The verification system can be accessed to a test component to be verified and implanted into a corresponding reference model, so that comprehensive multiplexing of a verification structure in a specific scene is completed.

Description

Verification system and verification method

Technical Field

The present application relates to the field of verification technologies, and in particular, to a verification system and a verification method.

Background

A verification platform established based on a System Verilog language + UVM verification methodology becomes a mainstream technology in the field of digital chip verification at present. The System Verilog language is compatible with the advantages of hardware language description of Verilog on one hand, and also absorbs object-oriented and generic programming concepts in the C + + software idea, so that the System Verilog can be used as hardware design and software engineering at the same time. Compared with C + +, the System Verilog greatly enhances the random constraint level, and improves the randomization capability required by chip verification. The verification structure members which can be used repeatedly and standardized are defined in the UVM standard library, the verification environments built by different engineers are unified in style to a certain extent in a manner of standardizing the verification structure members, the development efficiency of the verification environments is improved, and the difficulty in building the verification environments is reduced.

The UVM is a universal verification methodology, verification environments built by different engineers can be changed in a great variety, and the UVM does not provide a verification structure aiming at a specific scene. The verification structure under a specific scene is usually basically fixed, so that a unified verification structure based on the specific scene can be provided, and the verification structure under the specific scene can be comprehensively reused.

However, the existing verification environment has low expansibility, so that the verification environment is difficult to adapt to the requirement change at the later stage of project development, and the verification environment needs to be reconstructed.

Disclosure of Invention

An object of the embodiments of the present application is to provide a verification system and a verification method, so as to solve the problem that the expansibility of the existing verification environment is low, which results in that the verification environment is difficult to adapt to the requirement change in the later stage of project development, and the verification environment needs to be reconstructed.

The verification system provided by the embodiment of the application comprises a control layer, a data transceiving layer and a result comparison layer;

the data transceiving layer comprises at least one auxiliary test component and at least one storage unit component; the auxiliary test component is used for being connected with the test component through an interface, and the test component is configured to be connected with at least one design module to be verified;

the control layer is used for writing original data into the storage unit assembly;

the test component is used for reading original data from the storage unit component through the auxiliary test component; calculating the original data to obtain first result data, and writing the first result data into the storage unit component through the auxiliary test component;

the result comparison layer is used for acquiring original data in the storage unit assembly, calculating the original data by using a reference model module of the result comparison layer and obtaining second result data; the reference model module is used for implanting a reference model corresponding to the test component;

the result comparison layer is also used for comparing the first result data with the second result data and outputting a verification result after the comparison is finished.

In the technical scheme, the verification system comprises a control layer, a data transceiving layer and a result comparison layer, the data transceiving layer comprises an auxiliary test component and a storage unit component, after an interface of the auxiliary test component is connected with the test component, the control layer writes original data into the storage unit component, the test component reads the original data of the storage unit component through the auxiliary test component, and the test component writes first result data obtained by calculation according to the original data into the storage unit component through the auxiliary test component. The result comparison layer is used for implanting a reference module, such as an ESL model, and the reference model can obtain second result data according to the calculation of the original data, so that consistency comparison is carried out according to the first result data and the second result data, and a verification result is output after the comparison is finished. This verification system can insert the test component that needs to verify, and implant the reference model that corresponds, thereby accomplish under the specific scene verification structure comprehensive multiplexing, this verification system is succinct, it is fixed, the template is built to reliable verification environment, high expansibility has, horizontal multiplexing and perpendicular multiplexing between the similar project of being convenient for, and, the verification structure on three abstraction layers, the control layer has been realized, data send and receive the layer, the further decoupling zero between the layer is compared to the result, make verification environment clearer, maintainability has been promoted.

Each component of the data transceiving layer is responsible for realizing the functions of data reading, calculation and data writing. And the design module (RTL) reads original data from the storage unit assembly through the auxiliary test assembly, and writes the first result data into the storage unit assembly through the auxiliary test assembly after the calculation is finished, so that the reading, calculation and writing of data at one time are realized.

In some optional embodiments, the control layer comprises: the device comprises a main control assembly and a register model module;

the main control assembly is used for:

the control register model module configures a register of the design module;

writing the original data into the memory cell assembly;

and controlling a reference model module to calculate the original data.

In the technical scheme, a control layer mainly plays a role in scheduling and controls the sequential execution sequence of integral simulation, firstly, a main control component writes original data into a storage unit component, then, the configuration of a register is carried out, the read, calculation and write functions of a design module (RTL) are started through the configuration register, after the design module finishes data operation and writes data, the main control component sends a memory copy instruction, the data is copied into a C + + memory from a System Verilog memory for a reference model (such as an ESL model), and after the reference model finishes calculation and output, the main control component starts to compare results of partial models.

In some alternative embodiments, the resulting dyad layer comprises: a storage unit component copying module, a bisection model module and a reference model module;

the main control component is also used for controlling the storage unit component copying module and the bisection model module to start working;

the storage unit component copying module is used for copying the original data from the storage unit component in the first language to the storage unit component in the second language so as to provide the original data for the reference model module; copying the first result data from the memory cell component of the first language to the memory cell component of the second language for use by the split model module;

and the bisection model module is used for comparing the first result data with the second result data and outputting a verification result after the comparison is finished.

In the above technical solution, the result comparison layer is configured to perform result comparison on the first result data output by the test component and the second result data output by the reference model module.

In some optional embodiments, the memory cell component copy module comprises at least one of a DPI interface, a PLI interface, and a VPI interface.

In the above technical solution, the DPI (Direct Programming Interface) Interface is an Interface for mutual call between the System Verilog and other Programming languages, especially C/C + +. Through the DPI interface, the C function can be conveniently called in the System Verilog program, and the System Verilog function can also be called in the C program. In addition, the Interface between Verilog and C Language includes PLI (Verilog Programming Language Interface) Interface and VPI (Verilog program Interface) Interface.

In some alternative embodiments, the test assembly includes n design modules, n being a positive integer greater than 1; the first design module and the nth design module comprise at least one universal standard interface or custom interface used for being connected with the auxiliary test assembly, and the n design modules are connected through an internal interface.

Among the above-mentioned technical scheme, the test assembly includes n design modules, and the outmost design module of test assembly is first design module and nth design module promptly, and this outmost design module is used for being connected with supplementary test assembly, designs the interface between outmost design module and the supplementary test assembly for including a general standard interface or self-defined interface at least to guarantee the expansibility of verification system.

In some alternative embodiments, the test assembly includes a single design module; the single design module includes at least one of a generic standard interface or a custom interface for interfacing with the auxiliary test assembly.

In the above technical solution, the test component is a single design module, the single design module is used for being connected with the auxiliary test component, and the interface between the single design module and the auxiliary test component is designed to at least include a universal standard interface or a custom interface, so as to ensure the expansibility of the verification system.

In some optional embodiments, the control layer further comprises:

and the simulation starting component is used for starting the main control component.

An authentication method provided by an embodiment of the present application includes:

building a verification system as any one of the above;

taking a chip design module as a test component, and accessing the chip design module into a verification system through an interface;

implanting a reference model into a reference model module of the verification system;

the simulation is performed using a verification system that includes a chip design module and a reference model.

In the technical scheme, the built verification system is a verification structure of a three-abstraction-layer high-expansion implantable reference model, the verification structure provides a fixed verification environment structure in a scene that an ESL model needs to be implanted in a UVM environment, a test component is accessed into the verification structure and a reference model is implanted into the verification structure, so that comprehensive multiplexing of the verification structure in a specific scene is completed, and horizontal multiplexing and vertical multiplexing among similar projects can be realized through the method.

In some optional embodiments, the verification method further comprises setting the number of the storage unit assemblies and the auxiliary test assemblies when building the verification system.

In the technical scheme, the built verification system supports one or more storage single components to store the original data, the first result data and the second result data.

In some alternative embodiments, the simulation is performed by a verification system including a chip design module and a reference model, and includes:

sending a verification system containing a chip design module and a reference model to a hardware accelerator;

and operating the hardware accelerator, and generating a chip simulation report at the end of operation.

An embodiment of the application provides an electronic device, including: a processor and a memory, the memory storing machine-readable instructions executable by the processor, the machine-readable instructions, when executed by the processor, performing a method as in any above.

A computer-readable storage medium is provided in an embodiment of the present application, and has a computer program stored thereon, where the computer program is executed by a processor to perform the method described in any one of the above.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

Fig. 1 is a schematic diagram of a functional module of a verification system according to an embodiment of the present disclosure;

fig. 2 is a functional block diagram of an authentication system according to another embodiment of the present application;

FIG. 3 is a flowchart illustrating steps of a verification method according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure.

Icon: 1-control layer, 2-data transceiving layer, 21-memory unit component, 22-auxiliary test component, 23-test component, 3-result comparison layer, 41-processor, 42-memory, 43-communication interface, 44-communication bus.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

Referring to fig. 1, fig. 1 is a schematic diagram of a functional module of a verification system according to an embodiment of the present disclosure, including a control layer 1, a data transceiving layer 2, and a result comparing layer 3.

Wherein, the data transceiver layer 2 comprises at least one auxiliary test component 22 and at least one memory cell component 21; the auxiliary testing component 22 is configured to be connected to the testing component 23 through an interface, and the testing component 23 is configured to be connected to at least one design module to be verified. The control layer 1 is used to write original data to the memory cell unit 21. The test component 23 is used for reading the original data from the storage unit component 21 through the auxiliary test component 22; the raw data is calculated to obtain first result data, and the first result data is written into the memory cell unit 21 through the auxiliary test unit 22. The result ratio layer 3 is used for acquiring original data in the storage unit component 21, and the reference model module of the result ratio layer 3 is used for calculating the original data and obtaining second result data; wherein the reference model module is used to implant a reference model corresponding to the test component 23. The result comparison layer 3 is also used for comparing the first result data with the second result data, and outputting a verification result after the comparison is finished.

In the embodiment of the application, the verification system includes a control layer 1, a data transceiving layer 2 and a result comparison layer 3, the data transceiving layer 2 includes an auxiliary test component 22 and a storage unit component 21, after an interface of the auxiliary test component 22 is connected to the test component 23, the control layer 1 writes original data into the storage unit component 21, the test component 23 reads the original data of the storage unit component 21 through the auxiliary test component 22, and the test component 23 writes first result data obtained by calculation according to the original data into the storage unit component 21 through the auxiliary test component 22. The result comparison layer 3 is used for implanting a reference module, such as an ESL model, which can calculate second result data according to the original data, so as to perform consistency comparison according to the first result data and the second result data, and output a verification result after the comparison is completed. This verification system can insert the test component 23 that needs to verify to implant corresponding reference model, thereby accomplish the comprehensive multiplexing of verification structure under the specific scene, this verification system is that a succinct, fixed, reliable verification environment builds the template, has high expansibility, horizontal multiplexing and perpendicular multiplexing between the similar project of being convenient for, and, the verification structure on three abstract layers, control layer 1 has been realized, data send and receive layer 2, the result is than the further decoupling zero between layer 3, make the verification environment clearer, maintainability has been promoted.

Each component of the data transceiving layer 2 is responsible for realizing the functions of data reading, calculation and data writing. The design module (RTL) reads the original data from the memory cell module 21 through the auxiliary test module 22, and writes the first result data into the memory cell module 21 through the auxiliary test module 22 after the calculation is completed, thereby implementing the reading, calculation, and writing of data at one time.

Referring to fig. 2, fig. 2 is a schematic functional block diagram of a verification system according to another embodiment of the present disclosure. In this embodiment, the control layer 1 includes: a main control assembly and a register model module.

Correspondingly, the main control assembly is used for: the control register model module configures a register of the design module; writing the original data into the memory cell component 21; and controlling a reference model module to calculate the original data.

In the embodiment of the application, the control layer 1 mainly plays a role in scheduling and controls the sequential execution sequence of the overall simulation, the main control component writes original data into the storage unit component 21, then performs configuration of a register, starts the read, calculation and write functions of a design module (RTL) by configuring the register, after the design module completes data operation and writes data, the main control component sends a memory copy instruction, copies the data from a System Verilog memory into a C + + memory for a reference model (such as an ESL model), and after the reference model completes calculation and output, the main control component starts to compare results of the partial models.

In some alternative embodiments, the resulting layer 3 comprises: the memory cell assembly includes a copy module, a bisection model module, and a reference model module. The main control component is also used for controlling the storage unit component copying module and the bisection model module to start working. The storage unit component copying module is used for copying original data from the storage unit component 21 in the first language to the storage unit component 21 in the second language so as to provide the original data for the reference model module; the first result data is copied from the first language memory location component 21 into the second language memory location component 21 for use by the split model module. The bisection model module is used for comparing the first result data with the second result data, outputting a verification result after the comparison is completed, and if the first result data is consistent with the second result data, the verification is passed, and if the first result data is inconsistent with the second result data, the verification is not passed.

In the embodiment of the present application, the result comparison layer 3 function is to perform result comparison between the first result data output by the test component 23 and the second result data output by the reference model module. For example, the reference model is an ESL model, and the ESL model is generally realized by adopting a C + + language, so that the result is uniformly constructed by adopting C + + compared with the components of the layer 3, and the interaction of System Verilog and C + + uses a storage unit component copy module; and the storage unit component copying module copies the original data from the System Verilog memory to the C + + memory for ESL model calculation, the ESL model completes calculation and writes a result, and the first result data of the split model and the second result data output by the ESL model are compared.

In the embodiment of the present application, the DPI (Direct Programming Interface) Interface is an Interface for mutual call between the System Verilog and other Programming languages, and is particularly C/C + +. Through the DPI interface, the C function can be conveniently called in the System Verilog program, and the System Verilog function can also be called in the C program. In addition, the Interface between Verilog and C Language includes PLI (Verilog Programming Language Interface) Interface and VPI (Verilog program Interface) Interface.

In some alternative embodiments, test component 23 includes n design modules, n being a positive integer greater than 1; the first design module and the nth design module include at least one universal standard interface or custom interface for connecting with the auxiliary test assembly 22, and the n design modules are connected through an internal interface.

In the embodiment of the present application, the testing component 23 includes n design modules, the outermost design module of the testing component 23 is the first design module and the nth design module, the outermost design module is used for being connected with the auxiliary testing component 22, and the interface between the outermost design module and the auxiliary testing component 22 is designed to include at least one universal standard interface or custom interface, so as to ensure the expansibility of the verification system.

It should be understood that in some embodiments, the test component 23 may also be a single design module; the single design module includes at least one of a generic standard interface or a custom interface for interfacing with the auxiliary test assembly 22.

In the embodiment of the present application, the testing component 23 is a single design module, the single design module is used for being connected with the auxiliary testing component 22, and the interface between the single design module and the auxiliary testing component 22 is designed to at least include a universal standard interface or a custom interface, so as to ensure the expansibility of the verification system.

In some optional embodiments, the control layer 1 further comprises: and the simulation starting component is used for starting the main control component.

In this embodiment, the work flow of the verification system shown in fig. 2 is specifically as follows:

first, the emulation initiation component controls the initiation of the main control component. The main control assembly plays a role in scheduling each module and controls the sequential execution sequence of the overall simulation.

The master control element writes the raw data into one or more memories Mem (i.e., memory cell elements 21).

The main control module performs configuration of a register of a design module (RTL) in the test module 23 through the register model module, and starts read, calculate, and write functions of the design module (RTL) through the configuration register. The test assembly 23 of this embodiment includes three design modules connected by internal interfaces.

The configured testing component 23 reads the raw data in the one or more memories Mem through the auxiliary testing component 22. And calculating to obtain first result data according to the original data and by utilizing the calculation function of the design module to be verified. The test element 23 then writes the first result data to one or more memories Mem via the auxiliary test element 22.

In this embodiment, the reference model module adopts an ESL model, and the main control component controls the storage unit component copy module to copy the original data from the System Verilog memory to the C + + memory for use in calculation of the ESL model, and copy the first result data from the System Verilog memory to the C + + memory for use in the bisection model module. In this embodiment, DPI is used for System Verilog and C + + interaction.

The main control assembly controls the ESL model calculation of the reference model module, namely, according to the original data in the C + + memory, the ESL model is used for calculating to obtain second result data.

And (4) uniformly constructing the components of the layer 3 by adopting C + + as a result comparison, and comparing and analyzing the first result data and the second result data to obtain a verification result.

Therefore, the verification system of the embodiment is a verification structure of a high-expansion implantable ESL based on three abstract layers, provides a fixed verification environment structure under the scene that the ESL needs to be implanted in the UVM environment, and provides a simple, fixed and reliable verification environment building template for the special scene. In addition, the embodiment specifically layers the verification structure, and provides a verification structure with three abstraction layers, so that further decoupling between the control layer 1, the data transceiving layer 2 and the result layer 3 is realized, the verification environment is clearer, and the maintainability is improved. The verification structure has strong expandability in a specific scene and is convenient for horizontal multiplexing and vertical multiplexing among similar projects.

Furthermore, the verification system of the embodiment supports that the outermost design module adopts 1 or more universal standard interfaces or custom interfaces, supports that a single or a plurality of same or different design modules are embedded for verification, and supports that one or a plurality of memories are used for storing data.

Referring to fig. 3, fig. 3 is a flowchart illustrating steps of a verification method according to an embodiment of the present disclosure, including:

step 100, building a verification system as any one of the above;

step 200, taking a chip design module as a test component 23, and accessing the chip design module into a verification system through an interface;

step 300, implanting a reference model into a reference model module of a verification system;

step 400, simulation is carried out by utilizing a verification system comprising a chip design module and a reference model.

In the embodiment of the application, the built verification system is a verification structure of a three-abstraction-layer high-expansion implantable reference model, the verification structure provides a fixed verification environment structure in a scene that an ESL model needs to be implanted in a UVM environment, the verification structure is accessed to the test component 23 and the reference model is implanted, so that comprehensive multiplexing of the verification structure in a specific scene is completed, and horizontal multiplexing and vertical multiplexing among similar projects can be realized through the method.

In some optional embodiments, the verification method further includes setting the number of the storage unit assemblies 21 and the auxiliary test assemblies 22 when the verification system is built. In the embodiment of the application, the built verification system supports one or more storage single components to store the original data, the first result data and the second result data.

In some alternative embodiments, the simulation is performed by a verification system including a chip design module and a reference model, and includes: sending a verification system comprising a chip design module and a reference model to a hardware accelerator; and operating the hardware accelerator, and generating a chip simulation report at the end of operation.

Fig. 4 shows a possible structure of an electronic device provided in an embodiment of the present application. Referring to fig. 4, the electronic device includes: a processor 41, a memory 42, and a communication interface 43, which are interconnected and in communication with each other via a communication bus 44 and/or other form of connection mechanism (not shown).

The Memory 42 includes one or more (Only one is shown in the figure), which may be, but not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), an electrically Erasable Programmable Read-Only Memory (EEPROM), and the like. Processor 41, and possibly other components, may access, read, and/or write data to memory 42.

The processor 41 includes one or more (only one shown) which may be an integrated circuit chip having signal processing capabilities. The Processor 41 may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Micro Control Unit (MCU), a Network Processor (NP), or other conventional processors; the Processor may also be a dedicated Processor, including a Neural-Network Processing Unit (NPU), a Graphics Processing Unit (GPU), a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, a discrete Gate or transistor logic device, and a discrete hardware component. Also, when the processor 41 is plural, a part thereof may be a general-purpose processor, and another part thereof may be a dedicated processor.

The communication interface 43 includes one or more (only one shown) that can be used to communicate directly or indirectly with other devices for data interaction. The communication interface 43 may include an interface that performs wired and/or wireless communication.

One or more computer program instructions may be stored in the memory 42, and the processor 41 may read and execute the computer program instructions to implement the authentication method provided by the embodiment of the present application.

It will be appreciated that the configuration shown in fig. 4 is merely illustrative and that the electronic device may include more or fewer components than shown in fig. 4 or have a different configuration than shown in fig. 4. The components shown in fig. 4 may be implemented in hardware, software, or a combination thereof. The electronic device may be a physical device, such as a PC, a laptop, a tablet, a cell phone, a server, an embedded device, etc., or may be a virtual device, such as a virtual machine, a virtualized container, etc. The electronic device is not limited to a single device, and may be a combination of a plurality of devices or a cluster including a large number of devices.

The embodiment of the present application further provides a computer-readable storage medium, where computer program instructions are stored on the computer-readable storage medium, and when the computer program instructions are read and executed by a processor of a computer, the verification method provided by the embodiment of the present application is executed. The computer readable storage medium may be embodied as, for example, the memory 42 in the electronic device of fig. 4.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A verification system is characterized by comprising a control layer, a data transceiving layer and a result comparison layer;

the test component is used for reading the original data from the storage unit component through the auxiliary test component; calculating the original data to obtain first result data, and writing the first result data into the storage unit component through the auxiliary test component;

the result comparison layer is used for acquiring the original data in the storage unit assembly, calculating the original data by using a reference model module of the result comparison layer and obtaining second result data; wherein the reference model module is used for implanting a reference model corresponding to the test component;

2. The system of claim 1, wherein the control layer comprises: the device comprises a main control assembly and a register model module;

the main control assembly is used for:

controlling the register model module to configure the register of the design module;

writing the original data to the memory cell component;

and controlling the reference model module to calculate the original data.

3. The system of claim 2, wherein the result vs. layer comprises: a memory cell component copying module, a bisection model module and the reference model module;

the storage unit component copying module is used for copying the original data from the storage unit component in the first language to the storage unit component in the second language so as to provide the original data for the reference model module; copying the first result data from the memory cell component of the first language to the memory cell component of the second language for use by the bisection model module;

4. The system of claim 1, wherein the memory cell component copy module comprises at least one of a DPI interface, a PLI interface, and a VPI interface.

5. The system of claim 1, wherein the test component includes n design modules, n being a positive integer greater than 1; the first design module and the nth design module comprise at least one universal standard interface or custom interface used for being connected with the auxiliary test assembly, and the n design modules are connected through an internal interface.

6. The system of claim 1, wherein the test component comprises a single design module; the single design module includes at least one of a universal standard interface or a custom interface for interfacing with the auxiliary test assembly.

7. The system of claim 2, wherein the control layer further comprises:

8. An authentication method implemented on the basis of an authentication system according to any one of claims 1 to 7, the method comprising:

taking a chip design module as a test component of the verification system, and accessing the chip design module into the verification system through an interface;

and carrying out simulation by using a verification system comprising the chip design module and a reference model.

9. The method of validating as defined in claim 8, further comprising, in building the validation system, setting a number of storage cell assemblies and auxiliary test assemblies.

10. The verification method of claim 9, wherein the simulating with the verification system including the chip design module and the reference model comprises:

sending a verification system comprising a chip design module and a reference model to a hardware accelerator;

and operating the hardware accelerator, and generating a chip simulation report when the operation is finished.