CN115630595A

CN115630595A - Automatic logic circuit generation method and device, electronic device and storage medium

Info

Publication number: CN115630595A
Application number: CN202211312906.8A
Authority: CN
Inventors: 赵可
Original assignee: Spreadtrum Communications Tianjin Co Ltd
Current assignee: Spreadtrum Communications Tianjin Co Ltd
Priority date: 2022-10-25
Filing date: 2022-10-25
Publication date: 2023-01-20

Abstract

The method comprises the steps of obtaining a plurality of groups of input values and output values corresponding to each group of input values; acquiring an initial logical relationship between the output values and the input values according to the multiple groups of input values and the output values corresponding to each group of input values; the method comprises the steps of carrying out combined simplification processing on initial logical relations between output values and input values, determining the same items in the initial logical relations between the output values and the input values, using preset identification information to identify the same items, and using the identification information to update the initial logical relations to obtain target logical relations between the output values and the input values; and generating a logic circuit according to the target logic relation between the output value and the input value. The method automatically generates the logic circuit, particularly for a complex logic circuit, a logic circuit which can carry out mathematical calculation on a fixed input value is designed without adopting an iterative approximation algorithm by a user, so that the design time of the logic circuit is shortened, and the efficiency is improved.

Description

Automatic logic circuit generation method and device, electronic device and storage medium

Technical Field

The present application relates to the field of integrated circuit technologies, and in particular, to an automatic generation method and apparatus for a logic circuit, an electronic device, and a storage medium.

Background

With the rapid development of computers, the demand for high-speed execution of certain functions in hardware is increasing. For example, integrated circuits used to perform computer image processing and digital signal processing may often need to compute the value of a logarithmic or gamma function or other mathematical function for a given input value. In some techniques, when a more complex mathematical calculation is performed in a circuit, the more complex mathematical calculation is not directly operated, but is implemented by using some iterative approximation algorithm. For example, when performing trigonometric function calculations, a Cordic algorithm is typically used to obtain a calculated value by iteratively and continuously approximating the true result.

The above method requires that the developer is familiar with an iterative approximation algorithm, such as Cordic algorithm, and the developer designs a logic circuit capable of performing mathematical calculation on a fixed input value by using the iterative approximation algorithm. Especially, the logic circuit of complex mathematical computation is time-consuming and has high requirements on the capability of a developer, thereby causing low efficiency and long period of project development.

Disclosure of Invention

In view of this, the present application provides an automatic generation method and apparatus for a logic circuit, an electronic device, and a storage medium, so as to solve the problems in the prior art that the design of a logic circuit for implementing mathematical computation is time-consuming and inefficient.

In a first aspect, an embodiment of the present application provides an automatic generation method for a logic circuit, including:

acquiring a plurality of groups of input values and output values corresponding to each group of input values;

acquiring an initial logic relationship between the output values and the input values according to the multiple groups of input values and the output values corresponding to each group of input values;

combining and simplifying the initial logical relationship between the output value and the input value, determining the same item in the initial logical relationship between the output value and the input value, identifying the same item by using preset identification information, and updating the initial logical relationship by using the identification information to obtain a target logical relationship between the output value and the input value;

and generating a logic circuit according to the target logic relationship between the output value and the input value.

Preferably, the obtaining an initial logical relationship between the input values and the output values according to the plurality of sets of input values and the output values corresponding to each set of input values includes:

acquiring the preset digit number of the preset data format of each input value in any group of input values and the preset digit number of the preset data format of the output value;

according to the preset digit number of the preset data format of each input value in any group of input values and the preset digit number of the preset data format of the output value, carrying out conversion processing of the preset data format on each group of input values and the output values corresponding to each group of input values to obtain truth table information between the input values and the output values; the input value of the preset data format comprises a plurality of data bits of a corresponding preset bit; the output value of the preset data format comprises a plurality of data bits of a corresponding preset bit;

acquiring an initial logic relationship between an output value and an input value according to the truth table information; the initial logic relationship between the data bits of the different bit output values and the data bits in the input value is not completely the same.

Preferably, the combining and simplifying the initial logical relationship between the output value and the input value, determining a same item in the initial logical relationship between the output value and the input value, identifying the same item by using preset identification information, and updating the initial logical relationship by using the identification information to obtain a target logical relationship between the output value and the input value includes:

acquiring a preset simplification algorithm, and logically simplifying the logical relationship between each bit of the output value and each data bit in the input value according to the preset simplification algorithm to obtain the simplified logical relationship between each bit of the output value and each data bit in the input value;

and carrying out combined simplification processing on simplified logic relations between each data bit of the output value and each data bit of the input value, determining the same item in the simplified logic relations between the output value and the input value, identifying the same item by using preset identification information, and updating the logic relations by using the identification information to obtain a target logic relation between the output value and the input value.

Preferably, the combining and simplifying the simplified logical relationship between each bit of the output value and each bit of the input value to determine the same item in the simplified logical relationship between the output value and the input value, identifying the same item by using preset identification information, and updating the logical relationship by using the identification information to obtain the target logical relationship between the output value and the input value includes:

obtaining a comparison logic item according to a preset digit of a preset data format of each input value in any group of input values;

detecting whether the same item exists in the simplified logic relation between different data bits of the output value and each data bit in the input value according to the comparison logic item; and if so, identifying the same item by using preset identification information, and updating the simplified logical relationship by using the identification information to obtain a target logical relationship between the output value and the input value.

Preferably, the obtaining a comparison logic item according to a preset number of bits of a preset data format of each input value in any group of input values includes:

determining m logic input groups according to preset digits of preset data formats of all input values in any group of input values; each logic input group comprises two logic input values with opposite values; m is an integer greater than 1;

setting n as a preset initial value; the preset initial value is an integer which is greater than 1 and not greater than m;

forming a comparison logic item according to n logic input values from different logic input groups in the logic input values contained in the m logic input groups to obtain

A comparison logic term;

detecting whether n is equal to m;

if not, updating n to n +1, and re-executing the step to form a comparison logic item according to the n logic input values from different logic input groups in the logic input values contained in the m logic input groups to obtain

Comparing the logic items, and detecting whether n is equal to m until n is equal to m.

Preferably, said detecting whether there is the same item in the simplified logical relationship between different data bits of said output value and each data bit in at least one set of input values according to said comparison logical item; if yes, identifying the same item by using identification information, and updating the simplified logical relationship by using the identification information to obtain a target logical relationship between an output value and an input value, wherein the target logical relationship comprises:

determining the obtained comparison logic items as unmarked comparison logic items;

determining a target comparison logic item in the unmarked comparison logic items; the target logic item is the comparison logic item with the largest number of logic input values contained in the unmarked comparison logic items;

updating a marked comparison logic item according to a target comparison logic item, and updating the unmarked comparison logic item;

searching whether at least two items are the same as the mark comparison logic item in the simplified logic relationship between different data bits of the output value and each data bit in the input value according to the mark comparison logic item;

if so, utilizing the identification information mark and at least two items which are the same as the mark comparison logic item, and utilizing the identification information mark to update the simplified logic relation;

detecting the presence of an untagged comparison logic item;

if yes, re-executing the step to determine the target comparison logic item in the comparison logic items without marks, and detecting whether the comparison logic items without marks exist or not until the comparison logic items without marks do not exist.

Preferably, the preset simplified algorithm includes: queen-Macrasky Q-M reduction.

Preferably, the generating a logic circuit according to the target logic relationship between the output value and the input value includes:

and generating a register transmission level RTL code according to the target logic relation between the output value and the input value.

In a second aspect, an embodiment of the present application provides an apparatus for automatically generating a logic circuit, including:

the acquisition unit is used for acquiring a plurality of groups of input values and output values corresponding to each group of input values;

the acquiring unit is further configured to acquire an initial logical relationship between the output values and the input values according to the plurality of groups of input values and the output values corresponding to each group of input values;

the processing unit is used for carrying out combination simplification processing on the initial logical relationship between the output value and the input value, determining the same item in the initial logical relationship between the output value and the input value, identifying the same item by using preset identification information, and updating the initial logical relationship by using the identification information to obtain a target logical relationship between the output value and the input value;

and the processing unit is also used for generating a logic circuit according to the target logic relationship between the output value and the input value.

In a third aspect, an embodiment of the present application provides an electronic device, including a memory for storing computer program instructions and a processor for executing the program instructions, wherein when the computer program instructions are executed by the processor, the electronic device is triggered to execute the method of any one of the above first aspects.

In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, where the computer-readable storage medium includes a stored program, and when the program runs, a device on which the computer-readable storage medium is located is controlled to execute the method described in any one of the foregoing first aspects.

By adopting the scheme provided by the embodiment of the application, a plurality of groups of input values and output values corresponding to each group of input values are obtained; acquiring an initial logical relationship between the output values and the input values according to the multiple groups of input values and the output values corresponding to each group of input values; the method comprises the steps of carrying out combination simplification processing on initial logical relations between output values and input values, determining the same items in the initial logical relations between the output values and the input values, using preset identification information to identify the same items, and using the identification information to update the initial logical relations to obtain target logical relations between the output values and the input values; and generating a logic circuit corresponding to the target mathematical function according to the target logic relation between the input and output values and the input value. That is, in the embodiment of the present application, when the operation of the mathematical function is implemented, the input value of the mathematical function may be acquired and the output value thereof may be calculated. According to the input value and the output value, obtaining an initial logical relationship between the output value and the input value, carrying out combination simplification processing on the initial logical relationship between the output value and the input value, determining the same item in the initial logical relationship, adopting preset identification information to identify the same item, and updating the initial logical relationship according to the preset identification information to obtain a target logical relationship between the output value and the input value. And generating a logic circuit according to the target logic relation between the output value and the input value. That is to say, in the embodiment of the present application, the logic circuit can be automatically generated directly according to the input value and the output value of the data calculation, and a user does not need to design a logic circuit capable of mathematically calculating a fixed input value by using an iterative approximation algorithm, so that the design time of the logic circuit, especially a complex mathematical logic circuit, is reduced, and the efficiency is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive labor.

Fig. 1 is a schematic flowchart of an automatic logic circuit generation method according to an embodiment of the present disclosure;

fig. 2 is a schematic flowchart of an automatic generation method of a logic circuit according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of an automatic generation apparatus for a logic circuit according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

For better understanding of the technical solutions of the present application, the following detailed descriptions of the embodiments of the present application are provided with reference to the accompanying drawings.

It should be understood that the embodiments described are only a few embodiments of the present application, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.

The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is merely one type of associative relationship that describes an associated object, meaning that three types of relationships may exist, e.g., A and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

Before specifically describing the embodiments of the present application, terms applied or likely to be applied to the embodiments of the present application will be explained first.

RTL (Register Transfer Level), an abstract description of the actual circuit.

Q-M method: the Quen-Macraski simplification method is a logic expression simplification method, overcomes the limitation of Carnot diagram simplification, and is suitable for computer-aided simplification.

In the related art, when a more complex mathematical calculation is performed in a circuit, the calculation is not direct operation, but is implemented by using some iterative approximation algorithms. For example, when performing trigonometric function calculations, a Cordic algorithm is usually used to obtain a calculated value by iteratively approximating the true result.

The above approach requires the developer to be familiar with the algorithm of iterative approximation, such as Cordic algorithm, and to design a logic circuit capable of performing mathematical calculation on a fixed input value by using the algorithm of iterative approximation by the developer. The logic circuit which is mathematical calculation needs manual design by users, the time consumption is long, the workload of developers is increased, and the efficiency is low.

In view of the above problems, embodiments of the present application provide an automatic generation method and apparatus for a logic circuit, an electronic device, and a storage medium, where multiple groups of input values and output values corresponding to each group of input values are obtained; acquiring an initial logical relationship between the output values and the input values according to the multiple groups of input values and the output values corresponding to each group of input values; the method comprises the steps of combining and simplifying initial logical relations between output values and input values, determining the same items in the initial logical relations between the output values and the input values, identifying the same items by using preset identification information, and updating the initial logical relations by using the identification information to obtain target logical relations between the output values and the input values; and generating a logic circuit corresponding to the target mathematical function according to the target logic relationship between the input and output values and the input value. That is, in the embodiment of the present application, when the operation of the mathematical function is implemented, the input value of the mathematical function may be acquired and the output value thereof may be calculated. According to the input value and the output value, obtaining an initial logical relationship between the output value and the input value, carrying out combination simplification processing on the initial logical relationship between the output value and the input value, determining the same item in the initial logical relationship, adopting preset identification information to identify the same item, and updating the initial logical relationship according to the preset identification information to obtain a target logical relationship between the output value and the input value. And generating a logic circuit according to the target logic relation between the output value and the input value. That is to say, in the embodiment of the present application, the logic circuit can be automatically generated directly according to the input value and the output value of the data calculation, and a user does not need to design a logic circuit capable of mathematically calculating a fixed input value by using an iterative approximation algorithm, so that the design time of the logic circuit, especially a complex mathematical logic circuit, is reduced, and the efficiency is improved. The details will be described below.

Referring to fig. 1, a schematic flow chart of an automatic generation method of a logic circuit provided in an embodiment of the present application is shown. As shown in fig. 1, the method includes:

and S101, acquiring a plurality of groups of input values and output values corresponding to each group of input values.

And calculating the output value of each group by using a preset mathematical function. Each set of input values comprises at least one input value.

In the embodiment of the present application, in order to implement automatic generation of a logic circuit of a mathematical function, all possible input values may be preset for the mathematical function, and a plurality of sets of input values may be obtained by using all possible preset input values as one set of input values. Therefore, multiple preset groups of input values can be obtained, and each group of input values is calculated by utilizing a preset data function to obtain an output value corresponding to each group of input values.

It should be understood that when performing mathematical calculations, it is common to perform the calculations on a given input value. That is, input values and mathematical functions are generally set when performing mathematical calculations. Thus, the output value can be calculated according to the set input value and the mathematical function. Of course, when setting the input value, a specific numerical value may be directly set. That is, each group includes several input values and the specific numerical value of each input value, and the total number of groups of input values is set. The value range and the value rule of each input value can be set. The value-taking rules are used to identify how to obtain the input value within a value-taking range. For example, each set of input values includes two input values, a and b. The specific values of the input values a and b contained in different groups are different. Assuming that the value rule identifies that a and b are both integers, and the value ranges of a and b are both [0,9], the integers in the value ranges can be used as input values according to the value rule. Therefore, each group of input values can be determined according to the value range and the value rule of each input value, and 100 values can be obtained.

As a possible implementation, all possible output values need to be exhausted for more accurate generation of the logic circuit. Thus, when acquiring multiple sets of input values, all possible input values that need to be mathematically calculated are acquired. Thus, all possible output values can be exhausted, in case the mathematical function is known. That is, all sets of input values calculated by the preset mathematical function and output values corresponding to each set of input values are obtained.

As shown in the above example, in the case of 100 input values, 100 values may be obtained, and the calculation of the preset mathematical function may be performed for each set of input values, and the obtained 100 values may be calculated. Assuming a predetermined mathematical function of

The calculated output values are shown in table 1 below.

TABLE 1

Step S102, obtaining an initial logic relation between the output values and the input values according to the plurality of groups of input values and the output values corresponding to each group of input values.

The initial logic relationship between the data bits of the different bit output values and the data bits in the input value is not completely the same.

In this embodiment, after obtaining the multiple sets of input values and the output values corresponding to each set of input values, the numerical relationships between each set of input values and the output values corresponding to each set of input values may be converted into the logical relationships between the output values and the input values, that is, the initial logical relationships between the output values and the input values are obtained.

As a possible implementation manner, obtaining an initial logical relationship between an input value and an output value according to a plurality of groups of input values and output values corresponding to each group of input values includes:

acquiring preset digits of preset data formats of input values and output values in any group of input values, and performing conversion processing of the preset data formats on each group of input values and the output values corresponding to each group of input values according to the preset digits of the preset data formats of the input values and the preset digits of the preset data formats of the output values in any group of input values to obtain truth table information between the input values and the output values; and acquiring an initial logic relationship between the output value and the input value according to the truth table information.

The input value of the preset data format comprises a plurality of data bits of a corresponding preset bit; the output value of the predetermined data format includes a plurality of data bits corresponding to the predetermined bits. And, the value of each data bit in the input value and the output value is 0 or 1.

In order to obtain the initial logical relationship between the output value and the input value more quickly and accurately, the input value and the output value may be converted into a preset data format, and the initial logical relationship may be determined according to the relationship between the input value and the output value of the preset data format. For example, the predetermined data format is a binary data format, such that an initial logical relationship between the output value and the input value is obtained according to the input value and the numerical relationship between the output values after being converted into the binary data. At this time, the preset number of bits in the preset data format of each input value and the preset number of bits in the preset data format of each output value may be obtained. I.e. each input value and output value is represented by a number of binary digits. After the preset digit of the preset data format of each input value and the preset digit of the preset data format of the output value are obtained, each input value in each group of input values can be converted into data of the preset data format with the preset digit according to the preset digit of the preset data format of each input value. And converting each output value into data with a preset data format with preset digits so as to obtain truth table information between the input value and the output value. For example, when the preset data format is a binary format, after the preset digits of the binary data format of each input value and the preset digits of the binary data format of the output value are obtained, each input value in each group may be converted into a binary number with preset digits according to the preset digits of the binary data format corresponding to each input value. Similarly, the output value is converted into a binary number with preset digits according to the preset digits of the binary data format corresponding to the output value. And forming truth table information through each input value and corresponding output value in each group of input values in the binary data format to obtain truth table information between the input values and the output values. And converting the numerical relation between the input value and the output value into a logical relation according to truth table information between the input value and the output value to obtain an initial logical relation between the output value and the input value. That is, the logical relationship between each data bit of the output value and each data bit of at least one group of input values may be determined according to the truth table information between the input values and the output values, and the logical relationship may be used as the initial logical relationship between the output values and the input values to obtain the initial logical relationships of the preset number of bits of the output values.

The initial logical relationship between the output value and the input value means that each bit of data of the output value is represented by a data bit in the input value.

It should be understood that after the input value and the output value are respectively converted into data in the preset data format according to the corresponding preset number of bits, the initial logical relationship may be obtained according to the data relationship between each bit of the output value and each bit of the input value, and the initial logical relationship of the preset number of bits of the output value may be obtained.

That is, after the input value and the output value are converted into the data of the preset data format, the input value of the preset data format includes a plurality of data bits of the preset bits. The output value of the preset data format comprises a plurality of data bits of preset bits. For example, when the predetermined data format is a binary data format, after each input value is converted into data in the binary data format, each input value includes a plurality of data bits corresponding to the predetermined bit. After the output value is converted into data in a binary data format, the output value comprises a plurality of data bits corresponding to the preset bits. For example, the predetermined number of bits of the output value is c, and after the output value is converted into binary number, the output value contains c data bits, which are x 0, x 1, 8230, and x c-1. The value of each data bit is either 0 or 1. For example, if the output value x is 4 and the preset number of bits is 4, the value obtained by converting the output value x into the binary data format is: 0100; at this time, the output value includes 4 data bits, the first data bit x [0] has a value of 0, the second data bit x [1] has a value of 0, the third data bit x [2] has a value of 1, and the fourth data bit x [3] has a value of 0. At this time, it is necessary to obtain an initial logical relationship between each bit of the output value and the input value according to a numerical relationship between each bit of the output value and each bit of the input value, and c initial logical relationships can be obtained.

The preset number of bits of the input value and the output value is the number of bits of the preset data format of each input value and each output value according to the actual requirement on the design precision of the logic circuit. That is, the input value and the output value are represented by numbers in a several-bit predetermined data format. The preset digits between at least two input values in the same group can be the same or different, and can be set according to actual requirements. As in the above example, each set of input values includes an input value a and an input value b, where the predetermined number of bits of the input value a and the predetermined number of bits of the input value b may be the same or different. Since the number of input values included in the group is not changed since the number of input values in each group is changed, the number of input values included in different groups is the same. That is, two input values, i.e., the input value a and the input value b, are included in different sets of input values, and the value of the input value a and/or the value of the input value b in different sets are different. Therefore, the preset number of bits of the input value a is the same between different groups, and similarly, the preset number of bits of the input value b is the same between different groups.

It should be noted that the preset data format may be a binary data format, or may be other data formats capable of representing a logical relationship between an input value and an output value, which is not limited in this application.

For example, assume that the predetermined number of bits for each of the input and output values is 8 bits. As shown in the above example, after table 1 is obtained, the input values and the output values in table 1 may be converted into a binary data format to obtain truth table information between the input values and the output values, as shown in table 2 below. That is, according to table 1 above, the values of each a, b, x in table 1 are each converted to an 8-bit binary number representation (for convenience of illustration, x only holds integer bits, and decimal places are directly truncated), as shown in table 2 below.

TABLE 2

After the truth table information between the input value and the output value is obtained, the numerical relationship between the input value and the output value in the truth table can be converted into the logical relationship, and the target logical relationship between the output value and the input value is obtained. For example, the conversion of the relationship between the input value and the output value in table 2 above into a logical relationship can be represented by the following logical function expression. Since the expression is too lengthy, F is used below ₁ () In summary, the following is presented: x = F ₁ (a[7]，a[6],…,a[1],a[0],b[7]，b[6],…,b[1],b[0])。

Further, obtaining the initial logical relationship according to the truth table information may be performed in the following manner. Since the truth table information in table 2 is large, the following embodiment will be described with the simplified truth table information in table 3.

TABLE 3

With the truth table information shown in table 3, an initial logical relationship between each data bit of the output value and each data bit of at least one set of input values can be obtained. That is, it can be known that two bits of the data bits of the output value are x [1] and x [0] respectively through the truth table information shown in Table 3. When the data bit x [1] of the output value takes 1, it is related to the first set of input values a and b, the fourth set of input values a and b, the sixth set of input values a and b, and the seventh set of input values a and b. At this time, each of the four sets of input values a and b can be respectively used as one of the logical relationships between x [1] and the input value, and then x [1] can be represented by each data bit in the four sets of input values a and b:

x [1] = a [1] '& a [0]' & b [0] '+ a [1] & a [0] & b [0] + a [1] & a [0] & b [0]'; wherein a 1 ' represents the negation of a 1, a 0 ' represents the negation of a 0, and b 0 ' represents the negation of b 0.

Similarly, the expression of data bit x [0] that can be used to obtain the output value is:

x[0]＝a[1]&a[0]’&b[0]+a[1]&a[0]&b[0]’+a[1]&a[0]&b[0]。

for convenience of representation, X = F may be used ₁ (a[1],a[0],b[0]) To express both expressions uniformly.

When obtaining X = F ₁ (a[1],a[0],b[0]) Then, the obtained logical relationship between the output value and the input value may be directly determined as the initial logical relationship between the output value and the input value.

Step S103, carrying out combination simplification processing on the initial logical relationship between the output value and the input value, determining the same item in the initial logical relationship between the output value and the input value, identifying the same item by using preset identification information, and updating the initial logical relationship by using the identification information to obtain a target logical relationship between the output value and the input value.

In the embodiment of the present application, in the obtained initial logical relationship between the output value and the input value, each data bit of the output value is represented by each data bit of each input value in at least one group of input values, and at least part of data bits of different output values are represented by each data bit of each input value in different groups of input values. Therefore, the initial logical relationship of each bit of the output value is complicated, and if the logic circuit is generated based on the initial logical relationship, the generated logic circuit is complicated. That is, the complexity of the logical relationship is reduced, the initial logical relationship between each bit of data of the output value and the input value may be combined and simplified, that is, the same items in each initial logical relationship of the output value are found, the same items are identified by the preset identification information, the initial logical relationship is updated by using the preset identification information, the same items in the initial logical relationship are respectively represented by the corresponding preset identification information, and the updated initial logical relationship is used as the target logical relationship between the output value and the input value.

As a possible implementation manner, the combining and simplifying processing of the initial logical relationship between the output value and the input value, determining the same item in the initial logical relationship between the output value and the input value, identifying the same item by using preset identification information, and updating the initial logical relationship by using the identification information to obtain the target logical relationship between the output value and the input value includes: the method comprises the following steps:

and acquiring a preset simplifying algorithm, and logically simplifying the initial logical relationship between each bit of the output value and each data bit in the input value according to the preset simplifying algorithm to obtain the simplified logical relationship between each bit of the output value and each data bit in the input value. And carrying out combined simplification processing on simplified logic relations between each data bit of the output value and each data bit of the input value, determining the same item in the simplified logic relations between the output value and the input value, identifying the same item by using preset identification information, and updating the logic relations by using the identification information to obtain a target logic relation between the output value and the input value.

That is, the initial logic relationship between each data bit of the output value and each data bit of the input value may be obtained first according to the truth table information, that is, different data bits of the output value are obtained first according to the truth table information and are represented by each data bit of different input values, and the initial logic relationship is complex and needs to be simplified. At this time, a preset simplifying algorithm may be obtained, wherein the preset simplifying algorithm may simplify the logical relationship. After the preset simplification algorithm is obtained, the logical relationship between each bit of data of the output value and the input value can be simplified by using the preset simplification algorithm, so as to obtain the simplified logical relationship after simplification.

It should be understood that the preset reduction algorithm is an algorithm capable of reducing the logical relationship, which is preset according to actual requirements. As one possible implementation, the default reduction algorithm includes Q-M reduction. That is, the initial logical relationship between each bit of the output value and the input value is simplified by a Q-M simplification method, so as to obtain a simplified logical relationship after simplification. The predetermined simplification algorithm may also be other logic relation simplification algorithms, for example, carnot diagram simplification method, which is not limited in this application.

And simplifying the initial logic relationship between the obtained output value and the input value through a preset simplification algorithm to obtain a simplified logic relationship, namely the simplified logic relationship between different data bits of the output value and the input value. The simplified logical relationship between the different data bits of the output value and the input value is not exactly the same. The same terms may exist in the simplified logical relationship between different data bits of the output value and the input value, and the same terms may be implemented using one circuit when performing logic circuit generation. Therefore, in order to reduce the complexity of the logic circuit, all the same entries can be found for the simplified logical relationship between different data bits of the output value and the input value. For example, the logical relationship between each bit of the output value and the input value in table 2 is simplified to obtain a simplified logical relationship after simplification, which is specifically as follows:

x[7]＝a[1]&a[3]&b[7]&b[2]’+a[5]&a[2]’&b[0]；

x[6]＝a[4]&a[3]&b[7]+a[5]&a[2]’&b[0]+a[6]&a[3]’；

…

x [0] = a [1] & a [3] + a [5] & a [2]' & b [0]. Wherein a 1& a 3 in the logical relationship between x 7 and the input value is the same as a 1& a 3 in the logical relationship between x 0 and the input value, and a 1& a 3 in x 7 and x 0 can be realized by the same circuit when realizing the logic circuit. Based on the method, the simplified logical relationship between each data bit of the output value and each data bit of the input value can be combined and simplified, the same item in the simplified logical relationship between the output value and the input value is determined, the same item is identified by using the preset identification information, the logical relationship is updated by using the identification information, and the target logical relationship between the output value and the input value is obtained.

As a possible implementation manner, performing a combinatorial simplification process on a simplified logical relationship between each data bit of the output value and each data bit of the input value, determining a same item in the simplified logical relationship between the output value and the input value, identifying the same item by using preset identification information, and updating the logical relationship by using the identification information, so as to obtain a target logical relationship between the output value and the input value, including:

obtaining a comparison logic item according to a preset digit of a preset data format of each input value in any group of input values; detecting whether the same item exists in the simplified logic relation between different data bits of the output value and each data bit in the input value according to the comparison logic item; if the input value exists, the same item is identified by using the identification information, and the simplified logic relationship is updated by using the identification information, so that the target logic relationship between the output value and the input value is obtained.

In the embodiment of the present application, since each bit of data of the output value is represented by a bit of the input value, a comparison logic term may be obtained by performing all possible combinations on the data bits of all the input values of each group, and by comparing the comparison logic term with each item of each logic relationship, it may be found whether the same item exists in each logic relationship. Thus, the data bits of the input values can be combined in all possible combinations according to the truth table information to obtain the comparison logic entries. And detecting whether at least two items which are the same as the comparison logic item exist in the logic relationship between each bit of the output value and the input value or not for each comparison logic item, if so, determining that the same item exists in the simplified logic relationship between each bit of the output value and each data bit in the input value, identifying the same item by using preset identification information, replacing the same item in the simplified logic relationship between each bit of the output value and each data bit in the input value with the preset identification information, and updating the simplified logic relationship.

And taking the updated simplified logic relationship as a target logic relationship between the output value and the input value.

As a possible implementation manner, the comparison logic item may be determined by the following manner, that is, as shown in fig. 2, acquiring the comparison logic item according to the truth table information includes:

step S201, m logic input groups are determined according to preset digits of preset data formats of all input values in any group of input values.

Wherein each logic input group comprises two logic input values with opposite values. m is an integer greater than 1.

In this embodiment, in order to find out all the same entries in the simplified logical relationship, all possible combinations of the respective data bits of all the input values in each set of input values may be obtained. Since the number of input values contained within different sets of input values and the number of data bits contained in each input value are the same, all possible combinations of data bits for all input values in different sets of input values are the same. It is only necessary to determine all possible combinations of the individual data bits for all input values within a set of input values.

In order to obtain all possible combinations of the data bits in the input values, it is first determined how many bits of the data bits are contained in all the input values in any group of input values. At this time, the preset digit of the preset data format of each input value in any group of input values can be obtained, according to the preset digit of the preset data format of each input value, the total number of the data digits contained in all the input values in any group of input values is calculated, that is, the sum of the preset digits of the preset data format of each input value is determined as a value of m, each digit of all the data digits contained in all the input values in a group of input values is determined as a group of logic input groups, and different digits are different groups of logic input groups, so that m groups of logic input groups can be obtained. That is, m represents the sum of the number of bits of the data bits of each input value in a set of input values.

Because the value of each data bit has two conditions of 1 or 0, all possible combination forms among different data bits of all input values in a group of input values are obtained, and all possible combination forms among different values among all data bits of each input value in a group of input values are actually determined. When m groups of logic input groups are obtained, each logic input group comprises two logic input values with opposite values. That is, each logic input group includes two logic input values, where one logic input value takes a value of 1 and the other logic input value takes a value of 0.

Step S202, setting n as a preset initial value.

Wherein the preset initial value is an integer greater than 1 and not greater than m.

It should be noted that the preset initial value is preset, and the number of data bits that should be included in the comparison logic item is minimum.

As a possible implementation, the initial value is preset to 2.

Step S203, in the logic input values contained in the m logic input groups, a comparison logic item is formed according to the n logic input values from different logic input groups to obtain

And comparing the logical terms.

In the embodiment of the present application, since all possible combinations of different values between data bits of each input value in a group of input values need to be obtained, in the logic input values included in m logic input groups, the comparison logic items formed by n logic input values of all different logic input groups in the logic input values included in m logic input groups can be obtained in a manner that n logic input values from different logic input groups form one comparison logic item

A comparison logic term. Wherein the content of the first and second substances,

indicating that n data bits are selected from the m data bits and that there are 2 possibilities for each of the n data bits to take on a value.

And step S204, detecting whether n is equal to m.

The method comprises the steps of acquiring all possible combination forms of different values among data bits of each input value in a group of input values, detecting whether n is equal to m or not, if so, indicating that all possible combination forms of different values among data bits of each input value in the group of input values are acquired, and if not, indicating that all possible combination forms of different values among n data bits of each input value in the group of input values are acquired only, and if not, all possible combination forms of different values among m-n data bits are not acquired, and acquiring continuously.

It should be noted that when n and m are detected to be equal, it is indicated that all comparison logic items have been acquired, and at this time, the step of acquiring the comparison logic items may be ended. When n and m are not equal, the following step S205 is continued.

Step S205, if not equal, updating n to n +1, and re-executing the step to form a comparison logic item according to the n logic input values from different logic input groups in the logic input values included in the m logic input groups to obtain

In the embodiment of the present application, when it is detected that n is not equal to m, it indicates that all possible combinations of different values between data bits of each input value in a group of input values are not obtained, at this time, n is updated to n +1, and step S204 is executed again until n is equal to m.

Through the steps, when the preset initial value is 2, the data bits of all input values contained in a group of input values, the comparison logic items composed of all 2 data bits, the comparison logic items composed of all 3 data bits, \ 8230 \ 8230;, and the comparison logic items composed of all m data bits can be obtained. That is, by changing the value of n, all possible combinations of m data bits can be obtained. That is, by changing the value of n, all possible combinations of 2 data bits among m data bits, 3 data bits, 82308230, m data bits, can be obtained.

After all the comparison logic items are obtained, whether the same item exists in the simplified logic relation between different data bits of the output value and each data bit in the input value can be detected according to the comparison logic items; if the input value exists, the same item is identified by using the identification information, and the simplified logical relationship is updated by using the identification information, so that the target logical relationship between the output value and the input value is obtained.

As a possible implementation manner, the specific detection may be implemented by detecting whether the same item exists in the simplified logical relationship between different data bits of the output value and each data bit in at least one group of input values according to the comparison logical item; if yes, identifying the same item by using identification information, and updating the simplified logical relationship by using the identification information to obtain a target logical relationship between an output value and an input value, wherein the target logical relationship comprises:

determining the obtained comparison logic items as unmarked comparison logic items; determining a target comparison logic item in the unmarked comparison logic items; updating the marked comparison logic item according to the target comparison logic item, and updating the unmarked comparison logic item; according to the mark comparison logic item, searching whether at least two items in the simplified logic relation between different data bits of the output value and each data bit in the input value are the same as the mark comparison logic item; if so, marking at least two items which are the same as the marker comparison logic items by utilizing the identification information, and updating the simplified logic relation by utilizing the identification information; detecting the presence of an untagged comparison logic item; if yes, the step is executed again to determine the target comparison logic item in the comparison logic items which are not marked, and the step is executed to detect whether the comparison logic items which are not marked exist or not until the comparison logic items which are not marked do not exist.

The target logic item is the comparison logic item with the largest number of logic input values contained in the unmarked comparison logic item.

That is, in order to obtain the simplest logic circuit, when detecting whether the same item is included in the simplified logic relationship between different data bits of the output value and each data bit in the input value according to the comparison logic item, it is necessary to search in the order of at least more data bits included. Therefore, it is necessary to first obtain one of the comparison logic items that contains the most data bits. At this time, all comparison logic items obtained above may be determined as unmarked comparison logic items. Among the unmarked comparison logic items, the comparison logic item having the largest number of logic input values contained therein is determined as a target comparison logic item. If there are a plurality of comparison logic entries having the largest number of data bits contained therein, any one of the plurality of comparison logic entries having the largest number of data bits contained therein may be determined as the target comparison logic entry. And updating the target comparison logic item to be a marked comparison logic item, namely updating the comparison logic item with the largest number of data bits contained in the unmarked comparison logic item to be a marked comparison logic item, deleting the marked comparison logic item from the unmarked comparison logic item, and updating the unmarked comparison logic item. After updating the tag comparison logic, the tag comparison logic may be utilized to find out whether at least two entries are identical to the tag comparison logic in the simplified logic relationship between different data bits of the output value and each data bit of the input value. That is, it is found whether there are at least two entries having the same data bits contained therein as the data bits contained in the tag compare logic entry. If so, it is indicated that the same item exists in the simplified logical relationship between different data bits of the output value and each data bit in the input value, at least two items that are the same as the marked comparison logical item may be used as the same item in the simplified logical relationship, the at least two items may be marked by the identification information, and the same item in the simplified logical relationship may be replaced by the identification information, so as to update the simplified logical relationship. If not, the comparison logic item is deleted. In this way, at least two of the simplified logical relationships that are identical to the tag comparison logical term can be looked up. Detecting whether an unmarked comparison logic item still exists, if so, indicating that the comparison logic item still does not detect the same item in the simplified logic relationship, and then re-executing the steps in the unmarked comparison logic item to determine a target comparison logic item until the step detects whether the unmarked comparison logic item exists or not until the unmarked comparison logic item does not exist. At this time, all the same items in the simplified logical relationship can be determined, and are identified through the identification information, and the simplified logical relationship is updated to obtain the target logical relationship.

Illustratively, assume that different simplified logical relationships are obtained as x [7] = a [1] & a [3] & b [7] & b [2] '+ a [5] & a [2]' & b [0];

x < 6 > = a < 4 > & a < 3 > & b < 7 > + a < 5 > & a < 2 > '& b < 0 > + a < 6 > & a < 3 >'; \8230, x 0 (= a 1) & a 3 + a 5 & a 2' & b 0. If the determined labeled logic comparison item is a [1] & a [3], whether at least two items which are the same as the labeled logic item exist in different simplified logic relations or not is searched, and at the moment, it can be determined that two items in different simplified logic relations are the same as the labeled logic item, namely, the a [1] & a [3] appears twice in different simplified logic relations. At this time, the identification information temp1 may be used to identify the same item, that is, temp1= a [1] & a [3], and the identification information is used to replace the same item in the simplified logical relationship, so as to obtain the target logical relationship, where the target logical relationship is x [7] = temp1& b [7] & b [2]' + a [5] & a [2] & b [0]; x [6] = a [4] & a [3] & b [7] + a [5] & a [2]' & b [0] + a [6] & a [3 ]; \8230, x 0 (= temp1+ a 5 and a 2' & b 0); temp1= a [1] & a [3].

The target logical relationship between the output value and the input value can be obtained through the steps.

And step S104, generating a logic circuit according to the target logic relation between the output value and the input value.

In this embodiment, after the target logical relationship between the output value and the input value is obtained, the target logical relationship is the relationship of each device in the logic circuit, and at this time, the logic circuit may be directly generated according to the target logical relationship between the output value and the input value.

As a possible implementation, generating the logic circuit according to the target logical relationship between the output value and the input value includes: and generating the RTL code according to the target logic relation between the output value and the input value.

That is, the logic circuit is described by the RTL code, and thus the RTL code can be generated according to the target logical relationship. At this time, each line of the target logic relationship can be traversed directly according to the target logic relationship between the output value and the input value, and the RTL code is generated line by line to obtain the RTL file. And generating a logic circuit through the RTL file.

In the embodiment of the present application, when the operation of the mathematical function is implemented, the input value of the mathematical function may be obtained and the output value thereof may be calculated. According to the input value and the output value, obtaining an initial logical relationship between the output value and the input value, carrying out combination simplification processing on the initial logical relationship between the output value and the input value, determining the same item in the initial logical relationship, adopting preset identification information to identify the same item, and updating the initial logical relationship according to the preset identification information to obtain a target logical relationship between the output value and input. And generating a logic circuit according to the target logic relation between the output value and the input value. That is to say, in the embodiment of the present application, the logic circuit can be automatically generated directly according to the input value and the output value of the data calculation, and a user does not need to design a logic circuit capable of mathematically calculating a fixed input value by using an iterative approximation algorithm, so that the design time of the logic circuit, especially a complex mathematical logic circuit, is reduced, and the efficiency is improved.

Referring to fig. 3, an apparatus for automatically generating a logic circuit is provided in an embodiment of the present application. As shown in fig. 3, the automatic generation apparatus includes:

an obtaining unit 301 is configured to obtain multiple sets of input values and output values corresponding to the input values.

Wherein each set of input values comprises at least one input value. The output value is calculated from the input value using a predetermined mathematical function.

The obtaining unit 301 is further configured to obtain an initial logical relationship between the output value and the input value according to the multiple sets of input values and the output value corresponding to each set of input values.

The processing unit 302 is configured to perform a combination and simplification process on the initial logical relationship between the output value and the input value, determine a same item in the initial logical relationship between the output value and the input value, identify the same item by using preset identification information, and update the initial logical relationship by using the identification information, so as to obtain a target logical relationship between the output value and the input value.

As a possible implementation manner, the processing unit 302 is specifically configured to obtain a preset number of bits in a preset data format of each input value in any group of input values and a preset number of bits in a preset data format of an output value. And performing conversion processing of the preset data format on each group of input values and output values corresponding to each group of input values according to the preset digit number of the preset data format of each input value in any group of input values and the preset digit number of the preset data format of each output value to obtain truth table information between the input values and the output values. And acquiring an initial logic relationship between the output value and the input value according to the truth table information.

The input value of the preset data format comprises a plurality of data bits of a corresponding preset bit; the output value of the predetermined data format includes a plurality of data bits corresponding to the predetermined bits. The initial logical relationship between the data bits of the different bit output values and the data bits in the input values is not exactly the same.

As a possible implementation manner, the processing unit 302 is specifically configured to obtain a preset simplified algorithm, and logically simplify a logical relationship between each bit of the output value and each data bit in the input value according to the preset simplified algorithm to obtain a simplified logical relationship between each bit of the output value and each data bit in the input value; and carrying out combined simplification processing on simplified logic relations between each data bit of the output value and each data bit of the input value, determining the same item in the simplified logic relations between the output value and the input value, identifying the same item by using preset identification information, and updating the logic relations by using the identification information to obtain a target logic relation between the output value and the input value.

As a possible implementation manner, the processing unit 302 is specifically configured to obtain a comparison logic item according to a preset number of bits in a preset data format of each input value in any group of input values; detecting whether the same item exists in the simplified logic relation between different data bits of the output value and each data bit in the input value or not according to the comparison logic item; if the simplified logical relationship exists, the same item is identified by using preset identification information, and the simplified logical relationship is updated by using the identification information, so that a target logical relationship between the output value and the input value is obtained.

As a possible implementation manner, the processing unit 302 is specifically configured to determine m logical input groups according to preset digits of a preset data format of each input value in any group of input values. Setting n to presetAn initial value. Among the logic input values contained in m logic input groups, a comparison logic item is formed according to n logic input values from different logic input groups to obtain

A comparison logic term; detecting whether n is equal to m; if not, updating n to n +1, and re-executing in the logic input values contained in m logic input groups, and forming a comparison logic item according to n logic input values from different logic input groups to obtain

Each logic input group comprises two logic input values with opposite values; m is an integer greater than 1; the preset initial value is an integer greater than 1 and not greater than m.

As a possible implementation manner, the processing unit 302 is specifically configured to determine all the obtained comparison logic items as comparison logic items that are not marked; determining a target comparison logic item in the unmarked comparison logic items; updating the marked comparison logic item according to the target comparison logic item, and updating the unmarked comparison logic item; according to the mark comparison logic item, searching whether at least two items are the same as the mark comparison logic item in the simplified logic relation between different data bits of the output value and each data bit in the input value; if so, marking at least two items which are the same as the marker comparison logic items by utilizing the identification information, and updating the simplified logic relation by utilizing the identification information; detecting the presence of an unlabeled comparison logic term; if yes, re-executing the step to determine the target comparison logic item in the comparison logic items without marks, and detecting whether the comparison logic items without marks exist or not until the comparison logic items without marks do not exist.

The target logic item is the comparison logic item with the largest number of logic input values contained in the unmarked comparison logic items.

As a possible implementation, the preset simplified algorithm includes: queen-Macrasky Q-M reduction.

The processing unit 302 is further configured to generate a logic circuit according to a target logic relationship between the output value and the input value.

As a possible implementation, the processing unit 302 is specifically configured to generate the register transfer level RTL code according to a target logical relationship between the output value and the input value.

Corresponding to the embodiment, the application further provides the electronic equipment. Fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present invention, where the electronic device 400 may include: a processor 401, a memory 402, and a communication unit 403. The components communicate over one or more buses, and those skilled in the art will appreciate that the configuration of the servers shown in the figures are not meant to limit embodiments of the present invention, and may be in the form of buses, stars, more or fewer components than those shown, some components in combination, or a different arrangement of components.

The communication unit 403 is configured to establish a communication channel, so that the storage device can communicate with other devices. Receiving the user data sent by other devices or sending the user data to other devices.

The processor 401, which is a control center of the storage device, connects various parts of the entire electronic device using various interfaces and lines, and performs various functions of the electronic device and/or processes data by operating or executing software programs and/or modules stored in the memory 402 and calling data stored in the memory. The processor may be composed of Integrated Circuits (ICs), for example, a single packaged IC, or a plurality of packaged ICs connected to the same or different functions. For example, processor 401 may include only a Central Processing Unit (CPU). In the embodiment of the present invention, the CPU may be a single operation core, or may include multiple operation cores.

The memory 402 may be implemented by any type of volatile or non-volatile storage device or combination of volatile and non-volatile storage devices, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disk.

The execution instructions in memory 402, when executed by processor 401, enable electronic device 400 to perform some or all of the steps in the embodiment shown in fig. 1.

In specific implementation, the present invention further provides a computer storage medium, where the computer storage medium may store a program, and the program may include some or all of the steps in each embodiment of the automatic generation method of a logic circuit provided in the present invention when executed. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a Random Access Memory (RAM), or the like.

Those skilled in the art will readily appreciate that the techniques of the embodiments of the present invention may be implemented as software plus a required general purpose hardware platform. Based on such understanding, the technical solutions in the embodiments of the present invention may be substantially or partially embodied in the form of a software product, which may be stored in a storage medium, such as a ROM/RAM, a magnetic disk, an optical disk, or the like, and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute the method according to the embodiments or some parts of the embodiments.

The same and similar parts among the various embodiments in this specification may be referred to each other. Especially, as for the device embodiment and the terminal embodiment, since they are basically similar to the method embodiment, the description is relatively simple, and the relevant points can be referred to the description in the method embodiment.

Claims

1. A method for automatically generating a logic circuit, comprising:

2. The method of claim 1, wherein obtaining the initial logical relationship between the input values and the output values according to the plurality of sets of input values and the output values corresponding to each set of input values comprises:

acquiring an initial logic relationship between an output value and an input value according to the truth table information; wherein, the initial logic relationship between the data bits of the different bit output values and the data bits of the input values is not completely the same.

3. The method of claim 2, wherein the combining and simplifying the initial logical relationship between the output value and the input value to determine the same item in the initial logical relationship between the output value and the input value, identifying the same item by using preset identification information, and updating the initial logical relationship by using the identification information to obtain the target logical relationship between the output value and the input value comprises:

acquiring a preset simplification algorithm, and logically simplifying the logical relationship between each data bit of the output value and each data bit of the input value according to the preset simplification algorithm to obtain the simplified logical relationship between each data bit of the output value and each data bit of the input value;

4. The method of claim 3, wherein the performing a combinatorial reduction process on the reduced logical relationship between each bit of the output value and each bit of the input value to determine a same item in the reduced logical relationship between the output value and the input value, identifying the same item by using preset identification information, and updating the logical relationship by using the identification information to obtain the target logical relationship between the output value and the input value comprises:

acquiring a comparison logic item according to a preset digit of a preset data format of each input value in any group of input values;

5. The method according to claim 4, wherein the obtaining a comparison logic item according to a preset number of bits in a preset data format of each input value in any one of the sets of input values comprises:

determining m logic input groups according to the preset digit of the preset data format of each input value in any group of input values; each logic input group comprises two logic input values with opposite values; m is an integer greater than 1;

among the logic input values contained in m logic input groups, a comparison logic item is formed according to n logic input values from different logic input groups to obtain

A comparison logic term;

detecting whether n is equal to m;

if not, updating n to n +1, and re-executing the step to form a comparison logic item according to n logic input values from different logic input groups in the logic input values contained in the m logic input groups to obtain a comparison logic item

6. The method of claim 4, wherein detecting whether the same entry exists in the reduced logical relationship between different data bits of the output value and each data bit of at least one set of input values according to the comparison logic entry; if yes, identifying the same item by using identification information, and updating the simplified logical relationship by using the identification information to obtain a target logical relationship between an output value and an input value, wherein the target logical relationship comprises:

if yes, at least two items which are the same as the marker comparison logic item are marked by the identification information, and the simplified logic relation is updated by the identification information;

detecting the presence of an unlabeled comparison logic term;

if yes, the step is executed again to determine the target comparison logic item in the comparison logic items which are not marked, and the step is executed to detect whether the comparison logic items which are not marked exist or not until the comparison logic items which are not marked do not exist.

7. The method of claim 3, wherein the predetermined reduction algorithm comprises: queen-Macrasky Q-M reduction.

8. The method of any of claims 1-7, wherein generating a logic circuit based on the target logical relationship between the output value and the input value comprises:

9. An apparatus for automatically generating a logic circuit, comprising:

and the processing unit is also used for generating a logic circuit according to the target logic relation between the output value and the input value.

10. An electronic device comprising a memory for storing computer program instructions and a processor for executing the program instructions, wherein the computer program instructions, when executed by the processor, trigger the electronic device to perform the method of any of claims 1-8.

11. A computer-readable storage medium, comprising a stored program, wherein the program, when executed, controls an apparatus in which the computer-readable storage medium resides to perform the method of any one of claims 1-8.