CN115629815A

CN115629815A - FPGA prototype verification platform capable of verifying EMMC user interface

Info

Publication number: CN115629815A
Application number: CN202211152557.8A
Authority: CN
Inventors: 郑纯皓; 卢笙; 谢水源
Original assignee: Xinqiyuan Shanghai Semiconductor Technology Co ltd
Current assignee: Xinqiyuan Shanghai Semiconductor Technology Co ltd
Priority date: 2022-09-21
Filing date: 2022-09-21
Publication date: 2023-01-20

Abstract

According to the FPGA prototype verification platform capable of verifying the EMMC user interface, the testcase module is introduced to output user test instruction data which corresponds to the same test operation executed on the EMMC chip by the user design interface connected with the external EMMC chip, so that whether a hardware link of the user design interface connected to the external EMMC chip through the FPGA prototype verification platform is correct or not is determined by judging whether the test operation is successfully completed on the external EMMC chip or not, and the problem positioning process is simplified.

Description

FPGA prototype verification platform capable of verifying EMMC user interface

Technical Field

The invention relates to the field of prototype verification platforms based on an FPGA (field programmable gate array), in particular to an FPGA prototype verification platform capable of verifying an EMMC (embedded multimedia card) user interface.

Background

With the continuous improvement of chip integration and diversification of performance development, chip design becomes more and more complex, hundreds of billions of transistors need to be integrated on a very small chip, so that fine and huge engineering can be solved in a covered way instead of a single manpower range, and therefore, a prototype verification platform based on the FPGA becomes an optimal choice for a developer to check design.

For ASIC users, the final chip products often adopt a structure in which an EMMC chip is externally attached to access boot code. Therefore, when the prototype verification platform based on the FPGA is used by the users, the external EMMC chip is also required to be connected through the interface of the prototype verification platform. However, in the process that an ASIC user downloads a code to an FPGA-based prototype verification platform for prototype verification, for the user, there may be problems with the user code itself, the conversion process from the user code to the FPGA code, and the connection of the prototype verification platform to the user code and the EMMC chip. The user pays attention to the possible problems of the user code, the conversion process from the user code to the FPFGA code needs to be ensured by the user and a testing platform together, and the connection between the user code and the EMMC chip by a prototype verification platform needs to be ensured by the prototype verification platform.

Further, when a user accesses an external EMMC chip using an FPGA-based prototype verification platform, if a problem arises, it is generally considered from three aspects. The first is whether the user code itself has a problem, which is also the part that the user wants to verify using the prototype verification platform; secondly, whether the ASIC codes of the users are correct when the ASIC codes are transplanted to a prototype verification platform based on the FPGA; and thirdly, whether the interface connected with the external EMMC chip in the user design is correct in the process of connecting the interface connected with the external EMMC chip through the interface of the prototype verification platform.

When the use problem of the EMMC chip originally occurs, whether the conversion of the prototype verification platform to the user EMMC interface is correct or not and whether a hardware link is normal or not need to be eliminated, and a large amount of time is wasted, so that a method is needed for realizing the decoupling of the user side and the prototype verification platform side when the user uses the FPGA-based prototype verification platform to connect the external EMMC chip for analysis when the problem occurs.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide an FPGA prototype verification platform capable of verifying an EMMC user interface, which is used to solve the above technical problems occurring in the prior art.

To achieve the above and other related objects, the present invention provides a platform comprising: the testcase module is used for outputting user test instruction data which corresponds to a user design interface connected with an external EMMC chip and executes the same test operation on the EMMC chip; and the user interface conversion module is connected with the testcase module and used for sending the user test instruction data to an external EMMC chip connected with the user interface conversion module so as to execute corresponding test operation on the external EMMC chip, so that whether a hardware link in the user design interface connected to the external EMMC chip through the FPGA prototype verification platform is correct or not is determined by judging whether the test operation is successfully completed on the external EMMC chip or not.

In an embodiment of the present invention, the testcase module includes: and the parameterization module is used for generating user operation instruction data which accords with the time sequence of the external EMMC chip and corresponds to the same test operation executed on the EMMC chip by a user design interface connected with the external EMMC chip according to the parameters input through the platform visual interface of the FPGA prototype verification platform.

In an embodiment of the present invention, the testcase module includes: and the data import module is used for importing the user operation instruction data through a platform visual interface of the FPGA prototype verification platform.

In an embodiment of the present invention, whether the test operation on the external EMMC chip is completed is determined through a platform visualization interface of the FPGA prototype verification platform.

In an embodiment of the present invention, the manner of determining whether the test operation on the external EMMC chip is completed includes: comparing operation result data fed back on the platform visual interface by the test operation corresponding to the external EMMC chip executed based on the user operation instruction with operation result data corresponding to the test operation executed by the external EMMC chip executed by the user design interface; if the test result is consistent with the test result, the test operation on the external EMMC chip is judged to be successfully completed; otherwise, the completion is not successful.

In an embodiment of the present invention, the testcase module stores a test operation step file for performing a test operation on the EMMC chip, and the test operation step file includes: user test instruction data corresponding to one or more test operations executed on the EMMC chip and operation result data corresponding to each test operation executed on the EMMC chip by the user design interface are respectively obtained.

In an embodiment of the invention, the user test instruction data includes: initialization operation instruction data corresponding to initialization operation and/or read-write operation instruction data corresponding to read-write operation.

In an embodiment of the present invention, it may be further determined whether the time sequences are consistent by comparing the entry waveform of the ui conversion module captured through the platform gui with the entry waveform of the ui conversion module designed by the user.

In an embodiment of the present invention, the testcase version adopted by the testcase module is associated with a socket position of the EMMC chip on the FPGA prototype verification platform.

In an embodiment of the present invention, the data importing module is further configured to import, through the internal RAM of the platform visual interface, the user operation instruction data and operation result data corresponding to the test operation corresponding to the user operation instruction data executed by the corresponding user design interface on the EMMC chip.

As described above, the FPGA prototype verification platform capable of verifying the EMMC user interface according to the present invention has the following advantages: according to the invention, the testcase module is introduced to output the user test instruction data which corresponds to the same test operation executed by the user design interface connected with the external EMMC chip on the EMMC chip, so that whether the hardware link of the user design interface connected to the external EMMC chip through the FPGA prototype verification platform is correct or not is determined by judging whether the test operation is successfully completed on the external EMMC chip or not, and the problem positioning process is simplified.

Drawings

Fig. 1 is a schematic structural diagram of an FPGA prototype verification platform capable of verifying an EMMC user interface according to an embodiment of the present invention.

Fig. 2 is a schematic structural diagram of an FPGA prototype verification platform according to an embodiment of the present invention.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.

It is noted that in the following description, reference is made to the accompanying drawings which illustrate several embodiments of the present invention. It is to be understood that other embodiments may be utilized and that mechanical, structural, electrical, and operational changes may be made without departing from the spirit and scope of the present invention. The following detailed description is not to be taken in a limiting sense, and the scope of embodiments of the present invention is defined only by the claims of the issued patent. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Spatially relative terms, such as "upper," "lower," "left," "right," "lower," "below," "lower," "over," "upper," and the like, may be used herein to facilitate describing one element or feature's relationship to another element or feature as illustrated in the figures.

Throughout the specification, when a part is referred to as being "connected" to another part, this includes not only a case of being "directly connected" but also a case of being "indirectly connected" with another element interposed therebetween. In addition, when a certain portion is said to "include" a certain constituent element, unless otherwise specified, it means that other constituent elements may be further included without excluding other constituent elements.

The terms first, second, third, etc. are used herein to describe various elements, components, regions, layers and/or sections, but are not limited thereto. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the scope of the present invention.

Also, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," and/or "comprising," when used in this specification, specify the presence of stated features, operations, elements, components, items, species, and/or groups, but do not preclude the presence, or addition of one or more other features, operations, elements, components, items, species, and/or groups thereof. The terms "or" and/or "as used herein are to be construed as inclusive or meaning any one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of the following: a; b; c; a and B; a and C; b and C; A. b and C ". An exception to this definition will occur only when a combination of elements, functions or operations are inherently mutually exclusive in some way.

The embodiment of the invention provides an FPGA prototype verification platform capable of verifying an EMMC user interface, wherein a testcase module is introduced to output user test instruction data which corresponds to a user design interface connected with an external EMMC chip and executes the same test operation on the EMMC chip, so that whether a hardware link of the user design interface connected to the external EMMC chip through the FPGA prototype verification platform is correct or not is determined by judging whether the test operation is successfully completed on the external EMMC chip or not, and the problem positioning process is simplified.

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings so that those skilled in the art can easily implement the embodiments of the present invention. The present invention may be embodied in many different forms and is not limited to the embodiments described herein.

The platform includes:

the testcase module 11 is configured to output user test instruction data corresponding to one or more test operations that are performed on the EMMC chip 2 by a user design interface connected to the external EMMC chip 2; specifically, the testcase module 11 replaces the user code under the ordinary condition, so that whether the hardware link from the user code to the external EMMC chip is reliable under the same condition can be verified, and whether the user function can be realized under the same operation can be compared.

And the user interface conversion module 12 is connected with the testcase module 11 and used for sending the user test instruction data to the external EMMC chip 2 connected with the user interface conversion module so as to execute one or more corresponding test operations on the external EMMC chip, so that whether the hardware link in the process that the user design interface is connected to the external EMMC chip through the interface of the FPGA prototype verification platform is correct or not is determined by judging whether the test operation is successfully completed on the external EMMC chip 2 or not.

In one embodiment, the testcase module 11 includes: and the parameterization module is used for generating user operation instruction data which is in accordance with the external EMMC chip time sequence and corresponds to the same test operation executed on the EMMC chip 2 by the user design interface connected with the external EMMC chip 2 according to the parameters input through the platform visual interface of the FPGA prototype verification platform. The user may enter these parameters to control the output of the testcase module, for example, through a GUI interface of the prototype verification platform.

In one embodiment, the testcase module 11 includes: and the data import module is used for importing the user operation instruction data through a platform visual interface of the FPGA prototype verification platform. Preferably, the data importing module is further configured to import, through the built-in RAM of the platform visual interface, the user operation instruction data and operation result data corresponding to the test operation corresponding to the user operation instruction data executed by the EMMC chip 2 corresponding to the user design interface.

In an embodiment, whether the test operation on the external EMMC chip is completed is determined through a platform visualization interface of the FPGA prototype verification platform. The manner of determining whether the test operation on the external EMMC chip is completed includes: comparing operation result data fed back on the platform visual interface by the test operation corresponding to the external EMMC chip executed based on the user operation instruction with operation result data corresponding to the test operation executed by the external EMMC chip executed by the user design interface; if the test result is consistent with the test result, the test operation on the external EMMC chip is judged to be successfully completed; otherwise, the completion is not successful.

In one embodiment, the user test instruction data includes: initialization operation instruction data corresponding to initialization operation and/or read-write operation instruction data corresponding to read-write operation. It should be noted that the read/write operation instruction data includes: read operation instruction data corresponding to read operation and write operation instruction data corresponding to write operation; and the read-write operation can be only read or write, or the two operations can be combined.

And each operation may correspond to one or more operation steps, and each operation step may correspond to one or more instructions.

In an embodiment, the testcase module 11 stores a test operation step file for executing a test operation on the EMMC chip 2, and the test operation step file includes: user test instruction data corresponding to one or more test operations to be executed on the EMMC chip 2 and operation result data corresponding to each test operation to be executed on the EMMC chip 2 corresponding to the user design interface are respectively obtained. When the EMMC chip is used, the corresponding user design interface corresponding to the EMMC chip can be called from a platform visual interface to compare operation result data corresponding to the test operation executed by the EMMC chip with the operation result data to be fed back.

In one embodiment, the user may also eliminate timing issues by comparing the egress data of the testcase module with the user-designed egress data for the same operation. That is, the user interface conversion module may be configured to determine whether the time sequence is consistent by comparing the entry waveform captured via the platform visual interface to the entry waveform captured via the user design interface. Specifically, the testcase module can capture the entry waveform of the user interface conversion module through a GUI interface of the prototype verification platform, and provide the entry waveform of the user in the user interface conversion module compared with the design of the user.

In one embodiment, the testcase version adopted by the testcase module is associated with the socket position of the EMMC chip on the FPGA prototype verification platform. For example, a testcase version in the corresponding hardware environment is generated according to the use flow of the prototype verification platform.

To better illustrate the FPGA prototype verification platform that can verify the EMMC user interface described above, the present invention provides the following specific embodiments.

Example 1: an EMMC user interface verification method utilizing an FPGA prototype verification platform. Fig. 2 is a schematic structural diagram of an FPGA prototype verification platform.

The method comprises the following steps: and inserting the EMMC daughter card with the EMMC chip into an FPGA-based prototype verification platform, and generating a testcase version in a corresponding hardware environment according to the use flow of the prototype verification platform. And importing the version into the prototype verification platform through prototype verification platform software, normally starting according to the using steps of the user, and issuing CMD0, 1, 2, 3, 7, 9 and 6 according to the steps in the operation document to initialize the EMMC chip. And then, the local data file is imported into a user write memory through a user memory page of the GUI interface, and the data in the memory is written into the EMMC chip through a write command. And finally, reading the EMMC data back into the user read memory through a read command, checking the user read memory through a GUI interface, and comparing the read memory with the local data to prove that the read-write function is available. This makes it possible to verify that there is no problem with the prototype verification platform from the exit of the user's design to the entrance of the external EMMC chip.

After the testcase module is introduced, the testcase engineering is downloaded to the prototype verification platform, and the initialization and data reading and writing of the EMMC chip can be completed according to the example operation, so that whether the hardware link is normal or not can be proved. The user can also eliminate the timing problem by comparing the exit data of testcase under the same operation with the difference of the exit data designed by the user. The problem locating process is simplified.

In summary, the present invention provides an FPGA prototype verification platform capable of verifying an EMMC user interface, which manages each terminal configured in each client clinic and applications installed on each terminal by constructing a packaging device, a management terminal, and a terminal client program terminal; the invention effectively solves the management difficulty problems of multi-channel clients, various applications, parallel versions and the like, effectively senses the range influenced by the applications and the version changes, effectively controls the whole upgrading process of the applications, provides a completely feasible scheme for the sensing, monitoring, diagnosis and recovery of the managed applications, and particularly effectively guarantees the quick recovery of catastrophic accidents such as damage of client computer equipment, loss of running configuration and the like; a large amount of labor cost can be reduced in the aspects of deployment, installation and upgrade management of the application; and when facing tens of thousands of enterprise customers using the application, the method can efficiently and timely find the application operation problems, timely respond to the feedback of the customers, and greatly improve the acceptance and satisfaction of the customers to the company. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. An FPGA prototype verification platform capable of verifying an EMMC user interface, the platform comprising:

the testcase module is used for outputting user test instruction data which corresponds to a user design interface connected with an external EMMC chip and executes the same test operation on the EMMC chip;

and the user interface conversion module is connected with the testcase module and used for sending the user test instruction data to an external EMMC chip connected with the user interface conversion module so as to execute corresponding test operation on the external EMMC chip, so that whether a hardware link in the user design interface connected to the external EMMC chip through the FPGA prototype verification platform is correct or not is determined by judging whether the test operation is successfully completed on the external EMMC chip or not.

2. The FPGA prototype verification platform capable of verifying EMMC user interfaces of claim 1, wherein said testcase module comprises:

and the parameterization module is used for generating user operation instruction data which accords with the time sequence of the external EMMC chip and corresponds to the same test operation executed on the EMMC chip by a user design interface connected with the external EMMC chip according to the parameters input through the platform visual interface of the FPGA prototype verification platform.

3. The FPGA prototype verification platform capable of verifying EMMC user interfaces of claims 1 or 2, wherein said testcase module comprises: and the data import module is used for importing the user operation instruction data through a platform visual interface of the FPGA prototype verification platform.

4. The FPGA proto-verification platform capable of verifying an EMMC user interface of claim 1, wherein said platform visualization interface of said FPGA proto-verification platform is configured to determine whether said testing of said external EMMC chip is completed.

5. The FPGA prototype verification platform capable of verifying EMMC user interfaces of claim 4, wherein said means for determining whether said testing of said external EMMC chip is complete comprises:

comparing operation result data fed back on the platform visual interface by the test operation corresponding to the external EMMC chip executed based on the user operation instruction with operation result data corresponding to the test operation executed by the external EMMC chip executed by the user design interface; if the test result is consistent with the test result, the test operation on the external EMMC chip is judged to be successfully completed; otherwise, the completion is not successful.

6. The FPGA prototype verification platform capable of verifying EMMC user interfaces of claim 5, wherein said testcase module stores a test operation step file corresponding to a test operation to be performed on said EMMC chip, comprising: user test instruction data corresponding to one or more test operations executed on the EMMC chip and operation result data corresponding to each test operation executed on the EMMC chip by the user design interface are respectively obtained.

7. The FPGA prototype verification platform capable of verifying EMMC user interfaces of claim 1, wherein said user test instruction data comprises: initialization operation instruction data corresponding to initialization operation and/or read-write operation instruction data corresponding to read-write operation.

8. The FPGA proto-verification platform according to claim 4 for verifying an EMMC user interface, further comprising means for determining whether the timing sequence is consistent by comparing the entry waveform captured by the platform visual interface for the user interface transformation module with the entry waveform at the user interface transformation module by said user design interface.

9. The FPGA proto-verification platform capable of verifying EMMC user interfaces of claim 1, wherein said testcase module employs a testcase version that is associated with a location of said EMMC chip at a socket of said FPGA proto-verification platform.

10. The FPGA prototype verification platform capable of verifying an EMMC user interface of claim 3, wherein the data importing module is further configured to import the user operation instruction data and operation result data corresponding to the test operation corresponding to the user operation instruction data executed by the EMMC chip corresponding to the user design interface through an internal RAM of the platform visual interface.