CN115621147B - Wafer detection method and device and electronic equipment - Google Patents
Wafer detection method and device and electronic equipment Download PDFInfo
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- CN115621147B CN115621147B CN202211568168.3A CN202211568168A CN115621147B CN 115621147 B CN115621147 B CN 115621147B CN 202211568168 A CN202211568168 A CN 202211568168A CN 115621147 B CN115621147 B CN 115621147B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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Abstract
The application provides a wafer detection method, a wafer detection device and electronic equipment, and detection result recording aiming at each target crystal grain on a target wafer can be automatically realized by controlling the cooperation of image acquisition equipment, a test probe and other equipment, so that the wafer detection efficiency can be effectively improved, and the possible misoperation risk of manual detection is reduced.
Description
Technical Field
The application relates to the field of semiconductor device manufacturing, in particular to a wafer detection method and device and electronic equipment.
Background
In the manufacturing process of the display chip, the die (die) needs to be inspected at the wafer stage, and in the inspection process, each die (die) on the chip is subjected to probe test, and is contacted with a contact (pad) on the die through a special probe card (probe card), so as to transmit a test signal to the die to test the electrical characteristics of the die. Unqualified dies are marked, and when the wafer is cut into independent dies by taking the dies as units, the marked unqualified dies are eliminated and the next process is not carried out, thereby reducing the manufacturing cost. However, in the conventional wafer inspection process, each step is mainly performed manually, so that the execution efficiency is low, and misoperation is easy to occur.
Disclosure of Invention
In order to overcome the above-mentioned deficiencies in the prior art, the present application aims to provide a wafer inspection method, which includes:
acquiring an image of a target wafer positioned on a bearing table through image acquisition equipment;
determining a target crystal grain on the target wafer according to the image of the target wafer;
controlling a test probe to be electrically contacted with the target crystal grain, and transmitting a test signal to the target crystal grain through the test probe;
acquiring the working voltage/working current of the target crystal grain through the test probe, and detecting whether the working voltage/working current is abnormal or not to obtain a first detection result;
if the working voltage/working current is abnormal, stopping transmitting the test signal and removing the contact between the test probe and the target crystal grain;
if the working voltage/working current is not abnormal, controlling the image acquisition equipment to acquire a display state image of the target crystal grain, determining whether the target crystal grain is abnormal or not according to the display state image, obtaining a second detection result, stopping transmitting the test signal, and removing the contact between the test probe and the target crystal grain;
and determining a new target crystal grain on the target wafer.
In one possible implementation, the method further includes:
and generating a detection result mapping chart according to the position of each target crystal grain on the target wafer, the first detection result and the second detection result.
In one possible implementation, the step of determining a new target die on the target wafer includes:
determining whether there are any undetected dies on the target wafer;
if so, determining a new target crystal grain in the undetected crystal grains;
and if not, finishing the detection of the target wafer.
In a possible implementation manner, before the step of acquiring the image of the target wafer located on the carrier stage by the image acquisition device, the method further includes:
and controlling the bearing table to move the target wafer to a set image acquisition area.
In one possible implementation, the method further includes:
and inputting the detection result mapping charts of the target wafers into a pre-trained manufacturing process problem prediction model to obtain a manufacturing process problem prediction result output by the manufacturing process problem prediction model.
In a possible implementation manner, the detection result map includes pixel points corresponding to positions of the target crystal grains on the target wafer, and values of the pixel points are detection result vectors formed by detection results of the target crystal grains; the detection result vector comprises current and voltage, display brightness and display chromaticity which are fed back by the target crystal grain in the detection process.
In a possible implementation manner, the step of inputting the detection result maps of the plurality of target wafers into a pre-trained manufacturing process problem prediction model to obtain a manufacturing process problem prediction result output by the manufacturing process problem prediction model includes:
splitting the detection result map into a first map and a second map; the value of each pixel point in the first mapping chart is the current voltage fed back by the target crystal grain in the detection process; the value of each pixel point in the second mapping chart is the display brightness and the display chromaticity of the target crystal grain;
inputting the first mapping chart into a first feature extraction module of the manufactured flow problem prediction model to obtain a first feature chart;
inputting the second mapping chart into a second feature extraction module of the manufactured flow problem prediction model to obtain a second feature chart;
inputting the first feature map and the second feature map into a feature fusion module of the manufactured flow problem prediction model to obtain a fusion feature map;
and inputting the fusion characteristic diagram into a prediction classification module of the manufactured process problem prediction model to obtain a manufactured process problem prediction result.
Another objective of the present application is to provide a wafer inspecting apparatus, which includes:
the image acquisition unit is used for acquiring an image of a target wafer on the bearing table through image acquisition equipment;
the crystal grain confirmation unit is used for confirming a target crystal grain on the target wafer according to the image of the target wafer;
the probe control unit is used for controlling a test probe to be electrically contacted with the target crystal grain and transmitting a test signal to the target crystal grain through the test probe;
the detection unit is used for acquiring the working voltage/working current of the target crystal grain through the test probe, and detecting whether the working voltage/working current is abnormal or not to obtain a first detection result; if the working voltage/working current is abnormal, stopping transmitting the test signal and removing the contact between the test probe and the target crystal grain; if the working voltage/working current is not abnormal, controlling the image acquisition equipment to acquire a display state image of the target crystal grain, determining whether the target crystal grain is abnormal or not according to the display state image, obtaining a second detection result, stopping transmitting the test signal, and removing the contact between the test probe and the target crystal grain;
the die verification unit is further configured to determine a new target die on the target wafer.
Another object of the present application is to provide an electronic device, which includes a processor and a machine-readable storage medium, where the machine-readable storage medium stores machine-executable instructions, and the machine-executable instructions, when executed by the processor, implement the wafer inspection method provided in the present application.
Another object of the present application is to provide a machine-readable storage medium, wherein the machine-readable storage medium stores machine executable instructions, which when executed by one or more processors, implement the wafer inspection method provided by the present application.
Compared with the prior art, the method has the following beneficial effects:
according to the wafer detection method, the wafer detection device and the electronic equipment, detection and detection result recording aiming at each target crystal grain on the target wafer can be automatically realized by controlling the cooperation of the image acquisition equipment, the test probe and other equipment, so that the wafer detection efficiency can be effectively improved, and the possible misoperation risk of manual detection can be reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a schematic view of a wafer inspection system according to an embodiment of the present disclosure;
FIG. 2 is a schematic flowchart illustrating a step of a wafer inspection method according to an embodiment of the present disclosure;
FIG. 3 is a second flowchart illustrating steps of a wafer inspection method according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram of an electronic device provided in an embodiment of the present application;
fig. 5 is a functional block diagram of a wafer inspection apparatus according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or orientations or positional relationships that the products of the present invention are conventionally placed in use, and are used only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
Furthermore, the terms "horizontal", "vertical", "suspended" and the like do not imply that the components are absolutely horizontal or suspended, but may be slightly inclined. For example, "horizontal" merely means that the direction is more horizontal than "vertical" and does not mean that the structure must be perfectly horizontal, but may be slightly inclined.
In the description of the present application, it is further noted that, unless expressly stated or limited otherwise, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
Referring to fig. 1, fig. 1 is a schematic view of a wafer inspection system according to the present embodiment, which may include an image capturing device 200, a testing device 300, and an electronic device 100 as an upper computer. The image capturing device 200 and the testing device 300 are connected to the electronic device 100, and the electronic device 100 can capture an image of a target wafer to be tested through the image capturing device 200. The testing apparatus 300 may include a probe carrier assembly capable of moving, and the electronic apparatus 100 may control the probe carrier assembly to bring a testing probe disposed on the probe carrier assembly into contact with a target die on the target wafer, and then control the testing apparatus 300 to transmit a testing signal to the target die through the testing probe.
Referring to fig. 2, fig. 2 is a wafer inspection method provided in the present embodiment, which can be executed on the electronic apparatus 100 shown in fig. 1, and the wafer inspection method provided in the present embodiment is described in detail below.
In step S110, an image of the target wafer on the susceptor 400 is acquired by the image capturing apparatus 200.
In a possible implementation manner, referring to fig. 1 again, the electronic device 100 may further be connected to a carrier 400, the carrier 400 is provided with a conveying structure for conveying a wafer, and the electronic device 100 may control the carrier 400 to move the target wafer to a set image capturing area. The electronic device 100 may perform feedback control on the movement of the stage 400 in combination with the signal collected by the image collecting device 200, so that the target wafer can be conveyed to a correct position.
Step S120, determining a target die on the target wafer according to the image of the target wafer.
Step S130, controlling a test probe to electrically contact with the target die, and transmitting a test signal to the target die through the test probe.
In this embodiment, the relative position relationship between the test probe and each die on the target wafer may be determined according to the image of the target wafer. In this embodiment, each die on the target wafer may be sequentially determined as the target die from a die at a predetermined position, and the test probe is controlled to contact the target die, so as to perform the detection on the target die through the subsequent steps.
The test signal may include a power supply signal and a display signal, and the test signal may drive the target die to enter a real operating state.
Step S140, obtaining the working voltage/working current of the target die through the test probe, and detecting whether the working voltage/working current is abnormal, so as to obtain a first detection result.
In this embodiment, the working voltage/working current of the target die may be sampled by the testing device, and compared with a preset threshold value or a preset algorithm according to a sampling result. Thereby determining whether the working voltage/working current is abnormal or not and obtaining a first detection result.
If the working voltage/working current of the target die is abnormal, no further detection is needed, and the step S160 is directly skipped to, the transmission of the test signal is stopped, and the contact between the test probe and the target die is released.
If there is no abnormality in the operating voltage/operating current, step S150 is executed for further detection.
Step S150, controlling the image capturing device 200 to capture a display state image of the target die, and determining whether the target die has display abnormality according to the display state image, so as to obtain a second detection result.
In this embodiment, if there is no abnormality in the operating voltage/operating current, the light emitting effect of the target die needs to be further detected, so that the image capturing device 200 may be controlled to capture the display state image of the target die. Optionally, the display state image may be compared with a corresponding preset reference image according to the position of the target crystal grain in brightness and chromaticity, and whether the target crystal grain has display abnormality is determined according to a comparison result.
After step S150 is completed, the process may jump to step S160 again to stop transmitting the test signal and release the contact between the test probe and the target die.
Step S170, determining a new target die on the target wafer.
After determining the new target die, the method may jump to step S130 to continue detecting the new target die.
Specifically, referring to fig. 3, step S170 may include step 171 and step S172.
In step S171, it is determined whether there are any undetected dies on the target wafer.
If yes, step S712 is executed to determine a new target die among the undetected dies.
And if not, finishing the detection of the target wafer.
Based on the design, in the wafer detection method provided by the embodiment of the application, detection and detection result recording for each target crystal grain on the target wafer can be automatically realized by controlling the cooperation of the image acquisition equipment, the test probe and other equipment, so that the wafer detection efficiency can be effectively improved, and the possible misoperation risk of manual detection can be reduced.
In some possible implementation manners, after the detection of the working voltage/working current or the detection of the display state of the target die is completed, a detection result map is generated according to the position of each target die on the target wafer, the first detection result and the second detection result.
Specifically, in a possible implementation manner, the detection result map may include a plurality of pixel points, and each pixel point corresponds to one die position on the target wafer. The value of the pixel point may be a numerical value or a character representing the first detection result and/or the second detection result. For example, different characters or codes may be used to characterize normality, current/voltage abnormality, and display abnormality, respectively. In this way, in the subsequent process of cutting the wafer, the wafer with a problem can be rejected according to the indication of the detection result mapping chart.
Further, the first detection result and the second detection result may further include an identifier indicating the severity of the problem. For example, the severity indicator may include a problem severity level identified by a number, and in a subsequent process, a flow of die repair, wafer return or die reject rejection may be selected and executed according to the problem severity level.
In a possible implementation manner, after the detection of the target wafers is completed, the detection result maps of the target wafers may be input into a pre-trained manufacturing process problem prediction model, so as to obtain a manufacturing process problem prediction result output by the manufacturing process problem prediction model.
Specifically, in this embodiment, the manufacturing process problem prediction model may be based on a deep learning neural network model, which performs feature extraction according to the detection result map and performs classification prediction according to the extracted features, so as to predict what kind of problem in the previous manufacturing process the problem indicated by the first detection result and/or the second detection result in the detection result map may be generated. According to the training process or the training sample of the manufacturing process problem prediction model, the manufacturing process problem prediction result can comprise a metal sputtering process problem, a metal etching process problem, an evaporation material, an evaporation mask plate problem and the like.
In this case, the detection result map may record more information, for example, the detection result map includes pixel points corresponding to positions of the target dies on the target wafer, and values of the pixel points are detection result vectors formed by detection results of the target dies. The detection result vector comprises the current and voltage, the display brightness and the display chromaticity which are fed back by the target crystal grain in the detection process.
Specifically, in this embodiment, the manufacturing process problem prediction model may include a first feature extraction module, a second feature extraction module, a feature fusion module, and a prediction classification module.
When the detection result map is processed by the manufacturing flow problem prediction model, the detection result map may be split into a first map and a second map. The value of each pixel point in the first mapping chart is a current and voltage value fed back by the target crystal grain in the detection process and an identifier indicating whether the target crystal grain is normal or not, the current and voltage value can reflect the distribution condition of the target crystal grain with abnormal voltage/current and the distribution condition of the abnormal current/voltage value on the target crystal grain, and the displayed normal identifier can be obtained by comparing the displayed brightness with a preset normal brightness range value. The first mapping characteristic diagram can reflect the manufacturing problems of the driving unit, the connecting wire and the like in the array substrate which may exist in the manufacturing process flow.
The second mapping map can reflect the distribution situation of the target crystal grains displayed on the target wafer and the distribution situation of the numerical display effect, and can reflect whether the crystal grains have the problems of ink dots, apertures, color cast, white spots and the like. The second map may reflect manufacturing problems such as evaporation of organic electroluminescent materials that may exist in the manufacturing process flow.
The first map may then be input to a first feature extraction module of the manufactured flow problem prediction model to obtain a first feature map, and the second map may be input to a second feature extraction module of the manufactured flow problem prediction model to obtain a second feature map. Wherein the first and second feature extraction modules may include a plurality of down-sampling layers, a pooling layer, and a final full-connection layer, respectively.
And inputting the first feature diagram and the second feature diagram into the feature fusion module for manufacturing the flow problem prediction model to obtain a fusion feature diagram. Because some process problems may affect both the working voltage/current and the display effect of each die on the wafer, and the degrees of the effects are different, the fused feature map can represent more problem features on the target wafer by fusing the first feature map and the second feature map, so that the subsequent prediction classification is more accurate. In one example, the feature fusion module may directly stitch the first feature map and the second feature map together, and in another example, the feature fusion module may stitch feature vectors of pixels corresponding to positions in the first feature map and the second feature map, respectively, together. Some problems which need to be reflected only by combining the working current and voltage and the light-emitting effect can be reflected by the fusion characteristic diagram.
And finally, inputting the fusion characteristic diagram into a prediction classification module of the manufacturing process problem prediction model to obtain a manufacturing process problem prediction result.
Therefore, the detection result mapping chart is analyzed by combining the manufacturing process problem prediction model, the manufacturing process problem possibly existing in the preorder manufacturing process can be automatically and accurately predicted, and a more timely and accurate basis is provided for process improvement or problem elimination.
On the other hand, referring to fig. 4, fig. 4 is a block schematic diagram of the electronic device 100 shown in fig. 1 as an upper computer. The electronic device 100 may be a server, a personal computer, a notebook computer, a programmable controller, or other devices with logic processing capability. The electronic apparatus 100 includes a wafer inspection device 110, a machine-readable storage medium 120, and a processor 130.
The elements of the machine-readable storage medium 120, the processor 130, and the communication unit 140 are electrically connected to each other, directly or indirectly, to enable data transmission or interaction. For example, the components may be electrically connected to each other via one or more communication buses or signal lines. The wafer inspection apparatus 110 includes at least one software function module that can be stored in the form of software or firmware (firmware) in the machine-readable storage medium 120 or solidified in an Operating System (OS) of the electronic device 100. The processor 130 is configured to execute executable modules stored in the machine-readable storage medium 120, such as software functional modules and computer programs included in the wafer inspection apparatus 110.
The machine-readable storage medium 120 may be, but is not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Read-Only Memory (EPROM), an electrically Erasable Read-Only Memory (EEPROM), and the like. The machine-readable storage medium 120 is used for storing a program, and the processor 130 executes the program/can execute the wafer inspection method provided by this embodiment after receiving the execution instruction.
The processor 130 may be an integrated circuit chip having signal processing capabilities. The Processor may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; but may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. The various methods, steps, and logic blocks disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
Referring to fig. 5, the present embodiment further provides a wafer inspection apparatus 110, wherein the wafer inspection apparatus 110 includes at least one functional module that can be stored in a machine-readable storage medium 120 in a software form. Functionally, the wafer inspection apparatus 110 may include an image acquisition unit 111, a die recognition unit 112, a probe control unit 113, and an inspection unit 114.
The image acquiring unit 111 is configured to acquire an image of a target wafer on the susceptor through an image acquiring device.
In this embodiment, the image acquiring unit 111 may be configured to execute step S110 shown in fig. 2, and for a detailed description of the image acquiring unit 111, reference may be made to the description of step S110.
The die verification unit 112 is configured to determine a target die on the target wafer according to the image of the target wafer.
In this embodiment, the die verification unit 112 may be configured to perform step S120 shown in fig. 2, and the detailed description about the die verification unit 112 may refer to the description about step S120.
The probe control unit 113 is configured to control a test probe to electrically contact the target die, and transmit a test signal to the target die through the test probe.
In this embodiment, the probe control unit 113 may be configured to execute step S130 shown in fig. 2, and for a detailed description of the probe control unit 113, reference may be made to the description of step S130.
The detecting unit 114 is configured to obtain a working voltage/working current of the target die through the test probe, and detect whether the working voltage/working current is abnormal, so as to obtain a first detection result. And if the working voltage/working current is abnormal, stopping transmitting the test signal and removing the contact between the test probe and the target crystal grain. And if the working voltage/working current is not abnormal, controlling the image acquisition equipment to acquire a display state image of the target crystal grain, determining whether the target crystal grain is abnormal or not according to the display state image, obtaining a second detection result, stopping transmitting the test signal, and removing the contact between the test probe and the target crystal grain.
In this embodiment, the detecting unit 114 can be used to execute the steps S140 to S160 shown in fig. 2, and the detailed description about the detecting unit 114 can refer to the description about the steps S140 to S160.
The die verification unit 112 is further configured to determine a new target die on the target wafer.
In this embodiment, the die verification unit 112 is further configured to execute step S170 shown in fig. 2, and the detailed description about the die verification unit 112 may refer to the description about step S170.
In summary, the wafer detection method, the wafer detection device and the electronic device provided by the embodiment of the application can automatically realize detection and detection result recording for each target crystal grain on a target wafer by controlling the cooperation of the image acquisition device, the test probe and other devices, thereby effectively improving the wafer detection efficiency and reducing the possible misoperation risk of manual detection.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
The above description is only for various embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present application, and all such changes or substitutions are included in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (7)
1. A method of wafer inspection, the method comprising:
acquiring an image of a target wafer on a bearing table through image acquisition equipment;
determining a target crystal grain on the target wafer according to the image of the target wafer;
controlling a test probe to be electrically contacted with the target crystal grain, and transmitting a test signal to the target crystal grain through the test probe;
acquiring the working voltage/working current of the target crystal grain through the test probe, and detecting whether the working voltage/working current is abnormal or not to obtain a first detection result;
if the working voltage/working current is abnormal, stopping transmitting the test signal and removing the contact between the test probe and the target crystal grain;
if the working voltage/working current is not abnormal, controlling the image acquisition equipment to acquire a display state image of the target crystal grain, determining whether the target crystal grain is abnormal or not according to the display state image, obtaining a second detection result, stopping transmitting the test signal, and removing the contact between the test probe and the target crystal grain;
determining a new target crystal grain on the target wafer;
wherein the method further comprises:
generating a detection result mapping chart according to the position of each target crystal grain on the target wafer, the first detection result and the second detection result; the detection result mapping graph comprises pixel points corresponding to the positions of the target crystal grains on the target wafer, and the value of each pixel point is a detection result vector formed by the detection results of the target crystal grains; the detection result vector comprises a current voltage value, display brightness and display chromaticity which are fed back by the target crystal grain in the detection process;
and inputting the detection result mapping charts of the target wafers into a pre-trained manufacturing process problem prediction model to obtain a manufacturing process problem prediction result output by the manufacturing process problem prediction model.
2. The method of claim 1, wherein the step of determining a new target die on the target wafer comprises:
determining whether there are any undetected dies on the target wafer;
if so, determining a new target crystal grain in the undetected crystal grains;
and if not, finishing the detection of the target wafer.
3. The method of claim 1, wherein the step of inputting the inspection result maps of the target wafers into a pre-trained manufacturing process problem prediction model to obtain the prediction results of the manufacturing process problems outputted by the manufacturing process problem prediction model comprises:
splitting the detection result map into a first map and a second map; the value of each pixel point in the first mapping chart is a current and voltage value fed back by the target crystal grain in the detection process and a mark indicating whether the target crystal grain is normal or not; the value of each pixel point in the second mapping chart is the distribution of the display brightness value and the distribution of the display chromaticity value of the target crystal grain;
inputting the first mapping chart into a first feature extraction module of the manufactured flow problem prediction model to obtain a first feature chart;
inputting the second mapping chart into a second feature extraction module of the manufactured flow problem prediction model to obtain a second feature chart;
inputting the first feature map and the second feature map into a feature fusion module of the manufactured flow problem prediction model to obtain a fusion feature map;
and inputting the fusion characteristic diagram into a prediction classification module of the manufactured process problem prediction model to obtain a manufactured process problem prediction result.
4. The method of claim 1, wherein prior to the step of acquiring the image of the target wafer on the susceptor by the image acquisition device, the method further comprises:
and controlling the bearing table to move the target wafer to a set image acquisition area.
5. A wafer detection device, characterized in that, the wafer detection device includes:
the image acquisition unit is used for acquiring an image of a target wafer on the bearing table through image acquisition equipment;
the crystal grain confirmation unit is used for confirming a target crystal grain on the target wafer according to the image of the target wafer;
the probe control unit is used for controlling a test probe to be electrically contacted with the target crystal grain and transmitting a test signal to the target crystal grain through the test probe;
the detection unit is used for acquiring the working voltage/working current of the target crystal grain through the test probe, and detecting whether the working voltage/working current is abnormal or not to acquire a first detection result; if the working voltage/working current is abnormal, stopping transmitting the test signal and removing the contact between the test probe and the target crystal grain; if the working voltage/working current is not abnormal, controlling the image acquisition equipment to acquire a display state image of the target crystal grain, determining whether the target crystal grain is abnormal or not according to the display state image, obtaining a second detection result, stopping transmitting the test signal, and removing the contact between the test probe and the target crystal grain;
the die verification unit is further configured to determine a new target die on the target wafer.
6. An electronic device comprising a processor and a machine-readable storage medium having stored thereon machine-executable instructions that, when executed by the processor, implement the method of any of claims 1-4.
7. A machine-readable storage medium having stored thereon machine-executable instructions which, when executed by one or more processors, perform the method of any one of claims 1-4.
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