CN115618786B

CN115618786B - Creating and reusing customizable structured interconnects

Info

Publication number: CN115618786B
Application number: CN202211221542.2A
Authority: CN
Inventors: H-w·J·林; F·G·K·森德格; M·E·德鲁特; P·A·麦克库伯
Original assignee: Synopsys Inc
Current assignee: Synopsys Inc
Priority date: 2016-02-29
Filing date: 2017-02-28
Publication date: 2023-11-28
Anticipated expiration: 2037-02-28
Also published as: US20200089835A1; DE112017001063T5; CN108701168A; US20170249414A1; US10528696B2; US10909300B2; WO2017151681A1; CN108701168B; CN115618786A

Abstract

The customizable routing system allows a designer to create a customized connection layout that can be stored, converted to templates, reused, and further customized. The system describes the custom connection layout entered by the designer in terms of "structural instructions" that specify their patterns and properties rather than using precise dimensions. The structural instructions may describe a particular pattern of connections between structural components (e.g., skeletons or fishbones), placement, width, direction, or layer of a particular structural component, and properties of the structural component relative to other components. Such as by design constraints, these structural instructions are typically implemented during routing, which allows the router to locally optimize the design while taking into account the structural intent of the designer (e.g., for cost or wire length). The system may also learn and replicate custom patterns based on existing layout templates by comparing connectivity information to connectivity information of existing layout templates and applying applicable structural instructions.

Description

Creating and reusing customizable structured interconnects

The application is a divisional application of the application patent application with international application number of PCT/US2017/020046, international application date of 2017, 2 month and 28 days, chinese national stage date of entering of 2018, 8 month and 28 days, national application number of 201780013858.3 and the application name of 'creation and reuse of customizable structured interconnection'.

Cross Reference to Related Applications

The present application claims the benefit of U.S. provisional patent application serial No. 62/301,059, filed on date 2016, 2 and 29, entitled "Method to Create and Reuse Customizable Structured Interconnects," which is incorporated herein by reference in its entirety.

Technical Field

The present disclosure relates generally to designing Integrated Circuits (ICs), and more particularly to reusable custom structured interconnect designs.

Background

Routing is an integral part of integrated circuit design, but batch routers rarely achieve truly optimal results due to the troublesome nature of routing problems. Instead, they rely on heuristics to achieve "good enough" results that are often focused on goals such as cost. Custom routing is often inconsistent with these goals because they frequently require features that are not considered by the bulk router, such as symmetry or redundancy. Redundancy is particularly a problem because it is inherently not "necessary" from a batch router perspective and therefore is a cost that should be reduced. Thus, customizable routing is typically performed manually, which is cumbersome and time consuming. Furthermore, reusing carefully designed structured interconnects for similar layouts typically requires a large amount of adjustments, which are also time consuming.

Disclosure of Invention

Embodiments relate to customizable wiring systems that enable a designer to create custom connection layouts that can be stored, exported as templates, reused, and customized. This saves the designer time, without having to manually construct each custom connection layout for each design, and without having to manually modify for similar but different circuits. By describing the designer-entered custom connection layout according to "structural instructions" that specify their patterns and properties, rather than using precise dimensions, the customizable routing system can generate layout templates that can be applied to similar designs or further custom in the future, in addition to reapplying to the same design. This enables a designer to make design modifications in another design with different connectivity information or follow the structural principles of a previous design. Further, structural instructions are typically implemented during the routing process, such as through design constraints, which allow the router to improve the design while reflecting the structural intent of the designer (e.g., for cost or wire length).

In one embodiment, a customizable routing system generates customized layout connections by receiving connectivity information for one or more circuit elements and a user-defined layout that shows a physical layout of connections between the one or more circuit elements. The connectivity information may take the form of a schematic or netlist. The user-defined layout includes initial structural components and may be conveyed via a graphical interface or interactive drawing in an existing visual representation. The customizable routing system then extracts one or more structural instructions from the user-defined layout, such as by analyzing the layout to determine one or more structural instructions that can be used to describe the physical structure of the connection. Each structural instruction describes properties of the physical layout of the connections between one or more circuit elements, such as a particular connection pattern between structural components (e.g., skeletons or fishbones), placement, width, direction, or layer of a particular structural component, and properties of the structural component relative to other structural components. The configuration instructions may specify placement of the connection relative to one or more rows at which at least one circuit element of the one or more circuit elements is disposed. For example, the connection may be placed closer to the center of the channel between the corresponding row than between two of one or more rows. The customizable routing system stores one or more structural instructions as a layout template of the received connectivity information, which can then be selected (and modified if desired) and applied to future designs. The customizable routing system may further route one or more circuit elements while maintaining the attributes described by the structural instructions.

In one embodiment, the customizable routing system learns and/or replicates the customized pattern based on existing layout templates. In particular, the customizable routing system stores one or more layout templates, each layout template representing a physical layout of connections between one or more source circuit elements of the source circuit. Each layout template includes structural instructions describing attributes of the corresponding physical layout of the connection. The customizable routing system identifies one or more layout templates associated with connectivity information for one or more target circuit elements of the target circuit. The connectivity information of the target circuit element may match connectivity information of one or more source circuit elements for at least one of the identified one or more layout templates. Alternatively, the connectivity information of the target circuit element may be a scaled version of the connectivity information that adds or removes devices (in series or parallel) of at least one of the identified one or more layout templates. The plurality of identified one or more layout templates may represent a physical layout for the same one or more source circuit elements. The routing system may be customized to apply the structural instructions of the identified one or more layout templates to one or more target circuit elements of the target circuit for routing the one or more target circuit elements. The customizable routing system may apply the identified one or more layout templates by: one or more modifications to the layout templates are identified, structural instructions of the identified one or more layout templates are revised in accordance with the one or more modifications, and the revised structural instructions are sent for routing the one or more target circuit elements. The modification may include adding one or more redundant connections. The modification may be identified by: one or more differences between connectivity information of one or more target circuit elements and connectivity information of one or more source circuit elements of the identified one or more layout templates are determined, and then considered. The customizable routing system may further divide the connectivity information for the target circuit element into a plurality of chunks, and each of the one or more layout templates identified may correspond to one of the plurality of chunks.

Drawings

FIG. 1 is a flowchart illustrating various operations for designing and manufacturing an Integrated Circuit (IC) according to one embodiment.

FIG. 2 is a high-level block diagram illustrating an example of a computing device for performing custom design of an IC according to one embodiment.

Fig. 3 is a block diagram illustrating the architecture of a customizable routing system according to one embodiment.

Fig. 4A-4E are visual representations of example connection layouts corresponding to various structural instructions, according to one embodiment.

FIG. 5 is a flow diagram illustrating a method for creating a layout template, according to one embodiment.

Fig. 6A is a schematic diagram of a portion of an IC according to the first embodiment.

Fig. 6B is a connection diagram corresponding to a part of the IC in fig. 6A according to the first embodiment.

Fig. 6C is a layout diagram illustrating a customized connection layout corresponding to the connection diagram of fig. 6B according to the first embodiment.

Fig. 7A is a schematic diagram of a portion of an IC according to a second embodiment.

Fig. 7B is a connection diagram corresponding to a part of the IC in fig. 7A according to the second embodiment.

Fig. 7C is a layout diagram illustrating a customized connection layout corresponding to the connection diagram of fig. 7B according to the second embodiment.

FIG. 8 is a flow diagram illustrating a method for customizing an existing layout template, according to one embodiment.

Fig. 9A and 9B are layout diagrams illustrating custom connection layouts that have been further customized for reuse according to one embodiment.

10A and 10B are diagrams illustrating a custom layout template set of ICs and their corresponding portions shown in a schematic diagram according to one embodiment.

FIG. 11 is a flow diagram illustrating a method for automatically adapting existing layout templates for reuse according to one embodiment.

Fig. 12A is a connection diagram according to the first embodiment, which is different from the existing layout template available for reuse.

Fig. 12B is a layout diagram illustrating a connection layout corresponding to the connection diagram of fig. 12A according to the first embodiment.

Fig. 13A is a connection diagram different from an existing layout template available for reuse according to the second embodiment.

Fig. 13B is a layout diagram illustrating a connection layout corresponding to the connection diagram of fig. 12A according to the second embodiment.

Detailed Description

The drawings and the following description relate to preferred embodiments by way of illustration only. It should be noted that from the following discussion, alternative embodiments of the structures and methods disclosed herein will be readily recognized as viable alternatives that may be employed without departing from the principles of what is claimed.

Reference will now be made in detail to several embodiments, examples of which are illustrated in the accompanying drawings. Note that where possible, similar or like reference numerals may be used in the drawings and may indicate similar or like functionality. The figures depict embodiments of the disclosed system (or method) for purposes of illustration only. Those skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles described herein.

Embodiments relate to a layout template that includes structural instructions describing a particular connection pattern between structural components, an arrangement, width, direction, or layer of a particular structural component, and properties of the structural component relative to other components. The templates may be generated by a user or automatically by analyzing the physical layout of the connections between source circuit elements of the source circuit. The layout templates may be applied without modification or by modification to target circuit elements of the target circuit for performing routing between the target circuit elements.

The circuit elements described herein refer to elements in a circuit layout. The circuit elements may be active circuit elements (e.g., transistors) or passive circuit elements (e.g., resistors, capacitors, and inductors).

The structural components described herein refer to the branches (tap-off), trunk, and spine that create the physical connections between the pins of the circuit elements. A branch refers to a connection that extends directly to or from a pin. A backbone refers to a connection to multiple pins. The spine connects to the spine and/or other spines.

Overview of EDA design flow

FIG. 1 is a flowchart illustrating various operations for designing and manufacturing an integrated circuit, according to one embodiment. The design process 100 begins with the production of a product idea 110, the product idea 110 being implemented during a design process using Electronic Design Automation (EDA) software 112. When the design is complete, it may be subjected to a tape-out 134. After dicing, semiconductor die are fabricated 136 to form various objects (e.g., gates, metal layers, vias) in the integrated circuit design. The packaging and assembly process 138 is performed, which results in a finished chip 140.

The EDA software 112 may be implemented in one or more computing devices, such as the computing device 200 of FIG. 2. For example, EDA software 112 is stored as instructions in a computer-readable medium that are executed by a processor for performing operations 114-132 of a design flow, which will be described below. The design flow description is for illustrative purposes. In particular, the description is not meant to limit the disclosure. For example, an actual integrated circuit design may require a designer to perform the design operations in a different sequence than the sequence described herein.

During system design 114, the designer describes the functionality to be implemented. They can also perform "what-if planning" to refine functionality and check costs. Note that hardware-software architecture partitioning may occur at this stage. Example EDA software products from Synopsys, inc. of mountain view, calif. that can be used at this stage include: modelSystem/>And->And (5) a product.

During logic design and functional verification 116, VHDL or Verilog code for modules in the circuit is written and the design is checked for functional accuracy. More specifically, the design is checked to ensure that it produces the correct output. Example EDA software products from Synopsys, inc. of mountain view, calif. that can be used at this stage include: 10/>and->And (5) a product.

During synthesis and design for test 118, VHDL/Verilog is converted to a netlist. The netlist can be optimized for the target technology. In addition, tests may be designed and implemented to check the finished chip. Example EDA software products from Synopsys, inc. of mountain view, calif. that can be used at this stage include: designPhysical/> Power/>FPGAAnd->And (5) a product.

During netlist verification 120, the netlist is checked for compliance with timing constraints and for correspondence with the VHDL/Verilog source code. Example EDA software products from Synopsys, inc. of mountain view, calif. that can be used at this stage include: And->And (5) a product.

During design planning 122, an overall plan view of the chip is constructed and analyzed for timing and top level routing. Example EDA software products from Synopsys, inc. of mountain view, calif. that can be used at this stage include:and IC->And (5) a product.

During the physical implementation 124, placement (positioning of circuit elements) and routing (connection thereof) occurs. Example EDA software products from Synopsys, inc. of mountain view, calif. that can be used at this stage include: cupAnd IC->And (5) a product. The embodiments described herein relate generally to physical implementations 124.

During circuit analysis 126, the circuit function is verified at the transistor level, which allows refinement. Example EDA software products from Synopsys, inc. of mountain view, calif. that can be used at this stage include:and Star->And (5) a product.

During physical verification 128, the design is checked to ensure correctness in the following: manufacturing, electrical problems, lithographic problems, and circuitry. Example EDA software products from Synopsys, inc. of mountain View, calif. that can be used at this stage includeAnd (5) a product.

During resolution enhancement 130, geometric manipulations of the layout are performed to improve manufacturability of the design. Example EDA software products from Synopsys, inc. of mountain view, calif. that can be used at this stage include: AF and->And (5) a product.

During mask data preparation 132, "tape-out" data for producing a mask to produce a finished chip is provided. Example EDA software products from Synopsys, inc. of mountain View, calif. that can be used at this stage includeSerial products. Formal verification may be performed at the stage of logic design and functional verification 116. The low power design specification is typically handled during stage synthesis and design for test 118 or netlist verification 120.

Embodiments of the present disclosure may be used during one or more of the above-described stages. In particular, embodiments may be used in the process of designing the plan 122 and the physical implementation 124.

Overview of computing devices

FIG. 2 is a block diagram illustrating components of an example machine capable of reading instructions from a machine-readable medium and executing them in a processor (or controller). In particular, FIG. 2 shows a diagrammatic representation of a machine in the example form of a computer system 200 within which instructions 224 (e.g., software) for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In alternative embodiments, the machine operates as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, the machine may operate in the capacity of a server machine or a client machine in the server-client network environment, or as a peer machine in a peer-to-peer (or distributed) network environment.

The machine may be a server computer, a client computer, a Personal Computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a smart phone, a web appliance, a network router, switch or bridge, or any machine capable of executing instructions 224 (sequential or otherwise) that specify actions to be taken by that machine. Furthermore, while only a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute instructions 224 to perform any one or more of the methodologies discussed herein.

The example computer system 200 includes a processor 202 (e.g., a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Digital Signal Processor (DSP), one or more Application Specific Integrated Circuits (ASICs), one or more Radio Frequency Integrated Circuits (RFICs), or any combination of these), a main memory 204, and a static memory 206, which are configured to communicate with each other via a bus 208. The computer system 200 may further include: a graphic display unit 210 such as a Plasma Display Panel (PDP), a Liquid Crystal Display (LCD), a projector, or a Cathode Ray Tube (CRT). Computer system 200 may also include an alphanumeric input device 212 (e.g., a keyboard), a cursor control device 214 (e.g., a mouse, trackball, joystick, motion sensor, or other pointing instrument), a storage unit 216, a signal generation device 218 (e.g., a speaker), and a network interface device 220, which are also configured to communicate via bus 208.

The storage unit 216 includes a machine-readable medium 222 on which are stored instructions 224 (e.g., software) embodying any one or more of the methodologies or functions described herein. The instructions 224 (e.g., software) may also reside, completely or at least partially, within the main memory 204 or within the processor 202 (e.g., within the processor's cache memory) during execution thereof by the computer system 200, the main memory 204 and the processor 202 also constituting machine-readable media. The instructions 224 (e.g., software) may be transmitted or received over a network 226 via the network interface device 220.

While the machine-readable medium 222 is shown in an example embodiment to be a single medium, the term "machine-readable medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) that are capable of storing the instructions (e.g., instructions 224). The term "machine-readable medium" shall also be taken to include any medium that is capable of storing instructions (e.g., instructions 224) for execution by the machine and that cause the machine to perform any one or more of the methodologies disclosed herein. The term "machine-readable medium" includes, but is not limited to, data storage libraries in the form of solid state memory, optical media, and magnetic media.

Customizable wiring system

Fig. 3 is a block diagram illustrating the architecture of a customizable routing system 300 according to one embodiment. Customizable routing system 300 enables a user (designer) to design customized structured interconnects that can then be manufactured via a batch routing process or a non-batch routing process. The customizable wiring system 300 shown in fig. 3 includes a circuit design store 310, a structural instruction store 320, a structural instruction fetch module 330, a layout customization module 340, and a template adaptation module 350. In other embodiments, customizable routing system 300 may include additional, fewer, or different components for various applications. Each of the above-described components may be embodied as modules in the memory 204 of the computer of the customizable wiring system 300. Conventional components such as network interfaces, security functions, load balancers, failover servers, management and network operations consoles, and the like are not shown to avoid obscuring the details of the system architecture.

Circuit design store 310 is a database that stores physical layout data for one or more circuits. Physical layout data for a particular circuit includes (physical) connection layout, schematic layout mapping information, a plurality of metal layers to be used, and physical processes associated with manufacturing the circuit. The connection layout is a visual representation of the physical placement of the connections between the circuit pins. Fig. 4A to 4E, 6B, 6C, 7B, 7C, 9A, 9B, 10A, 10B, 12B, and 13B include examples of connection layouts, as described in detail below. The schematic layout mapping information may indicate the grouping of pins of one or more circuit elements into one or more subsets of pins, and the correspondence of pins in one or more circuit elements with other pins in one or more circuit elements.

The circuit design store 310 also stores a "layout template" which is a set of structural instructions (described below in connection with the structural instruction store 320) that describes a particular connection layout associated with corresponding connectivity information. The connectivity information indicates which pins are connected and may be derived from schematic and schematic layout mapping information or provided directly in the form of a netlist or other similar indication. Although the circuit design store 310 is described as being part of the customizable wiring system 300, the circuit design store 310 may be part of another system external to the customizable wiring system 300. For example, the circuit design repository 310 may be embodied as an open access (OpenAccess) database.

The structure instruction store 320 is a database that stores "structure instructions" describing the general physical structure and placement of connections in a connection layout. The bulk wiring system (which may be part of the customizable wiring system 300 or may be a separate system) may interpret and apply the structural instructions, such as by having them design constraints. For example, the structure instructions may describe a connection pattern within a row or across multiple rows. The structural instructions may also describe properties of the structural component itself, such as orientation, width, placement (such as on an axis parallel to the structural component), and metal layers. The structural instructions may also indicate the type of pin being connected, such as diffusion, polysilicon, or a combination thereof. The structural instructions are discussed in more detail in connection with fig. 4A-4E.

The structural instruction fetch module 330 fetches structural instructions from the connection layout. To this end, the structural instruction fetch module 330 matches the connection layout with a known pattern associated with the structural instruction. For example, the structural instruction fetch module 330 may analyze the physical shapes present in the connection layout in conjunction with the logical connectivity and process data to determine the direction in which the branches should extend from the pins of the device (e.g., up, down, toward the central axis), how many trunks should be used (e.g., a single trunk, one trunk per three pins) to connect a row of branches, and the trunk(s) should be positioned relative to the row (e.g., offset from the central axis along the central axis in a direction toward or away from the row).

The layout customization module 340 generates a custom connection layout and a layout template. To "start from scratch" the custom connection layout is generated, the layout customization module 340 receives structural components from the designer, such as through drawing (e.g., existing layout data or in a graphical interface of the customizable wiring system 300) or text commands. The structural components are organized into custom connection layouts. To generate a custom connection layout based on an existing layout template, the layout customization module 340 retrieves the layout template and receives modifications to the structural component from the designer. The layout customization module 340 then generates a modified connection layout based on the connection layout from the retrieved layout template and the user modification. The layout customization module 340 may also generate layout templates from any of the types of custom connection layouts described above by storing the extracted structural instructions in association with corresponding logical structures (e.g., schematic fragments) in the circuit design store 310 for future use. In either scenario, structural instructions associated with the connection layout may additionally or alternatively be sent for bulk routing of the corresponding circuit elements.

The template adaptation module 350 generates a connection layout based on the adaptation to the existing layout template. For example, the target circuit may have similar connectivity information with one or more source circuits already associated with the layout template. Rather than requiring the designer to create another connection layout for the target circuit from scratch, the template adaptation module 350 automatically modifies (if necessary) and applies the structural instructions of the existing layout template to the target circuit to create the connection layout.

The template adaptation module 350 adapts the layout template by identifying pattern similarities while not requiring the same physical structure. For example, the layout template created from FIG. 4A (discussed further below) represents a two-row structure with one backbone in the channel under each row. For a four-row structure with similar device patterns, the template adaptation module 350 will determine that four stems are desired, each stem being placed in a channel under one of the four rows. Other adaptations performed by the template adaptation module 350 include expanding the number of devices per row and adjusting the backbone or spine placement to suit designs with different numbers of tracks. In some embodiments, the template adaptation module 350 may receive mapping guidance between techniques to guide the adaptation. For example, the original layout template may specify geometric dimensions and/or process layers relative to a particular technology. An external mapping specification may be applied to map a corresponding portion of the original layout template to the target circuit, the external mapping specification describing how layers of the target circuit correspond to layers of the source circuit associated with the original layout template and providing dimension reduction guidance.

In some embodiments, the designer can further customize the adapted connection layout through layout customization module 340. Either (or both) of the adapted connection layout or the further customized connection layout may also be stored as a layout template. The adaptation layout templates are discussed further below in connection with fig. 11-13B.

Connection layout attributes and structure instructions

The structural instructions describe general structural features of the structural components in the connection layout and may be categorized based on which aspects of the structural components they describe. For example, the structure instructions discussed below may be grouped into structures, attributes, and patterns. The structural instructions describing the structure indicate how the structural components are connected, the structural instructions describing the attributes specify the characteristics of the structural components themselves, and the structural instructions describing the pattern indicate how the structural components are organized on rows of pins. The structural instructions described below are merely examples, and are not intended to be limiting, of how the structural instructions correspond to a connection layout. Other embodiments or implementations may use other structural instructions to describe similar or additional structural components of the connection layout. Similarly, other embodiments or implementations may describe other structural features in place of, or in addition to, the specific structural features discussed below. The structure instructions are indicated below in curly brackets (i.e., { }) and may be separated by semicolons to delineate between rows.

Fig. 4A-4E are layout diagrams of example finfets corresponding to various structural instructions, according to one embodiment. Each of the examples 400 a-400 e includes a 16 pin FinFET, represented as a vertical rectangle. The 16 pins are organized into two rows of eight pins each, referred to as the "top row" (i.e., upper FinFET) and "bottom row" (i.e., lower FinFET). The top and bottom rows are separated by an intermediate channel that does not contain any pins. In some examples 400 a-400 e, there is also a bottom channel below the bottom row, which similarly does not contain any pins. The dark pins in the two rows represent the pins to be connected. The four middle pins in the top row are dark and are referred to as "top pins". The two outermost pins (i.e., four pins in total) on each side of the bottom row are also dark and are referred to as "bottom pins". Some examples 400 a-400 e do not explicitly show that the top pin is connected to the bottom pin. In practice, the stem(s) of the top pins and the stem(s) of the bottom pins may be connected by one or more spines. These spines connecting the top and bottom pins have been omitted for simplicity.

Fig. 4A to 4D illustrate examples of structures described by the structure instructions. Fig. 4A and 4B are examples of main structures { skeleton } ({ backbone }) and { fishbone } ({ fishbone }), respectively. Fig. 4C and 4D are examples of structural modifications { intermittence } ({ interaction }) and { match } ({ match }) that can be applied to the main structure. { skeleton }, { fish bone }, { intermittent }, and { matching } are structural instructions that may be used to describe the spine, and in some embodiments, they may also be used to describe the spine.

The example 400a of fig. 4A illustrates a { skeleton } structure featuring branches extending from only one side of the trunk. Branches 402 extend from four top pins into the middle channel and connect to a single trunk 404 in the middle channel. Branch 406a extends from the leftmost two bottom pins into the bottom channel. Branch 406b extends from the rightmost two bottom pins into the bottom channel. Both branches 406a and 400b are connected to a single trunk 408 in the bottom channel. The backbones 404 and 408 have branches 402 and 406a and 406b (respectively) on only one side, and will therefore be described by the structural instructions { skeleton }. Note that the unmodified { skeleton } structure includes a single backbone (e.g., 404 and 408) for each row of pins-even if the pins are not adjacently located (e.g., bottom pins).

The example 400B of fig. 4B illustrates a { fishbone } structure characterized by branches extending from both sides of the torso. As in example 400a, branches 402 extend downward from four top pins and connect to a single trunk 410 in a middle channel. However, unlike example 400a, branches 406a and 406b of the bottom pins extend upward from the four bottom pins into the middle channel and connect to the same backbone 410 to which the top pins are connected. The backbone 410 has branches extending from both sides to connect to pins on the top and bottom rows, and will therefore be described by the structural instructions { fishbone }.

Example 400C of fig. 4C illustrates { intermittent } modification to the { skeleton } structure. The { intermittent } modification is characterized by defining the number and placement of trunks based on groups of adjacent pins. The top pin connections of example 400c match those of example 400a, but the bottom pin connections now include two separate trunks 410a and 410b in the bottom channel instead of the single trunk 408. In example 400a, a single backbone 408 spans the entire length of the bottom channel, including four unconnected pins, to connect the leftmost two bottom pins to the rightmost two pins. However, the { intermittent } modification divides the single trunk 408 into multiple trunks 412a and 412b, each trunk 412a and 412b spanning only the portion of the bottom channel corresponding to the group of adjacent pins to which they are connected. Specifically, the two leftmost bottom pins are adjacent, so that the corresponding branch 406a is connected to one backbone 412a, and the two rightmost bottom pins are adjacent, so that the corresponding branch 406b is connected to the other backbone 412b. Unlike example 400a, here the second leftmost Bian Yinjiao and second rightmost bottom pins are not connected via one backbone.

In some embodiments, the pins need not be directly adjacent (i.e., literally adjacent) to each other to be considered adjacent for grouping purposes. For example, pins within four pins of each other may be considered to be adjacent and connected to the same backbone in a { intermittent } configuration. Additionally, in some cases, adjacency may only apply to the horizontal direction, such that pins in different rows are considered "adjacent" if they are in adjacent columns. Thus, according to the { intermittent } modifier, trunk connection pins (e.g., { fishbone } structure) in a plurality of rows can be decomposed into multiple trunks. The { intermittent } modifier may also have no effect on some backbones, such as those of the top row in example 400 c. When all pins connected to a backbone are adjacently located (e.g., top pins), there is no need to introduce multiple backbones, such that the { middle skeleton } structure is indistinguishable from the unmodified { skeleton } structure.

Example 400D of fig. 4D illustrates { matching } modification to { skeleton } structure. The { match } modification is characterized in that the common trunk length of all trunks in the connection layout is defined by the shortest trunk (e.g., the trunk connecting the smallest group of adjacent pins). The only difference between example 400d and example 400c is that in the bottom row, the single trunk 404 of example 400c is replaced with two trunks 414a and 414b to match the trunk lengths of trunks 412a and 412b, which connect the smallest group of adjacent pins. Similar to the { intermittent } modification, in some cases the { match } modification may not be distinguishable from other structures. For example, when looking at only the bottom row of examples 400c and 400d, the { matching skeleton } structure is indistinguishable from the { intermittent skeleton } structure.

The attribute structure instruction may be different from other structure instructions in that the attribute structure instruction is not a set of rules applied to a group of structural components, but reflects a particular value of the structural element(s). The example 400E of fig. 4E illustrates a specification of < track > properties for a backbone in a { skeleton } structure. The < track > attribute specifies the "track" of the channel in which the trunk(s) associated with the row are located. The < track > attribute is specified relative to the total number of available tracks, counting from the top. In example 400e, there is a first track 416 and a second track 418. The backbone 404 travels along the first track 416 so it will be described by the structure instructions track 1/2. Backbone 420 travels along second track 418 so it will be described by the structure instruction track 2/2. If an invalid value is entered for the < track > attribute, the customizable routing system 300 may round the value to the nearest valid value (e.g., when adapting the layout template). For example, if { track 3/5} is input for a channel having only three tracks, it will be rounded to { track 2/3}. In some embodiments, { over } ({ over }) may be added to the < track > attribute to indicate that the track is over the pin row instead of in the channel. For example, the structure instruction { upper track 1/3} describes such a backbone: it is on the first of the three tracks above the row of pins.

Other attributes include < row >, < width >, and < layer >. The < row > attribute specifies the number of pin rows connected to the backbone on one or more channels. For example, { row all } indicates that pins in all rows of the connection layout are connected to a single backbone, while { row 2} indicates that pins in the first two rows (from the row to which the structure instructions apply) are connected to a single backbone. The < row > attribute may also be used to specify whether the backbone is located above (described by { row up } or below (described by { row down } the connected row). The < width > attribute indicates the width of the stem. For example, { width 0.2} indicates that the width of the stem should be 20% of the default width. The < layer > attribute indicates a metal layer in which the backbone is to be manufactured. For example, one backbone may be designated as { layer M2}, while the other backbone is designated as being on { layer M1 }.

Although the above examples discuss structural instructions about the spine, some structural instructions may also be applied to the spine or even the branches. For example, the < width > and < layer > attributes may be additionally applied to branches and spines. In addition, the spine may have additional structural instructions describing properties such as < column > (similar to < row > for the spine with respect to the branches) or < direction > (e.g., { horizontal } or { vertical }). Further, general attributes such as < offset > may be applied to any structural element.

Returning to fig. 4E, example 400E also shows an example of a { mirror } pattern. The { mirror } pattern is characterized by reflection about the horizontal axis and affects the placement of stems in the channels above or below the rows of pins to which they are connected. As noted in connection with the explanation of the < track > attribute, backbone 420 connects the bottom pins and is located on the second track in the middle channel. In other examples 400 a-400 d, the backbone(s) connecting the bottom row pins are located in the bottom channel, which is the default behavior in these examples 400 a-400 e. Because example 400e includes a { mirror } pattern, the structural components for the bottom pins (branches 406a and 400b and backbone 420) are reflected through the center of the intermediate channel through the axis. This example is described by the structure instruction { skeleton mirror }.

The { mirror } pattern also applies any structure or attribute included in the rows that are the basis for mirroring to the mirror rows. For example, the structure instruction { intermittent skeleton layer M1 width 0.5 mirror } will result in: a first row, which may also be described by { intermittent skeleton layer M1 width 0.5}, a second row, which is described by { intermittent skeleton layer M1 width 0.5}, up to { intermittent skeleton layer M1 width 0.5}, which may be combined into { intermittent skeleton layer M1 width 0.5; intermittent skeleton line 1 is 0.5 width toward upper layer M1.

The { mirror } pattern may also be used for a multi-line pattern, which is represented as { mirror } that acts as its own line (i.e., after a semicolon). When the { mirror } pattern is used for multiple rows, any other row-based pattern is reflected about an axis through the central channel of the connection layout. If the specified row pattern is less than the row preceding the central axis, the specified row pattern is repeated. For example, if { skeleton line 1 is up; intermittent skeleton line 1 is downward; mirror image will be applied to a connection layout with six rows, the first row will be { skeleton row 1 up }, the second row will be { intermittent skeleton row 1 down }, the third row will be { skeleton row 1 up }, the fourth row will be { skeleton row 1 down }, the fifth row will be { intermittent skeleton row 1 up }, and the sixth row will be { skeleton row 1 down }.

Creating connection layout templates

FIG. 5 is a flow diagram illustrating a method 500 for creating a layout template, according to one embodiment. Fig. 6A-6C and 7A-7C illustrate two example applications of the method 500 of fig. 5. Customizable routing system 300 receives 510 connectivity information for a plurality of circuit elements being designed for structured interconnection. The connectivity indicates which pins of the plurality of circuit elements should be connected. Connectivity information may be communicated to the customizable routing system 300 in the form of schematic diagrams and corresponding schematic layout mapping information. Alternatively, the designer may manually select pins or input a matrix (or other similar representation) indicating the pins to be connected.

The customizable routing system 300 receives 520 initial structural components for the connection layout, such as from a designer, to form a customized connection layout. The designer may draw the initial structural components (e.g., the trunks and branches in fig. 4A-4E) through the interface of the customizable routing system 300, or submit another type of visual representation. In some embodiments, such as by way of detailed illustration, connectivity information and initial structural components may be received 510 and 520 together.

The customizable routing system 300 then converts 530 the initial structural component into structural instructions. The conversion 530 may be accomplished by analyzing patterns in the custom connection layout and matching them to similar known patterns described by the structural analysis. The customizable routing system 300 then generates 540 a layout template by associating connectivity information with structural instructions for customizing the connection layout, the layout template being stored 550 for future use. Future uses may include direct reuse (e.g., applying custom connection layout templates to the same design), indirect reuse (e.g., applying custom connection layout templates to similar designs without performing any modifications), or custom reuse, which are described by reference to methods 800 and 1100 of fig. 8 and 11, respectively.

Fig. 6A illustrates a schematic diagram 600 of a portion of an IC, and fig. 6B is a connectivity diagram corresponding to a physical representation of the schematic diagram 600 according to a first embodiment. Schematic 600 includes two transistors 602 and 604, with the gate connection 606 of transistor 602 highlighted to indicate that it is the connection to which the connection layout corresponds. The connectivity diagram of fig. 6B is a visual representation of four rows of pins separated by a first channel, a second channel, and a third channel, respectively. Line 620 reflects the connectivity information and indicates the pins 610, 612a, 612b, 614a, 614b, and 616 are to be connected. These pins have been darkened to distinguish them from pins that do not need to be connected in this example.

Fig. 6C is a customized connection layout 650 corresponding to the connectivity diagram of fig. 6B according to the first embodiment. In the first row, branch 652a extends downward from the leftmost three pins 610 to connect to backbone 654a in the first channel, and branch 652b extends downward from the rightmost three pins 610 to connect to backbone 654b in the first channel. Both trunks 654a and 654b are located on the first track { track 1/2} in the first lane. In the second row, branch 656a extends upward from pin 612a to connect to backbone 658a in the first channel, and branch 656b extends upward from pin 612b to connect to backbone 658b in the first channel. Both trunks 658a and 658b are located on the second track { track 2/2} in the first channel. In the third row, branch 660a extends downward from pin 614a and connects to backbone 662a in the third channel, and branch 660b extends downward from pin 614b and connects to backbone 662b in the third channel. Both backbones 662a and 662b are located on the first track 1/2 in the third channel. In the fourth row, branch 664a extends upward from the three rightmost pins 616 to connect to backbone 666a in the third channel, and branch 664a extends upward from the three rightmost pins 616 to connect to backbone 666b in the third channel. Both trunks 666a and 666b are located on the second track 2/2 of the third channel. Backbones 658a and 662a are connected via spine 668a, backbones 654a and 666a are connected via spine 670a, backbones 654b and 666b are connected via spine 670a, and backbones 658b and 662b are connected via spine 668 b. The vertebrae 668a, 668b, 670a and 670b are connected by a horizontal spine 672.

Connection layout 650 is described by structure instructions { match skeleton mirror }. Each backbone 654a, 654b, 658a, 658b, 662a, 622b, 666a and 666b has only branches extending from one side, making it a { skeleton } structure. In addition, each backbone 654a, 654b, 658a, 658b, 662a, 662b, 666a and 666b has the same length, i.e., the length of backbones 658a, 685b, 662a and 662b, because they are connected to the smallest group of pins (i.e., three pins), resulting in { match } modifications. Finally, the stem placement in the second row is a reflection of the stem placement in the first row through the center of the first channel through the axis, which is a { mirror } pattern. More generally, trunks 654a, 654b are on tracks x/n in the channel below the corresponding row (first channel), and trunks 656a, 656b are on tracks (n-x+1)/n in the channel above the corresponding row (first channel). The third and fourth rows then have the same attributes as the first and second rows, and need not be explicitly described, as the structural instructions are automatically repeated. Connection layout 650 may also be more explicitly described by other structural instructions, such as { match trunk 1 down track 1/2; matching main row 1 up track 2/2.

Fig. 7A is a schematic diagram 700 of a portion of an IC, and fig. 7B is a connectivity diagram corresponding to a physical implementation of the schematic diagram 700, according to a second embodiment. Schematic 700 includes two transistors 602 and 604, with the gate connection 706 of transistor 604 highlighted to indicate that it is a connection that is designing a connection layout. The connectivity diagram of fig. 7B is a visual representation of four rows of pins separated by a first channel, a second channel, and a third channel, respectively. Line 720 reflects the connectivity information and indicates the pins 710a, 710b, 712, 714, 716a, and 716b are to be connected. These pins have been darkened to distinguish them from pins that do not need to be connected in this example.

Fig. 7C is a customized connection layout 750 corresponding to the connectivity diagram of fig. 7B, according to a second embodiment. In the first row, branch 752a extends downward from the leftmost three pins 610a to connect to backbone 754a in the first channel, and branch 752b extends downward from the rightmost three pins 710 to connect to backbone 754b in the first channel. Both trunks 754a and 754b are located on the first track { track 1/2} in the first lane. In the second row, branches 756 extend upward from pins 712 to connect to trunks 758 in the first channel. Backbone 758 is located on the second track { track 2/2} in the first channel. In the third row, branch 760 extends downward from pin 714 and connects to trunk 762 in the third channel. The backbone 662 is located on the first track 1/2 in the third channel. In the fourth row, branch 764a extends upward from the leftmost three pins 616a to connect to backbone 766a in the third channel, and branch 764a extends upward from pin 616b to connect to backbone 766b in the third channel. Both trunks 766a and 766b are located on the second track { track 2/2} of the third channel. Trunks 754a and 766a are connected via spine 768a, trunks 754a and 660a are connected via redundant spines 770a and 770b, trunks 754b and 760b are connected via spine 770a, and trunks 758 and 662 are connected via spines 770a and 770 b. The spines 768a, 768b, 770a and 770b are connected by a horizontal spine 772.

The connection layout 750 is mirrored by the structure instruction { intermittent skeleton; mirror } description. Each backbone 754a, 754b, 758, 762, 766a, 766b has only branches extending from one side, making it a { backbone } structure. In addition, backbones 658a, 658b, 662a and 662b are separated due to { intermittent } modifications. Finally, similar to connection layout 650, the trunk placement in the second row is a reflection of the trunk placement in the first row through the center of the first channel through the axis, which is a { mirror } pattern. The third and fourth rows are then reflections of the first and second rows across the central axis of the connection layout 750 (which passes through the middle of the second channel). The connection layout 750 may also be more explicitly described by other structural instructions.

Customizing connection layout templates for reuse

FIG. 8 is a flow diagram illustrating a method 800 for customizing an existing layout template, according to one embodiment. Customizable routing system 300 first receives 810 a selection of an existing layout template that is to be modified for particular connectivity information. In one embodiment, there may be only one layout template associated with the connectivity information. In this case, the submission of connectivity information constitutes the receipt 810 of the selection, as only one option is available. In other embodiments, several layout templates may be associated with connectivity information, in which case the received 810 selection may be a user selection between a plurality of applicable layout templates or an automatic system selection based on achieving design goals.

Once the layout template is selected, customizable routing system 300 receives 820 a customization from the designer, such as through a drawing in a graphical interface. The customizable routing system 300 then analyzes the customization of the connection layout to determine and update 830 the structural instructions associated with the layout template. The updated structural instructions may then be used to wire connections and/or generate 840 another layout template that is stored 850 for further use or customization in the future.

Fig. 9A and 9B are example custom connection layouts 900 and 950 that have been customized for reuse using method 800, according to one embodiment. Fig. 9A illustrates a connection layout 900, which is a customized version of the connection layout 650. The customization is performed to generate a connection layout 900, the customization including: removing two vertical spines, moving two remaining vertical spines, and extending the spine. Specifically, the connection layout 900 includes spines 918a and 918b, the spines 918a and 918b being placed between the third pin and the fourth pin of each row, and between the ninth pin and the tenth pin of each row. Because there are now only two vertical spines 918a, 918b, each of the backbones 904a, 904b, 908a, 908b, 912a, 912b, 916a and 916b is extended to connect to the spine. Similarly, the horizontal spinal column 922 is shorter than the original horizontal spinal column 672 because the spinal columns 918a, 918b are not as far as the spinal columns 668a, 668b, 670a and 670 b. If the space between each pin is considered a track, this customization can be described as { spine track 3/11/8/11 }, which defines all vertical spines (i.e., no other vertical spines 900 are present in the connection layout). Alternatively, the structural instructions may define the customized vertical spine 918a, 918b in relative terms, such as between the backbones 908a/912a and 904a/916a, and between the backbones 904b/916b and 908b/912 b.

Fig. 9B illustrates a connection layout 950, which is a customized version of the connection layout 750. The customization is performed to generate a connection layout 950, the customization including: the stems for the second and third rows are moved to the same track as the stems of the first and fourth rows, the two external vertical spines are moved, and two additional vertical spines are added. Specifically, backbone 958 is placed on { track 1/2} instead of { track 2/2}, and backbone 962 is placed on { track 2/2} instead of { track 1/2} in the third channel. If there is one track through the center of each pin, the vertical spines 968a, 968b, 969a, 969b, 970a and 970b are now described as { spine track 1/12 3/12 5/12 8/12 10/12 }. The horizontal spine 972 is also longer to accommodate the position of the outermost vertical spines 968a, 968 b. The structural instructions may be similarly defined in relative terms, such as designating that the trunks 958 and 962 are located on default tracks of trunks 754a, 754b, 764a and 764b, respectively, and that the modified vertical spines 968a, 968b, 970a and 970b are located at outer edges of the corresponding trunks 754a, 754b, 766a and 766 b.

10A and 10B are diagrams illustrating a custom layout template set and its corresponding schematic portions, according to one embodiment. Each schematic portion (or other type of connectivity information) may be associated with a plurality of layout templates. Fig. 10A indicates that the illustrative portion 600 is associated with connection layouts 650 and 900 because both connection layouts 650 and 900 connect the same pins of the associated connectivity graph of fig. 6B. The schematic portion 600 and the connection layouts 650 and 900 may be considered together as a layout template, or the schematic portion 600 paired with the connection layout 650 may be considered one layout template and the schematic portion 600 paired with the connection layout 900 may be considered another layout template. Fig. 10B indicates that the illustrative portion 700 is associated with connection layouts 750 and 950 because both connection layouts 750 and 950 connect the same pins of the associated connectivity graph of fig. 7B. Similarly, illustrative portion 700 and connection layouts 750 and 950 may be considered together as one layout template or in an illustrative portion connection layout pairing as one layout template.

Automatically adjusting connection layout templates for reuse

FIG. 11 is a flow diagram illustrating a method 1100 for automatically adapting existing layout templates for reuse, according to one embodiment. The boxes with dashed lines indicate that those steps (1120, 1140, 1150, and 1170) are optional.

The customizable routing system 300 receives 1110 connectivity information for a plurality of target circuit elements of a target circuit. In some embodiments, the customizable routing system 300 separates 1120 the connectivity information for the circuit elements into a plurality of chunks, which may or may not overlap. Each chunk represents a subset of connectivity information for a target circuit element and may be used to match the connectivity information with a plurality of existing layout templates that may be combined to achieve connectivity of the target circuit element. FIG. 13B illustrates an example chunk.

The customizable routing system 300 identifies 1130 one or more similar layout templates that may be applied to a plurality of target circuit elements (or chunks). For example, by having connectivity information that matches or can be scaled to match the connectivity information of the target circuit element or its chunks, one or more similar layout templates can be "similar". Fig. 12A illustrates an example of scaling. If desired, the customizable routing system 300 determines connectivity differences between one or more similar layout templates and updates 1140 the structural instructions for the layout templates.

The customizable routing system applies 1150 the structural instructions (or the structural instructions of update 1140, if applicable) to the connectivity information received 1110, which may then be used to route 1160 the plurality of circuit elements.

Fig. 12A is a connectivity diagram 1200 according to a first embodiment, which is different from the connectivity diagram of an existing layout template that is available for reuse. The connectivity diagram 1200 has four rows of 16 pins. Line 1220 indicates that pins 1210, 1212a, 1212b, 1214a, 1214b, and 1216 are to be connected. The customizable routing system 300 receives the connectivity map 1200, the connectivity map 1200 not matching any of the previously mentioned connectivity maps. However, customizable wiring system 300 can analyze the connectivity information and determine that it is a horizontally scaled version of the connectivity graph of fig. 6B.

In this context, horizontal scaling means that the general connectivity pattern and the number of rows remain the same, but the number of pins per row increases in a scaled manner. For example, in connectivity diagram 1200, four pins per group corresponds to three pins per group in the connectivity diagram of fig. 6B. Specifically, there are eight pins 1210 corresponding to six pins 610, four pins 1212a corresponding to three pins 612a, four pins 1212b corresponding to three pins 1212b, four pins 1214a corresponding to three pins 614a, four pins 1214b corresponding to three pins 1214b, and eight pins 1216 corresponding to six pins 610. Thus, connectivity map 1200 scales 4/3 in the horizontal direction (pin count) relative to the connectivity map of FIG. 6B. The connectivity map may be scaled in the vertical direction based on the number of rows rather than the pin count per row.

Based on this analysis and determination, custom batch router system 300 may adapt a layout template corresponding to the connectivity diagram of fig. 6B. Using the layout template with connection layout 900, customizable routing system 300 determines that it needs to make a major structural adjustment to change { vertical spine 3/11,8/11} to { vertical spine 4/15,11/15}. Alternatively, the spine may be defined in relative terms (such as those described in connection with fig. 9A and 9B), in which case no structural adjustments are required.

The customizable routing system 300 updates the structural instructions accordingly and generates a corresponding connection layout 1250, as shown in fig. 12B.

The connection layout 1250 of FIG. 12B repeats the connection layout 900 with a 4/3 horizontal scaling. Branches 1252a, 1252b, 1256a, 1256b, 1260a, 1260b, 1264a, and 1264b correspond to branches 652a, 652b, 656a, 656b, 660a, 660b, 664a, and 664b, respectively. Backbones 1254a, 1254b, 1258a, 1258b, 1262a, 1262b, 1266a and 1266b correspond to backbones 904a, 904b, 908a, 908b, 912a, 912b, 916a and 916b, respectively. The spines 1268a, 1268b and 1272 correspond to the spines 918a, 918b and 922, respectively. Although connection layout 1250 has a different size (and thus different connectivity information) than connection layout 900, connection layout 1250 retains the structural aspects of connection layout 900. Specifically, connection layout 1250 has only two vertical spines 1268a, 1268b, with the two vertical spines 1268a, 1268b being located between (1) backbone 1256a/1262a and backbone 1254a/1266a, and (2) backbone 1254a/1266b and 1258b/1262 b.

Fig. 13A is another connectivity diagram 1300 according to the second embodiment, which is different from the connectivity diagram of an existing layout template that is available for reuse. The connectivity diagram 1300 has four rows of 24 pins. The customizable routing system 300 analyzes the connectivity map 1300 and determines that it can divide it into two chunks 1310 and 1320, each corresponding to an existing layout template. Block 1310 matches the connectivity of the connectivity map of FIG. 6B, and block 1320 matches the connectivity of the connectivity map of FIG. 7B. The customizable routing system 300 retrieves the structural instructions for the corresponding connection layouts 900 and 950, determines that the only modification it needs to apply is to combine the horizontal spines 922 and 972 and modify the structural instructions appropriately. The wiring system 300 can then customize the connection layout 1350 of fig. 13B by applying the connection layout 900 to the tiles 1310 to generate half 1360 of the connection layout 1350, applying the connection layout 950 to the tiles 1320 to generate the other half 1370 of the connection layout 1350, and connecting the two horizontal spines.

The foregoing description of embodiments of the invention have been presented for purposes of illustration; it is not intended to be exhaustive or to limit the invention to the precise form disclosed. Those skilled in the relevant art will appreciate that many modifications and variations are possible in light of the above disclosure.

The language used in the specification has been principally selected for readability and instructional purposes, and may not have been selected to delineate or circumscribe the inventive subject matter. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by any claims issued based on the applications herein. Accordingly, the disclosure of the embodiments of the invention is intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.

Claims

1. A method for designing an integrated circuit, comprising:

receiving at least one first layout template representing a physical layout of connections associated with one or more source circuit elements of a source circuit;

receiving one or more structural instructions corresponding to the at least one first layout template, each structural instruction of the one or more structural instructions describing a different attribute of a physical layout of a connection associated with the one or more source circuit elements;

receiving connection information for a plurality of target circuit elements of a target circuit;

identifying one or more second layout templates by comparing connectivity information of the target circuit elements with physical layouts of connections associated with the one or more source circuit elements, the second layout templates representing physical layouts of connections associated with one or more of the target circuit elements;

Updating the one or more structural instructions such that each of the updated one or more structural instructions describes a different attribute of the physical layout of the connection associated with the one or more target circuit elements; and

the one or more updated structural instructions of the identified one or more second layout templates are applied to the one or more target circuit elements of the target circuit for routing the one or more target circuit elements.

2. The method of claim 1, further comprising:

identifying one or more modifications of the one or more second layout templates relative to the at least one first layout template;

revising one or more structural instructions of the identified one or more second layout templates in accordance with the one or more modifications; and

the one or more target circuit elements are routed using the revised one or more structural instructions.

3. The method of claim 2, wherein the one or more modifications comprise adding one or more redundant connections to the at least one first layout template.

4. The method of claim 2, wherein identifying the one or more modifications comprises:

One or more differences between a subset of connectivity information of the one or more target circuit elements and a physical layout of connections associated with the one or more source circuit elements are determined.

5. The method of claim 2, further comprising:

the revised one or more structural instructions are stored as the one or more second layout templates for a subset of connectivity information of the one or more target circuit elements.

6. The method of claim 1, wherein at least a subset of connectivity information of the one or more target circuit elements matches a physical layout of connections associated with the one or more source circuit elements.

7. The method of claim 1, wherein a plurality of the identified one or more second layout templates represent a physical layout for the one or more source circuit elements.

8. The method of claim 1, further comprising:

the connectivity information of the target circuit element is divided into a plurality of chunks,

wherein each of the identified one or more second layout templates corresponds to a respective chunk of the plurality of chunks.

9. The method of claim 8, wherein one or more chunks of the plurality of chunks match a physical layout of connections associated with the one or more source circuit elements.

10. The method of claim 1, wherein the subset of connectivity information for the one or more target circuit elements is a scaled version of connectivity information for a physical layout of connections associated with the one or more source circuit elements.

11. A non-transitory computer-readable medium comprising computer-executable instructions that, when executed by one or more processors, cause the one or more processors to:

12. The computer-readable medium of claim 11, wherein the commands further cause the one or more processors to:

13. The computer-readable medium of claim 12, wherein the one or more modifications comprise adding one or more redundant connections to the at least one first layout template.

14. The computer-readable medium of claim 12, wherein the commands further cause the one or more processors to:

15. The computer-readable medium of claim 12, wherein the commands further cause the one or more processors to:

16. The computer-readable medium of claim 11, wherein at least a subset of connectivity information of the one or more target circuit elements matches a physical layout of connections associated with the one or more source circuit elements.

17. The computer-readable medium of claim 11, wherein a plurality of the identified one or more second layout templates represent a physical layout for the one or more source circuit elements.

18. The computer-readable medium of claim 11, wherein the commands further cause the one or more processors to:

19. The computer-readable medium of claim 18, wherein one or more of the plurality of chunks matches a physical layout of connections associated with the one or more source circuit elements.

20. The computer-readable medium of claim 11, wherein the subset of connectivity information for the one or more target circuit elements is a scaled version of connectivity information for a physical layout of connections associated with the one or more source circuit elements.