CN115617400B - Register matching method and device - Google Patents
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- CN115617400B CN115617400B CN202211638123.9A CN202211638123A CN115617400B CN 115617400 B CN115617400 B CN 115617400B CN 202211638123 A CN202211638123 A CN 202211638123A CN 115617400 B CN115617400 B CN 115617400B
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
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Abstract
The invention provides a register matching method and a device, wherein the method comprises the steps of dividing a first register and a second register to obtain a plurality of continuous first units corresponding to the first register and a plurality of continuous second units corresponding to the second register, simultaneously comparing all corresponding first units and second units, if the corresponding first units and second units are matched with each other, determining a ranking value of a first identifier of a matched target identifier in the first unit from a low position to a high position, and the total number of the first identifiers in all the first units lower than the matched target unit, summing the ranking value and the number, and outputting a summation value. When the method provided by the invention is used for matching two registers, the position value required to be obtained can be quickly output, and meanwhile, the method has the advantages of short matching time, less time delay and less limitation, can be suitable for most scenes and has excellent effect.
Description
Technical Field
The invention belongs to the technical field of registers, and particularly relates to a register matching method and device.
Background
Registers are small storage areas inside a CPU (Central Processing Unit) for storing data, and are used for temporarily storing data participating in operations and operation results. Generally, a register is a common sequential logic circuit, but the sequential logic circuit only comprises a storage circuit, the storage circuit of the register is formed by latches or flip-flops, and since one latch or flip-flop can store 1-bit binary number, an N-bit register can be formed by N latches or flip-flops. Registers are high-speed memory units of limited memory capacity, and are also components within the central processing unit, and may be used to temporarily store instructions, data, and addresses.
Registers can be divided into two broad categories, basic registers and shift registers, according to their functions. The basic register can only be used for parallel input and parallel output, the data in the shift register can be sequentially shifted to the right or left bit by bit under the action of shift pulses, and the data can be input in parallel and output in parallel, can be input in series and output in series, can be input in parallel and output in series, or can be input in series and output in parallel, so that the method is very flexible and has wide application.
When the two registers are matched (the matching aims at generating a preset instruction triggered if the matching is successful, and the preset operation can be executed by executing the preset instruction, such as executing an interrupt operation, a connection operation, or generating a positive pulse operation, so as to complete a related control or data transmission function), the method can be realized by using a shift register mode, but if the method is used, the delay of an output position result can generate longer delay under the worst condition, so that the method is not suitable for certain delay-sensitive application scenes; if the direct matching method is adopted, a long time is often needed to complete the matching.
Disclosure of Invention
In order to overcome the defects of the prior art, the present invention provides a register matching method, applied to matching a first register and a second register, where the bit widths of the first register and the second register are the same, the first register is recorded with a plurality of first identifiers and a plurality of second identifiers, and the second register is recorded with one first identifier and a plurality of second identifiers, the method includes:
dividing the first register and the second register in the same manner to obtain a plurality of continuous first units corresponding to the first register and a plurality of continuous second units corresponding to the second register, wherein the number of the first units is the same as that of the second units, each first unit corresponds to a unique second unit, and the relative positions of the corresponding first units and the corresponding second units in the respective registers are the same; all the areas of the first unit and all the second unit for storing the identification are continuous;
simultaneously comparing all corresponding first units with the corresponding second units;
if the first unit and the second unit which correspond to each other realize the matching of the first identification, setting the first identification matched in the first unit as a target identification, and setting the first unit matched in the first unit as a target unit;
determining the ranking value of the first identifier, located in the first unit where the target identifier is located, from low to high, and the total number of the first identifiers in all first units ranked lower than the target unit;
summing the sorting values and the number, and outputting a summation value;
and if the matching of the first unit and the second unit is not finished, outputting a corresponding unmatched preset value.
Specifically, the first flag is 1, and the second flag is 0.
Preferably, said aligning all corresponding said first units and said second units comprises:
aiming at each corresponding first unit and second unit, carrying out bitwise calculation on the first unit and the second unit;
if the calculation result is 1, confirming that the first unit and the second unit realize the matching of the first identifier;
and if the calculation result is 0, confirming that the first unit and the second unit cannot realize the matching of the first identifier.
Preferably, said aligning all corresponding said first units and said second units comprises:
for each corresponding first unit and second unit, judging whether the second unit has the first identifier or not; if the first identification exists, setting the existing first identification as a reference identification, and determining a reference relative position of the reference identification in the second unit;
if the identifier of the reference relative position in the first unit is a first identifier, confirming that the first unit and the second unit realize the matching of the first identifier;
and if the mark of the reference relative position in the first unit is not the first mark, confirming that the first unit and the second unit cannot realize the matching of the first mark.
The present invention also proposes a register matching apparatus for implementing the method as described above, said apparatus comprising:
the dividing module is used for dividing the first register and the second register in the same mode to obtain a plurality of continuous first units corresponding to the first register and a plurality of continuous second units corresponding to the second register; the number of the first units is the same as that of the second units, each first unit corresponds to a unique second unit, and the relative positions of the corresponding first units and the corresponding second units in respective registers are the same; all the areas of the first unit and all the second unit for storing the identification are continuous;
the comparison module is used for simultaneously comparing all the corresponding first units with the corresponding second units;
the setting module is used for setting the first identifier matched in the first unit as a target identifier and setting the first unit matched in the first unit as a target unit when the first unit and the second unit which correspond to each other realize the matching of the first identifier;
the statistical module is used for determining the ranking value of the first identifier, positioned in the first unit where the target identifier is positioned, from the low order to the high order, and the total number of the first identifiers in all the first units which are ranked lower than the target unit;
and the first output module is used for summing the sorting values and the number and outputting a summation value.
Specifically, the apparatus further comprises:
and the second output module is used for outputting a corresponding unmatched preset value when the matching of the first unit and the second unit is not completed.
Specifically, the first flag is 1, and the second flag is 0.
Preferably, the alignment module comprises:
a calculation unit, configured to perform bitwise and calculation on the first unit and the second unit for each corresponding first unit and second unit;
if the calculation result is 1, confirming that the first unit and the second unit realize the matching of the first identifier;
and if the calculation result is 0, confirming that the first unit and the second unit cannot realize the matching of the first identifier.
Preferably, the alignment module comprises:
a first judging unit, configured to judge, for each corresponding first unit and second unit, whether the second unit has the first identifier;
a determining unit, configured to set the existing first identifier as a reference identifier and determine a reference relative position of the reference identifier in the second unit when the determination result of the first determining unit is existence;
a second judgment unit configured to judge whether or not the marker of the reference relative position in the first unit is the first marker; if the judgment result is yes, the first unit and the second unit are confirmed to realize the matching of the first identifier; and if the judgment result is negative, confirming that the first unit and the second unit cannot realize the matching of the first identifier.
The invention has at least the following beneficial effects:
the method provided by the invention divides the two registers into a plurality of units, simplifies the process of the registers during matching, has the advantages of higher speed, less limitation and shorter time delay compared with the traditional mode, and can be suitable for most register matching scenes.
Furthermore, the comparison mode of the method provided by the invention is flexible and rapid, and the grouping can be further divided on the basis of units, so that the effect of parallel computation is achieved, and the matching speed is further improved on the basis of the original method.
Therefore, the invention provides a register matching method and a device, when the method provided by the invention is used for matching two registers, the position value required to be obtained can be rapidly output, and meanwhile, the method has the advantages of short matching time, less time delay and less limitation, can be suitable for most scenes and has excellent effect.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic overall flow chart of a register matching method provided in embodiment 1;
FIG. 2 is a schematic diagram of a register partitioning;
FIG. 3 is a schematic diagram of a cell partition into groups;
FIG. 4 is a schematic block diagram of the steps performed in a packet within a cell;
fig. 5 is a schematic block diagram of a register matching apparatus according to embodiment 2.
Reference numerals:
1-a partitioning module; 2-an alignment module; 3-setting a module; 4-a statistical module; 5-a first output module; 6-a second output module; 21-a calculation unit; 22-a first judgment unit; 23-a determination unit; 24-a second judging unit.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Various embodiments of the present invention will be described more fully hereinafter. The invention is capable of various embodiments and of modifications and variations therein. However, it should be understood that: there is no intention to limit various embodiments of the invention to the specific embodiments disclosed herein, but on the contrary, the intention is to cover all modifications, equivalents, and/or alternatives falling within the spirit and scope of various embodiments of the invention.
Hereinafter, the terms "includes" or "may include" used in various embodiments of the present invention indicate the presence of the disclosed functions, operations, or elements, and do not limit the addition of one or more functions, operations, or elements. Furthermore, as used in various embodiments of the present invention, the terms "comprises," "comprising," "includes," "including," "has," "having" and their derivatives are intended to mean that the specified features, numbers, steps, operations, elements, components, or combinations of the foregoing, are only meant to indicate that a particular feature, number, step, operation, element, component, or combination of the foregoing, and should not be construed as first excluding the existence of, or adding to the possibility of, one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.
In various embodiments of the invention, the expression "or" at least one of a or/and B "includes any or all combinations of the words listed simultaneously. For example, the expression "a or B" or "at least one of a or/and B" may include a, may include B, or may include both a and B.
Expressions (such as "first", "second", and the like) used in various embodiments of the present invention may modify various constituent elements in various embodiments, but may not limit the respective constituent elements. For example, the above description does not limit the order and/or importance of the elements described. The foregoing description is for the purpose of distinguishing one element from another. For example, the first user device and the second user device indicate different user devices, although both are user devices. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of various embodiments of the present invention.
It should be noted that: in the present invention, unless otherwise explicitly stated or defined, the terms "mounted," "connected," "fixed," and the like are to be construed broadly, e.g., as being fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium; there may be communication between the interiors of the two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, it is to be understood by those skilled in the art that the terms indicating an orientation or positional relationship herein are based on the orientation or positional relationship shown in the drawings only for the convenience of description and simplicity of description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention.
The terminology used in the various embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the various embodiments of the invention. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present invention belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments of the present invention.
Example 1
The embodiment provides a register matching method, which is applied to matching of a first register and a second register, where bit widths of the first register and the second register are the same, the first register is recorded with a plurality of first identifiers and a plurality of second identifiers, and the second register is recorded with a first identifier and a plurality of second identifiers, please refer to fig. 1, where the method includes:
and step A, dividing the first register and the second register in the same mode respectively to obtain a plurality of continuous first units corresponding to the first register and a plurality of continuous second units corresponding to the second register, and entering the step B.
It should be noted that, in this embodiment, the first register includes a large-bit-width register, and the second register includes a one-hot-code template register, please refer to fig. 2, where the number of the first units is the same as that of the second units, each first unit corresponds to a unique second unit, and the relative positions of the corresponding first unit and the corresponding second unit in the respective registers are the same; all first cells are contiguous with all second cells' areas for storing the identity.
The bit width of the large-bit-width register and the bit width of the one-hot code template register, which are used for recording the identification, are both 256 bits, the large-bit-width register and the one-hot code template register are divided to obtain four first units and four second units, and the bit width of the first units and the bit width of the second units are 64 bits.
And step B, simultaneously comparing all corresponding first units with all corresponding second units, and judging whether the corresponding first units and the corresponding second units realize the matching of the first identification.
If the first unit and the second unit which correspond to each other are matched with the first identifier, entering the step C; and F, if the first unit and the second unit which correspond to each other do not exist to realize the matching of the first identifier, entering the step F.
And step C, setting the first identifier matched in the first unit as a target identifier, setting the first unit matched in the first unit as a target unit, and entering the step D.
And D, determining the ranking value of the first identifiers in the first unit where the target identifiers are located from low to high and the total number of the first identifiers in all the first units with the ranking lower than that of the target unit, and entering the step E.
And E, summing the sorting values and the number, and outputting a sum value.
And F, outputting corresponding unmatched preset values.
In this embodiment, the first identifier is 1, the second identifier is 0, and the "unmatched preset value" in step F is 0.
Preferably, the step of "aligning all corresponding first units with second units" in step B may include:
aiming at each corresponding first unit and second unit, carrying out bitwise calculation on the first unit and the second unit;
if the calculation result is 1, the first unit and the second unit are confirmed to realize the matching of the first identifier;
and if the calculation result is 0, confirming that the first unit and the second unit cannot realize the matching of the first identifier.
Preferably, the step B of "aligning all corresponding first units with second units" may further include:
judging whether a first identifier exists in the second unit or not aiming at each corresponding first unit and second unit; if the judgment result is that the first identifier exists, setting the existing first identifier as a reference identifier, and determining the reference relative position of the reference identifier in the second unit;
if the mark of the reference relative position in the first unit is the first mark, the first unit and the second unit are confirmed to realize the matching of the first mark;
and if the mark of the reference relative position in the first unit is not the first mark, confirming that the first unit and the second unit cannot realize the matching of the first mark.
Further, referring to fig. 3, the packet may be further divided based on the divided units, and the unit is replaced by the packet in the above steps as an executed unit, the way of dividing the packet by the unit is the same as the way of dividing the unit by the register, in this embodiment, each of the first unit and the second unit is divided to obtain eight first packets and eight second packets, and the bit width of the first packets and the second packets is 8 bits.
In this embodiment, the large bit width register and the one-hot template register are used to indicate the status of the device in the system. The large bit width register is used for indicating whether the device of the application layer configuration is selected or not, and the one-hot code register is used for indicating the position of the current device in the system. The system has 32 board cards, each board card comprises eight deviceids (Device identifications) including dev0-dev7 (dev is the abbreviation of Device and the Chinese name is Device), and the sequence of the deviceids (Device identifications) corresponds to the bits; because each dev (Device abbreviated as Device) can only be located on one board card, the boards are mutually exclusive, so that eight groups divided by the same unit can be calculated in parallel, and the purpose of increasing the highest clock frequency is achieved, and fig. 4 is a schematic block diagram of the step executed by the groups. The calculation of the position value of one unit can be completed in each clock cycle, and after four clock cycles, the calculation of the position value of 256 bits in total of four units can be completed.
Example 2
The present embodiment provides a register matching apparatus for implementing the method of embodiment 1, please refer to fig. 5, the apparatus includes:
the device comprises a dividing module 1, a first storage module and a second storage module, wherein the dividing module is used for dividing a first register and a second register respectively in the same mode to obtain a plurality of continuous first units corresponding to the first register and a plurality of continuous second units corresponding to the second register;
the comparison module 2 is used for comparing all corresponding first units and second units at the same time;
the setting module 3 is used for setting the first identifier matched in the first unit as a target identifier and setting the first unit matched in the first unit as a target unit when the first unit and the second unit which correspond to each other are matched with each other;
the statistical module 4 is used for determining the ranking value of the first identifier of the first unit where the target identifier is located from low to high, and the total number of the first identifiers in all the first units with lower ranking than the target unit;
and the first output module 5 is used for summing the sorting values and the number and outputting a summation value.
It should be noted that the number of the first units divided by the dividing module 1 is the same as the number of the second units, each first unit corresponds to a unique second unit, and the relative positions of the corresponding first unit and the corresponding second unit in the respective registers are the same; all first cells are contiguous with all second cells' areas for storing the identity.
In this embodiment, the first register includes a large-bit-width register, the second register includes a unique code template register, the large-bit-width register and the unique code template register are used for recording that the bit widths of the identifiers are 256 bits, the dividing module 1 divides the large-bit-width register and the unique code template register to obtain four first units and four second units, and the bit widths of the first units and the second units are 64 bits.
Specifically, the system further comprises:
and the second output module 6 is used for outputting the corresponding unmatched preset value when the corresponding first unit and the second unit are not matched.
In this embodiment, the first identifier is 1, the second identifier is 0, and the "unmatched preset value" output by the second output module 6 is 0.
Preferably, the alignment module 2 comprises:
a calculating unit 21, configured to perform bit-wise calculation on the first unit and the second unit for each corresponding first unit and second unit;
if the calculation result is 1, the first unit and the second unit are confirmed to realize the matching of the first identifier;
and if the calculation result is 0, confirming that the first unit and the second unit cannot realize the matching of the first identifier.
Preferably, the alignment module 2 comprises:
a first judging unit 22, configured to judge, for each corresponding first unit and second unit, whether a first identifier exists in the second unit;
a determination unit 23 configured to set the existing first identifier as a reference identifier and determine a reference relative position of the reference identifier in the second unit when the determination result of the first determination unit 22 is presence;
a second judgment unit 24 for judging whether the mark of the reference relative position in the first unit is the first mark; if the judgment result is yes, the first unit and the second unit are confirmed to realize the matching of the first identification; if the judgment result is negative, the first unit and the second unit are confirmed to be incapable of realizing the matching of the first identification.
Further, the grouping may be further divided by the dividing module 1 based on the divided units, and in the above steps, the grouping is performed by using the grouping instead of the unit as an executed unit, the way of dividing the grouping by the unit is the same as the way of dividing the unit by the register, in this embodiment, eight first groups and eight second groups are obtained by dividing each of the first unit and the second unit, and the bit widths of the first groups and the second groups are 8 bits.
In this embodiment, the large bit width register and the one-hot template register are used to indicate the status of the device in the system. The large bit width register is used for indicating whether the device of the application layer configuration is selected or not, and the one-hot code register is used for indicating the position of the current device in the system. The system has 32 board cards, each board card comprises eight deviceids (Device identifications) including dev0-dev7 (dev is the abbreviation of Device and the Chinese name is Device), and the sequence of the deviceids (Device identifications) corresponds to the bits; because each dev (Device, abbreviated as a Device in chinese) can only be located on one board, the boards are mutually exclusive, and thus eight groups divided by the same unit can be calculated in parallel, thereby achieving the purpose of increasing the highest clock frequency.
In summary, the present invention provides a register matching method and device, when the method provided by the present invention is used to match two registers, the position value required to be obtained can be output quickly, and meanwhile, the method requires a shorter matching time, requires less delay, has fewer limitations, can be applied to most scenes, and has an excellent effect.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (6)
1. A register matching method, applied to matching of a first register and a second register, where bit widths of identifiers recorded in the first register and the second register are the same, the first register is recorded with a plurality of first identifiers and a plurality of second identifiers, the second register is recorded with one first identifier and a plurality of second identifiers, the first identifier is 1, and the second identifier is 0, the method comprising:
dividing the first register and the second register in the same manner to obtain a plurality of continuous first units corresponding to the first register and a plurality of continuous second units corresponding to the second register; the number of the first units is the same as that of the second units, each first unit corresponds to a unique second unit, and the relative positions of the corresponding first units and the corresponding second units in respective registers are the same; all the areas of the first unit and all the second unit for storing the identification are continuous;
simultaneously comparing all corresponding first units with the corresponding second units; the comparing all corresponding first units and second units comprises: aiming at each corresponding first unit and second unit, carrying out bitwise calculation on the first unit and the second unit; if the calculation result is 1, confirming that the first unit and the second unit realize the matching of the first identifier; if the calculation result is 0, confirming that the first unit and the second unit cannot realize the matching of the first identifier;
if the first unit and the second unit which correspond to each other realize the matching of the first identification, setting the first identification matched in the first unit as a target identification, and setting the first unit matched in the first unit as a target unit;
determining the ranking value of the first identifier of the first unit where the target identifier is located from low order to high order, and the total number of the first identifiers in all the first units with lower ranking than the target unit;
and summing the sorting value and the number, and outputting a summation value.
2. The register matching method according to claim 1, wherein if the matching is completed by the absence of the corresponding first unit and the second unit, a default value corresponding to a mismatch is output.
3. The register matching method according to claim 1, wherein said comparing all corresponding first units with corresponding second units comprises:
for each corresponding first unit and second unit, judging whether the second unit has the first identifier or not; if the first identification exists, setting the existing first identification as a reference identification, and determining a reference relative position of the reference identification in the second unit;
if the identifier of the reference relative position in the first unit is a first identifier, confirming that the first unit and the second unit realize the matching of the first identifier;
and if the mark of the reference relative position in the first unit is not the first mark, confirming that the first unit and the second unit cannot realize the matching of the first mark.
4. A register matching apparatus, applied to matching of a first register and a second register, where bit widths of identifiers recorded in the first register and the second register are the same, the first register is recorded with a plurality of first identifiers and a plurality of second identifiers, the second register is recorded with one first identifier and a plurality of second identifiers, the first identifier is 1, and the second identifier is 0, the apparatus comprising:
the dividing module is used for dividing the first register and the second register in the same mode to obtain a plurality of continuous first units corresponding to the first register and a plurality of continuous second units corresponding to the second register; the number of the first units is the same as that of the second units, each first unit corresponds to a unique second unit, and the relative positions of the corresponding first units and the corresponding second units in respective registers are the same; all the areas of the first unit and all the second unit for storing the identification are continuous;
the comparison module is used for simultaneously comparing all the corresponding first units with the corresponding second units; the comparing all corresponding first units and second units comprises: aiming at each corresponding first unit and second unit, carrying out bitwise calculation on the first unit and the second unit; if the calculation result is 1, confirming that the first unit and the second unit realize the matching of the first identifier; if the calculation result is 0, confirming that the first unit and the second unit cannot realize the matching of the first identifier;
the setting module is used for setting the first identifier matched in the first unit as a target identifier and setting the first unit matched in the first unit as a target unit when the first unit and the second unit which correspond to each other realize the matching of the first identifier;
the statistical module is used for determining the ranking value of the first identifier, positioned in the first unit where the target identifier is positioned, from the low order to the high order, and the total number of the first identifiers in all the first units which are ranked lower than the target unit;
and the first output module is used for summing the sorting values and the number and outputting a sum value.
5. The register matching apparatus of claim 4, wherein said apparatus further comprises:
and the second output module is used for outputting a corresponding unmatched preset value when the matching of the first unit and the second unit is not completed.
6. The register matching apparatus according to claim 4, wherein the comparison module comprises:
a first judging unit, configured to judge, for each corresponding first unit and second unit, whether the second unit has the first identifier;
a determining unit, configured to set the existing first identifier as a reference identifier and determine a reference relative position of the reference identifier in the second unit when the determination result of the first determining unit is existence;
a second judgment unit configured to judge whether the flag of the reference relative position in the first unit is a first flag; if the judgment result is yes, the first unit and the second unit are confirmed to realize the matching of the first identifier; and if the judgment result is negative, confirming that the first unit and the second unit cannot realize the matching of the first identifier.
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| CN108027767A (en) * | 2015-09-19 | 2018-05-11 | 微软技术许可有限责任公司 | Register read/write-in sequence |
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