CN115616372A - Fault injection test method and system - Google Patents

Fault injection test method and system Download PDF

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Publication number
CN115616372A
CN115616372A CN202211049234.6A CN202211049234A CN115616372A CN 115616372 A CN115616372 A CN 115616372A CN 202211049234 A CN202211049234 A CN 202211049234A CN 115616372 A CN115616372 A CN 115616372A
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tuple
tested
signal
circuit
fault injection
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闵鹏
谷飞扬
石俊
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XFusion Digital Technologies Co Ltd
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XFusion Digital Technologies Co Ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/2806—Apparatus therefor, e.g. test stations, drivers, analysers, conveyors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
    • G01R31/2812—Checking for open circuits or shorts, e.g. solder bridges; Testing conductivity, resistivity or impedance

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The application relates to a fault injection test method and a fault injection test system, which relate to the technical field of circuit test, in the application, the method is applied to a circuit to be tested, the circuit to be tested comprises a plurality of candidate tuples, each candidate tuple comprises a signal identifier, a signal sending device and a signal receiving device, and the method comprises the following steps: generating a target test case corresponding to the tuple to be tested of the circuit to be tested according to the preset corresponding relation between the candidate tuples and the test case elements; the tuple under test is one of a plurality of candidate tuples. And carrying out fault injection test on the circuit to be tested according to the target test case. According to the method, the test cases of the circuit to be tested can be automatically generated and automatically tested through the preset corresponding relation between the candidate tuples and the multiple test case elements, and the technical problems of long test period and low test efficiency of fault injection test are solved.

Description

Fault injection test method and system
Technical Field
The present application relates to the field of circuit testing technologies, and in particular, to a fault injection testing method and system.
Background
The fault injection test is a test technology, and can be understood as injecting a corresponding fault into a system to be tested according to a test case, acquiring response information to the fault, which is fed back by the system to be tested, and verifying and evaluating the system to be tested by analyzing the response information.
The system under test may be a circuit. Random failures of a circuit are unpredictable failures in the circuit design process, and the random failures can cause circuit failure. Among them, random failures such as device damage in a circuit, line short, and the like. By performing fault injection testing on the circuit, the response of the circuit to random faults can be verified and evaluated.
In the related art, a test case is designed manually, and a corresponding fault is injected manually according to the test case to complete the test. The corresponding fault injection mode of manual injection comprises but is not limited to welding flying wires, tweezers or air switch injection short-circuit faults, and the like. However, the manual design of the test case causes the technical problems of long test period and low test efficiency in the fault injection test process. Therefore, how to improve the testing efficiency becomes an urgent technical problem to be solved.
Disclosure of Invention
The embodiment of the application provides a fault injection testing method and system, which are used for solving the technical problems of long testing period and low testing efficiency of fault injection testing.
In order to achieve the above purpose, the embodiments of the present application adopt the following technical solutions:
in a first aspect, a fault injection test method is provided, which is applied to a circuit to be tested, where the circuit to be tested includes a plurality of candidate tuples, and each candidate tuple includes an identifier of a signal and a transmitting device and a receiving device of the signal, where the method includes: generating a target test case corresponding to the tuple to be tested of the circuit to be tested according to the preset corresponding relation between the candidate tuples and the test case elements; the target test case comprises a target test case element corresponding to the identification of the signal of the tuple to be tested, the sending device of the tuple to be tested and the receiving device of the tuple to be tested, and the tuple to be tested is one of a plurality of candidate tuples. According to the method, the test cases of the circuit to be tested can be automatically generated and automatically tested through the preset corresponding relation between the candidate tuples and the multiple test case elements, and the technical problems of long test period and low test efficiency of fault injection test are solved.
In one possible implementation manner of the first aspect, the test case element includes at least one of a failure mode, a failure injection manner, and a test criterion. The multiple test case elements corresponding to the tuple to be tested can be determined through the preset corresponding relation between the multiple candidate tuples and the multiple test case elements, the target test case is generated according to the multiple test case elements, the automatic generation of the test case of the circuit to be tested can be realized, and the technical problems of long test period and low test efficiency of fault injection test are solved.
In a possible implementation manner of the first aspect, the preset correspondence includes a first correspondence between a transceiver of a candidate tuple and a fault mode, a second correspondence between the transceiver of the candidate tuple and a fault injection manner, and a third correspondence between a signal category corresponding to the fault mode, the fault injection manner, and an identifier of a signal of the candidate tuple and a test criterion, where the transceiver is a transmitter or a receiver. Determining a target test case corresponding to the tuple to be tested of the circuit to be tested according to the preset corresponding relation between the candidate tuples and the test case elements, wherein the method comprises the following steps of: determining a target fault mode corresponding to the transceiver of the tuple to be tested based on the first corresponding relation; determining a target fault injection mode corresponding to the transceiver of the tuple to be tested based on the second corresponding relation; based on the third corresponding relation, determining a corresponding target test criterion according to a signal type, a target fault mode and a target fault injection mode corresponding to the identification of the signal of the tuple to be tested; and generating a target test case, wherein the target test case comprises a target fault mode, a target fault injection mode and a target test criterion. The multiple test case elements corresponding to the tuple to be tested can be determined through the preset corresponding relation between the multiple candidate tuples and the multiple test case elements, the target test case is generated according to the multiple test case elements, the automatic generation of the test case of the circuit to be tested can be realized, and the technical problems of long test period and low test efficiency of fault injection test are solved.
In a possible implementation manner of the first aspect, before generating a target test case corresponding to a tuple to be tested of a circuit to be tested according to a preset corresponding relationship between a plurality of candidate tuples and a plurality of test case elements, the method further includes: acquiring design information of a circuit to be tested, wherein the design information comprises signal transmission relations among different devices of the circuit to be tested; a plurality of candidate tuples is determined according to the signal transmission relation. The method comprises the steps of determining a plurality of candidate tuples according to signal transmission relations among different devices of a circuit to be tested, determining a test case corresponding to each candidate tuple according to a preset corresponding relation, determining a plurality of test cases of the circuit to be tested without analyzing the circuit to be tested according to personal experience by technicians, and solving the technical problems of long test period and low test efficiency of fault injection test.
In a possible implementation manner of the first aspect, determining a plurality of candidate tuples according to a signal transmission relationship includes: determining two devices with signal transmission relations in a circuit to be tested and N different signals transmitted between the two devices as N signal tuples; wherein N is an integer greater than or equal to 2; determining a plurality of candidate tuples according to the M signal tuples, wherein if a receiving device of a first signal tuple in the M signal tuples is a sending device of a second signal tuple and the influence of a signal in the first signal tuple and a signal in the second signal tuple on a circuit to be tested is the same, generating one candidate tuple according to the first signal tuple and the second signal tuple, wherein the sending device of the candidate tuple is the sending device of the first signal tuple, the receiving device of the candidate tuple is the receiving device of the second signal tuple, and M is an integer larger than N. Under the condition that the influence of signals in the signal tuples on the circuit to be tested is the same, the number of finally determined candidate tuples can be effectively reduced by combining the signal tuples, the test times of fault injection test are further effectively reduced, the test efficiency is improved, and the test time is saved.
In a possible implementation manner of the first aspect, the tuple to be tested satisfies one or more of the following conditions: the fault mode in the test case corresponding to the tuple to be tested is a preset fault mode; the signal category corresponding to the signal in the tuple to be tested is a preset signal category; the identification of the signal in the tuple to be detected is a preset identification; the receiving device in the tuple to be tested is a first appointed device; and/or the sending device in the tuple to be tested is the second designated device. According to the method, by setting the conditions for determining the tuple to be tested, each candidate tuple can be screened according to actual test requirements, the tuple to be tested is further determined from the candidate tuples, then the target test case elements corresponding to the identification of the signal of the tuple to be tested, the sending device of the tuple to be tested and the receiving device of the tuple to be tested are determined, the target test case is generated, fault injection test is performed in the circuit to be tested according to the target test case, and different test requirements are met.
In a possible implementation manner of the first aspect, the method further includes: and carrying out fault injection test on the circuit to be tested according to the target test case.
In a possible implementation manner of the first aspect, the performing, by the test case, a fault injection test on the circuit to be tested according to the target test case includes: controlling an injection device to inject a fault at a target fault injection position in a target fault injection mode in a target test case; the target fault injection position is the position indicated by the fault injection position information corresponding to the tuple to be detected; acquiring response information of a circuit to be tested after a fault is injected; and obtaining a test result of the circuit to be tested according to the response information and the target test criterion in the target test case. Therefore, by controlling the injection device, the fault can be automatically injected into the circuit to be tested in a fault injection mode in the target test case, and the fault does not need to be manually injected. Meanwhile, the injection device can be effectively moved through the power device, so that the injection device can perform fault injection at a target fault injection position in the circuit to be tested, and the efficiency is improved.
In a possible implementation manner of the first aspect, the fault injection position information corresponding to each candidate tuple is determined according to the identifier of the signal, the position coordinate information of each pin of the sending device, and the position coordinate information of each pin of the receiving device, where the fault injection position information is used to determine a fault injection position of the test case corresponding to the candidate tuple in the circuit to be tested. And according to the design information of the circuit to be tested, the fault injection position information corresponding to each candidate tuple can be quickly determined, so that a fault is injected at the target fault injection position indicated by the fault injection position information, and the fault injection test is completed.
In a second aspect, there is provided a fault injection testing apparatus, the apparatus comprising: the functional units for executing any one of the methods provided by the first aspect, wherein the actions performed by the respective functional units are implemented by hardware or by hardware executing corresponding software. For example, the fault injection test apparatus may include a test case determination unit and a test case execution unit. The test case determining unit is configured to execute a target test case corresponding to the tuple to be tested of the circuit to be tested according to the preset corresponding relation between the candidate tuples and the test case elements; the target test case comprises a target test case element corresponding to the identification of the signal of the tuple to be tested, the sending device of the tuple to be tested and the receiving device of the tuple to be tested, and the tuple to be tested is one of a plurality of candidate tuples. And the test case execution unit is configured to execute fault injection test on the circuit to be tested according to the target test case.
In a third aspect, a fault injection testing system is provided, including: a processor, a memory, a power device, and an injection device; the memory is used for storing computer instructions; a processor, coupled to the memory, for executing the computer instructions to implement any one of the methods provided by the first aspect; the power device is connected with the processor and the injection device and is used for controlling the power device to move under the control of the processor; and the injection device is used for injecting the fault at the target fault injection position in a target fault injection mode.
In a fourth aspect, there is provided a chip comprising: a processor and interface circuitry; the interface circuit is used for receiving the code instruction and transmitting the code instruction to the processor; a processor for executing code instructions to perform any of the methods provided by the first aspect above.
In a fifth aspect, a computer-readable storage medium is provided, which stores computer-executable instructions, and when the computer-executable instructions are executed on a computer, the computer is caused to perform any one of the methods provided by the first aspect.
In a sixth aspect, there is provided a computer program product comprising computer executable instructions which, when executed on a computer, cause the computer to perform any one of the methods provided in the first aspect above.
For technical effects brought by any one of the design manners in the second aspect to the sixth aspect, reference may be made to technical effects brought by different implementation manners in the first aspect, and details are not described here.
Drawings
Fig. 1 illustrates an application scenario diagram of a fault injection testing system provided in an embodiment of the present application;
FIG. 2 is a diagram illustrating an application scenario of another fault injection testing system provided in an embodiment of the present application;
fig. 3 is a schematic flowchart illustrating a fault injection testing method provided in an embodiment of the present application;
FIG. 4 is a circuit diagram of a circuit under test according to an embodiment of the present application;
fig. 5 is a schematic flowchart illustrating a fault injection testing method provided in an embodiment of the present application;
fig. 6 shows a block diagram of a fault injection testing apparatus according to an embodiment of the present application;
fig. 7 is a block diagram illustrating a structure of another fault injection testing apparatus according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In the description of the present application, the term "plurality" means two or more than two unless otherwise specified. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or multiple.
In addition, in order to facilitate clear description of technical solutions of the embodiments of the present application, in the embodiments of the present application, words such as "first" and "second" are used to distinguish identical items or similar items with substantially identical functions and actions. Those skilled in the art will appreciate that the terms "first," "second," and the like do not denote any order or importance, but rather the terms "first," "second," and the like do not denote any order or importance. Also, in the embodiments of the present application, words such as "exemplary" or "for example" are used to mean serving as examples, illustrations or illustrations. Any embodiment or design described herein as "exemplary" or "such as" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present relevant concepts in a concrete fashion for ease of understanding.
The fault injection test is a test technology, and can be understood as injecting a corresponding fault into a system to be tested according to a test case, acquiring response information to the fault, which is fed back by the system to be tested, and verifying and evaluating the system to be tested by analyzing the response information. The system under test may be a circuit under test, which may include a plurality of devices.
It is well known that there are two causes of circuit failure, one is a system failure and the other is a random failure, wherein the system failure is usually caused by an error in the design process or the manufacturing process of the circuit, and the system failure can be handled through simulation-based verification and formal property verification. The random fault is an unpredictable fault in the circuit design process, and can be faults such as device damage, line short circuit and the like in the circuit. By performing fault injection testing on the circuit, the response of the circuit to random faults can be verified and evaluated.
In the related art, a test case is designed manually, that is, a person skilled in the art analyzes a circuit to be tested and designs a corresponding test case according to experience. The test case is a description of a test task performed on a test target, and embodies a test scheme, a method, a technology and a strategy. And then, the technician manually injects corresponding faults into the circuit to be tested according to the designed test case to complete the test. The fault injection mode includes but is not limited to welding flying wires, tweezers or air switch injection short circuit fault, and using functional electric soldering iron to break welding and the like.
However, for different circuits to be tested, manual work is required to design and execute test cases respectively, a large amount of time is consumed, the automation degree is low, and the fault injection test process has the technical problems of long test period and low test efficiency. Therefore, how to improve the testing efficiency is an urgent technical problem to be solved. On one hand, the design of the test case depends on the personal experience of the technical personnel, so that the problem of being not objective and accurate is also solved. On the other hand, the execution of the test case requires manual operation of a technician, which causes the problems of less test times, less covered samples and great difficulty in repeated tests in a limited time.
In view of this, the present application provides a fault injection testing method, which is applied to a circuit to be tested, where the circuit to be tested includes a plurality of candidate tuples, where each candidate tuple is determined according to design information of the circuit to be tested, and each candidate tuple includes a sending device, a receiving device, and an identifier of a signal sent by the sending device to the receiving device, where the sending device has a signal transmission relationship in the circuit to be tested. The method comprises the following steps: generating a target test case corresponding to a tuple to be tested of a circuit to be tested according to a preset corresponding relation between a plurality of candidate tuples and a plurality of test case elements, wherein the target test case comprises a target test case element corresponding to an identification of a signal of the tuple to be tested, a sending device of the tuple to be tested and a receiving device of the tuple to be tested, and the tuple to be tested is one of the candidate tuples. And carrying out fault injection test on the circuit to be tested according to the target test case. According to the method, the test cases of the circuit to be tested can be automatically generated and automatically tested through the preset corresponding relation between the candidate tuples and the multiple test case elements, and the technical problems of long test period and low test efficiency of fault injection test are solved.
The method provided by the embodiment of the application is explained in the following with the accompanying drawings of the specification.
Fig. 1 is a diagram of an application scenario of a fault injection testing system according to an embodiment of the present application, as shown in fig. 1, including a fault injection testing apparatus 110 and a circuit under test 120.
The fault injection testing device 110 is configured to generate a target test case corresponding to a tuple to be tested of the circuit to be tested according to a preset corresponding relationship between a plurality of candidate tuples and a plurality of test case elements, where the target test case includes a target test case element corresponding to an identifier of a signal of the tuple to be tested, a sending device of the tuple to be tested, and a receiving device of the tuple to be tested, and perform a fault injection test on the circuit to be tested 120 according to the target test case.
The circuit to be tested 120 may be a single board printed with the circuit to be tested, and the circuit to be tested 120 may be applied to an electrical and/or electronic system in the technical field of a server, the technical field of communication, the technical field of industrial automation, or the technical field of automobiles, for example, the circuit to be tested is a server motherboard for implementing a computing function or a resource management function of the server. The circuit to be tested comprises a plurality of candidate tuples, and each candidate tuple comprises a signal, a transmitting device and a receiving device of the signal. Optionally, the candidate tuples are determined according to design information of the circuit to be tested, where the design information includes signal transmission relationships between different devices in the circuit to be tested.
The test case is a description of a test task of a test object, and embodies a test scheme, a method, a technology and a strategy. In different application scenarios, the content contained in the test case is different. In this embodiment, the test case specifically includes a plurality of test case elements having a preset corresponding relationship with the tuple to be tested, for example, the test case elements include at least one of a failure mode, a failure injection mode, and a test criterion. The preset corresponding relation comprises a first corresponding relation between a transceiver of the candidate tuple and a fault mode, a second corresponding relation between the transceiver of the candidate tuple and a fault injection mode, and a third corresponding relation between a signal category corresponding to the fault mode, the fault injection mode and the identification of the signal of the tuple to be tested and the test criterion, wherein the transceiver of the candidate tuple is a transmitter or a receiver of the candidate tuple.
In a possible implementation manner, the test case elements further include PIN (PIN) fault information of a receiving device or a sending device of the tuple to be tested, a system detection scheme corresponding to the identifier of the tuple to be tested, and a prefabrication condition corresponding to the identifier of the tuple to be tested, where the composition of the test case including the test case elements is not particularly limited, and can be adjusted according to actual requirements.
The failure mode may also be referred to as a failure mode, and the failure mode is a manifestation of a failure, which may be understood as a failure of any device in the circuit under test or a failure of any signal in the circuit under test. For example, in the case that a crystal oscillator exists in a device included in a circuit to be tested, the failure mode may be that the crystal oscillator has frequency deviation or has no output. In the case where the circuit to be tested outputs the first signal, the failure mode may also be that the first signal cannot be successfully output.
The fault injection mode comprises welding flying wires or inserting probes so as to realize the injection of short-circuit faults in the circuit to be tested.
The test criterion can be understood as a test judgment basis. Namely the predicted reaction of the circuit to be tested after the circuit to be tested injects the fault corresponding to the test case.
In an implementation manner, referring to fig. 2, fig. 2 is an application scenario diagram of another fault injection test system, and on the basis of fig. 1, the fault injection test system further includes an injection device 121, where the injection device 121 is configured to inject a fault into the circuit under test 120 according to a target test case.
In another implementation manner, the fault injection testing system further includes a power device 122, where the power device 122 is connected to the injection device 121, and the power device 122 is configured to move the injection device 121 to a corresponding position according to the target test case, so that the injection device 121 injects the fault at the position corresponding to the target test case in the circuit to be tested. For example, the power device 122 may be a robotic arm, and the injection device 121 may be a probe secured to the robotic arm. The mechanical arm moves, so that the probe can be inserted into a position corresponding to a target test case in the circuit to be tested, the circuit to be tested is short-circuited at the position, and fault injection is realized.
In another implementation, the fault injection testing system further includes a power supply device 123, where the power supply device 123 is electrically connected to the power device 122, and the power supply device 123 is configured to supply power to the power device 122.
In another implementation manner, the fault injection testing system further includes an operation table 124, the operation table 124 is disposed below the power device 122, and the operation table 124 is used for placing the circuit under test 120, so as to fix and position the circuit under test 120, so that the power device 122 moves to a position corresponding to a target test case, and the injection device 121 injects a fault into the circuit under test on the operation table 124.
In another implementation, the fault injection test system further includes a heat sink 125, and the heat sink 125 is used to provide heat dissipation for the power device 122, so as to prevent the power device 122 or the circuit under test 120 from being damaged due to over-high temperature.
The fault injection testing device 110 is further configured to obtain response information fed back by the circuit to be tested after the injecting device 121 injects the fault corresponding to the target test case into the circuit to be tested, and determine a fault injection testing result corresponding to the test case according to the response information and the corresponding testing criterion in the target test case.
The fault injection testing device 110, the injection device 121, the power device 122, the power supply device 123 and the heat dissipation device 125 may be integrated into one electronic device, or may be separately disposed in different electronic devices, and the arrangement manner of the fault injection testing device 110, the injection device 121, the power device 122, the power supply device 123 and the heat dissipation device 125 is not particularly limited.
The method provided by the embodiment of the present application is described below with reference to the fault injection testing system shown in fig. 1. Fig. 3 is a flowchart of a fault injection testing method according to an embodiment of the present application, where the method is applied to a circuit to be tested. As shown in fig. 3, the fault injection testing method for a circuit under test may include:
s301: the method comprises the steps of obtaining design information of a circuit to be tested, wherein the design information comprises signal transmission relations among different devices of the circuit to be tested.
The design information may include, but is not limited to, a source code file generated in the design process of the circuit to be tested, for example, the source code file may be an integrated circuit diagram of the circuit to be tested, and design information such as device electrical connection relationship topology information and signal network topology information between a plurality of devices in the circuit to be tested may be acquired from the integrated circuit diagram. The device electrical connection relation topology information is used for representing the connection relation among all devices in the circuit to be tested, and the signal network topology information is used for representing signals transmitted among all devices in the circuit to be tested. And further, the signal transmission relation among different devices in the circuit to be tested can be obtained according to the device electrical connection relation topology information and the signal network topology information.
S302: a plurality of candidate tuples is determined according to the signal transmission relation. Each candidate tuple includes an identification of the signal and a transmitting device and a receiving device of the signal.
That is to say, each candidate tuple includes a set of devices having a signal transmission relationship in the circuit to be tested and an identifier of a signal, that is, a sending device and a receiving device, where the sending device is configured to send a signal to the receiving device, and the receiving device is configured to receive the signal sent by the sending device, where the receiving device or the sending device of the tuple to be tested may also be referred to as a transceiver of the tuple to be tested.
It should be noted that one signal may be transmitted or multiple signals may be transmitted between the transmitting device and the receiving device in the same group of devices. For the same group of transmitting devices and receiving devices, if a plurality of signals are transmitted between the transmitting devices and the receiving devices, and each signal has a corresponding identifier, the group of devices can be determined as a plurality of candidate tuples, and each candidate tuple comprises the identifier of the signal and the transmitting device and the receiving device of the signal. In the implementation manner, the electrical connection relationship between any two devices in the circuit to be tested can be determined through the device electrical connection relationship topology information, and the signals transmitted between every two devices having a connection relationship in the circuit to be tested can be determined through the signal network topology information, so that any two devices having a connection relationship are determined as a group of devices, one of the devices is a sending device, the other device is a receiving device, and the sending device is used for sending signals to the receiving device.
For example, referring to fig. 4, fig. 4 is a circuit diagram of a circuit to be tested according to an embodiment of the present application, where the circuit to be tested includes three devices, and the identifiers of the three devices are respectively U 1 、U 2 And U 3 Determining three candidate tuples according to the design information, wherein the three candidate tuples are respectively a first candidate tuple, a second candidate tuple and a third candidate tuple, and the identifier of a transmitting device of the first candidate tuple is U 1 Identification of the receiving device of the first candidate tuple is U 2 Transmitting device U 1 For feeding to receiving devices U 2 The identity of the transmitting device transmitting the first signal and the second candidate tuple is U 2 And the identification of the receiving device of the second candidate tuple is U 3 Transmitting device U 2 For feeding to receiving devices U 3 The second signal is transmitted, and the identifier of the transmitting device of the third candidate tuple is U 1 Identification U of the receiving device of the third candidate tuple 3 Transmitting device U 1 For feeding to receiving devices U 3 A third signal is transmitted. It should be noted that, according to the difference of signals transmitted between two devices, the same device in the circuit to be tested may be a transmitting device in one candidate tuple, and may also be a receiving device of another candidate tuple. For example, the above-mentioned mark U 2 The corresponding device is both a receiving device in the first candidate tuple and a sending device in the second candidate tuple.
However, in the circuit under test, the same signal or a signal having the same effect may be transferred between two or more devices in succession, that is, one transmitting device transmits a signal, which has the effect of improving the quality of the signal, to a receiving device, which in turn transmits the signal to another receiving device. For the fault injection test, because the influence of the signal transmitted between the two candidate tuples on the circuit to be tested is the same, no matter the fault of the signal short circuit is injected into any one of the two candidate tuples, the fault mode is the same for the circuit to be tested. Therefore, redundancy exists in the fault injection test due to a large number of candidate tuples with the same signals, the test frequency of the fault injection test is increased, and the test efficiency is low.
In one implementation, the step S302 includes: determining two devices with a signal transmission relation in a circuit to be tested and N different signals transmitted between the two devices as N signal tuples; wherein N is an integer greater than or equal to 2; determining a plurality of candidate tuples according to the M signal tuples, wherein if a receiving device of a first signal tuple in the M signal tuples is a sending device of a second signal tuple and the influence of a signal in the first signal tuple and a signal in the second signal tuple on a circuit to be tested is the same, a candidate tuple is generated according to the first signal tuple and the second signal tuple, the sending device of the candidate tuple is a sending device of the first signal tuple, the receiving device of the candidate tuple is a receiving device of the second signal tuple, and M is an integer greater than N.
Illustratively, as shown in fig. 4, two signal tuples are determined according to the design information, namely a first signal tuple and a second signal tuple, and the identifier of the transmitting device of the first signal tuple is U 1 The identification of the receiving device of the first signal tuple is U 2 Transmitting device U 1 For feeding to receiving devices U 2 Transmitting a first signal, the second signal tuple comprising a transmitting device U 2 And a receiving device U 3 Transmitting device U 2 For feeding to receiving devices U 3 A second signal is transmitted. Wherein the device U 2 For a series resistance R, device U in the circuit to be tested 2 For lifting past the device U 2 The signal quality of the first signal. Device U 2 The effect of the first signal is not changed, so the receiving device of the first signal tuple is the sending device of the second signal tuple, and the signal in the first signal tuple and the signal in the second signal tuple have the same influence on the circuit to be tested. In this case, the sum of the first signal tuplesA second signal tuple generating a candidate tuple whose transmitting device is identified by U 1， The identity of the receiving device of the candidate tuple is U 3 。
By the above, under the condition that signals in a plurality of signal tuples have the same effect, a candidate tuple is obtained based on the plurality of signal tuples, redundancy can be effectively avoided, the test times of fault injection test are further effectively reduced, the test efficiency is improved, and the test time is saved.
In a possible implementation manner, generating a candidate tuple according to the first signal tuple and the second signal tuple further includes: an identification of the signal of the first signal tuple and an identification of the signal of the second signal tuple are added to the candidate tuple. So that the operator can quickly find the candidate tuple generated from the first signal tuple and the second signal tuple according to the identification of the signal of the first signal tuple and the identification of the signal of the second signal tuple.
In the implementation manner, in the design information of the circuit to be tested, the device electrical connection relationship topology information among the multiple devices and the signal network topology information are usually in the form of a data table, and a plurality of signal tuples can be obtained by processing the data table, and then each signal tuple is sequentially analyzed to merge the signal tuples to generate the candidate tuples.
However, when the device electrical connection relation topology information among the multiple devices in the design information of the circuit to be tested and the signal network topology information are not in the form of a data table but in the form of a topology diagram, the integrated circuit diagram of the circuit to be tested is processed through a diagram traversal algorithm, multiple signal tuples can be directly obtained, then each signal tuple is sequentially analyzed, and the signal tuples are combined to generate candidate tuples. Wherein, the graph traversal algorithm may be a directed graph traversal algorithm. For example, each device included in a circuit to be tested is sequentially identified from an integrated circuit diagram of the circuit to be tested according to a traversal algorithm, then a plurality of groups of devices are determined according to the identified devices, one group of devices includes a sending device and a receiving device, and under the condition that the influence of signals transmitted between any two groups of devices on the circuit to be tested is the same, a candidate tuple is obtained according to signal tuples corresponding to the two groups of devices.
Based on this, in one implementation, the method further includes:
and determining the device information of each device from the design information, and if the device information exists in the database, determining the device corresponding to the device information as a candidate device. And determining a plurality of candidate tuples according to the signal transmission relation between different candidate devices and other devices, wherein at least one of a transmitting device or a receiving device in each candidate tuple is a candidate device.
The device information may be a preset code corresponding to each device, or may also be a name of each device, or information describing a function of the device in the circuit structure, and the device corresponding to the device information may be determined from the circuit structure through the device information. In this implementation, the device information may be obtained from a bill of materials (BOM) table of the circuit under test.
In the above implementation manner, the preset device is a device capable of causing a fault to the circuit structure, and when one device in the circuit structure is not the preset device, it indicates that the device does not cause a fault to the circuit structure. It is also understood that devices stored in the database are devices of a first type and devices not stored in the database are devices of a second type. It can also be understood that the predetermined device is a first type device, and the non-predetermined device is a second type device. Therefore, according to the device information of each device in the circuit to be tested, the devices in the circuit to be tested are divided into the first type devices (the candidate devices belong to the first type devices) or the second type devices, and the second type devices are screened out, so that the number of determined candidate tuples can be effectively reduced, and unnecessary tests are avoided.
It should be noted that, in S301 to S302, the candidate tuple is determined based on the design information of the circuit to be tested, and for a specific implementation manner of determining the candidate tuple, the determination manner of the candidate tuple of the circuit to be tested is not limited here.
S303: and acquiring a preset corresponding relation between the candidate tuples and the test case elements.
The target test case comprises target test case elements corresponding to the identification of the signal of the tuple to be tested, the sending device of the tuple to be tested and the receiving device of the tuple to be tested, and the tuple to be tested is one of a plurality of candidate tuples.
In one possible implementation, the tuple under test satisfies one or more of the following conditions: the failure mode in the test case corresponding to the tuple to be tested is a preset failure mode, the identifier of the signal in the tuple to be tested is a preset identifier, the receiving device in the tuple to be tested is a first designated device, and/or the sending device in the tuple to be tested is a second designated device. For example, according to the following table 3, candidate tuples satisfying the condition may be used as tuples to be tested, and test cases corresponding to the tuples to be tested may be used as target test cases.
In another implementation, the tuple under test satisfies the following condition: and the type of the signal in the tuple to be tested is a preset type, the candidate tuple meeting the condition is used as the tuple to be tested, and the test case corresponding to the tuple to be tested is used as the target test case. In the above implementation manner, a technician may input a condition to the fault injection testing apparatus 110, and the fault injection testing apparatus 110 selects, in response to the condition input by the technician, a candidate tuple that satisfies the condition as a tuple to be tested from all candidate tuples, and uses a test case generated according to the tuple to be tested as a target test case.
According to the method, the condition for determining the tuple to be tested is set, each candidate tuple can be screened according to actual test requirements, the tuple to be tested is further determined from the candidate tuples, then the target test case elements corresponding to the identification of the signal of the tuple to be tested, the sending device of the tuple to be tested and the receiving device of the tuple to be tested are determined, the target test case is generated according to the target test case elements, fault injection test is carried out in the circuit to be tested on the basis of the target test case, and different test requirements are met.
In a possible implementation manner, the test case element includes at least one of a failure mode, a failure injection manner, and a test criterion, the preset correspondence includes a first correspondence between a transceiver of a candidate tuple and the failure mode, a second correspondence between the transceiver of the candidate tuple and the failure injection manner, and a third correspondence between a signal type corresponding to an identifier of a signal of the failure mode, the failure injection manner, and the tuple to be tested and the test criterion, where the transceiver of the candidate tuple is a transmitter or a receiver of the candidate tuple.
A technician may determine, based on design information of the sample circuit, a failure mode corresponding to a device identifier of each device in the multiple sample circuits, to obtain a first corresponding relationship between the device identifier of each device and the failure mode, determine, based on the design information of the sample circuit, a failure injection manner corresponding to each device in the multiple sample circuits, to obtain a second corresponding relationship between the device identifier of each device and the failure injection manner, and may also obtain, based on the design information of the sample circuit, a third corresponding relationship between a signal type corresponding to the failure mode, the failure injection manner, and an identifier of a signal of a to-be-tested tuple, and a test criterion. It should be noted that the sample circuit is a single board printed with a circuit to be tested, and the sample circuit may be the same as or different from the application field of the circuit to be tested. For example, a circuit including a plurality of devices and having a signal transmission relationship between the plurality of devices may be used as the sample circuit, and the sample circuit is not particularly limited herein.
S304, generating a target test case corresponding to the tuple to be tested of the circuit to be tested according to the preset corresponding relation between the candidate tuples and the test case elements.
The target test case comprises a target test case element corresponding to an identifier in a tuple to be tested and a sending device and a receiving device of a signal, and the tuple to be tested is one of a plurality of candidate tuples.
In a possible implementation manner, the step S304 includes: determining a target fault mode corresponding to the transceiver of the tuple to be tested based on the first corresponding relation; determining a target fault injection mode corresponding to the transceiver of the tuple to be tested based on the second corresponding relation; based on the third corresponding relation, determining a target test criterion according to the signal type, the target fault mode and the target fault injection mode corresponding to the identification of the signal of the tuple to be tested; and generating a target test case, wherein the target test case comprises a target fault mode, a target fault injection mode and a target test criterion.
In the foregoing implementation manner, the preset correspondence may be stored in a database in the form of a data table, for example, referring to table 1, table 1 is a preset correspondence table provided in this embodiment of the present application, and includes a fault mode corresponding to a device identifier of each device and a device in a plurality of sample circuits, and a fault injection manner corresponding to a device identifier of each device and a device in a plurality of sample circuits, and it can also be understood that table 1 below includes a first preset relationship and a second preset relationship.
TABLE 1
Device identification Fault PIN Failure mode Fault injection method
U 1 PIN01 Mode a Mode a
U 3 PIN02 B mode Mode B
Referring to table 2, table 2 is a preset correspondence table provided in this embodiment, and includes test criteria corresponding to fault modes, fault injection manners, and signal types in multiple sample circuits, and it can also be understood that the following table 2 includes a third preset relationship.
TABLE 2
Class of signal Failure mode Fault injection method Test criteria
Class A Mode a Mode a Test criterion d
Class B B mode Mode B Test criterion D
Illustratively, if the tuple to be tested is the candidate tuple A, the device identifier of the sending device of the tuple to be tested is U 1 Determining the sending of the tuple A to be tested in the circuit to be tested according to the table 1 under the scene of performing fault injection test on the circuit A to be testedDevice identification U of device 1 The corresponding target failure mode is a-mode, the target failure injection mode is a-mode, and the obtained results are shown in table 3. TABLE 3
Figure BDA0003823072480000091
In the above example, the identifier of the signal of the candidate tuple a is 001, the signal class corresponding to the identifier 001 of the signal is class a, and with reference to the table 2, based on the third preset relationship, the target signal class of the tuple to be tested is class a, the target fault mode a mode and the target fault injection mode are a modes, and the target test criterion corresponding to the tuple a to be tested is the test criterion d. And generating a target test case, wherein the target test case comprises a target fault mode which is an a mode, a target fault injection mode which is an a mode and a target test criterion which is a test criterion d.
It should be noted that, in the test case generation method provided in the embodiment of the present application, a part or all of the steps in S301 to S304 may constitute a test case generation method, where the test case generation method may determine, through a preset corresponding relationship between a plurality of candidate tuples and a plurality of test case elements, a plurality of test case elements corresponding to tuples to be tested, and generate a target test case according to the plurality of test case elements, so as to implement automatic generation of a test case for a circuit to be tested, and solve the technical problems of long test period and low test efficiency of fault injection test.
The embodiment of the present application further provides a fault injection testing method, which at least includes the following step S305 on the basis of the steps S301 to S304. And S305, performing fault injection test on the circuit to be tested according to the target test case.
In an implementation manner, referring to fig. 5, the candidate tuple corresponds to fault injection location information, the test case includes a fault injection manner and a test criterion, and the step S305 includes:
s305a, controlling an injection device to inject a fault at a target fault injection position in a fault injection mode in a target test case; and the target fault injection position is the position indicated by the fault injection position information corresponding to the tuple to be tested.
The test criterion can be understood as a test criterion. Namely the predicted reaction of the circuit to be tested after the circuit to be tested injects the fault corresponding to the test case. For example, the preset reaction after the fault is injected into the circuit to be tested is as follows: and after the circuit to be tested has the fault K, the circuit to be tested feeds back fault information corresponding to the fault K. The judgment basis is as follows: and after the circuit to be tested is injected with the fault K, whether fault information corresponding to the fault K is fed back or not is judged.
In one implementation, the fault injection position is determined according to the fault injection position information of the target test case, and the power device 122 is controlled to operate so that the injection device 121 is aligned with the target fault injection position. Then, the injection device 121 performs fault injection at a target fault injection position of the circuit to be tested in a fault injection manner corresponding to the target test case, in this implementation manner, the power device 122 may be a mechanical arm, and the injection device 121 may be a probe fixed on the mechanical arm. The mechanical arm moves, so that the probe can be inserted into a target fault injection position of the circuit to be tested, the circuit to be tested is short-circuited at the target fault injection position, and fault injection is realized.
In one implementation manner, the fault injection position information corresponding to each candidate tuple is determined according to a signal, position coordinate information of each pin of the sending device, and position coordinate information of each pin of the receiving device, where the fault injection position information is used to determine a fault injection position of a test case corresponding to the candidate tuple in the circuit to be tested.
In the above implementation manner, the position coordinate information of each pin of the transmitting device and the position coordinate information of each pin of the receiving device may be obtained from the design information of the circuit to be tested. And according to the design information of the circuit to be tested, the fault injection position information corresponding to each candidate tuple can be quickly determined, so that a fault is injected at the target fault injection position indicated by the fault injection position information, and the fault injection test is completed.
S305b, acquiring response information of the circuit to be tested after the fault is injected.
In the implementation manner, a fault is injected in a target fault injection position of a circuit to be tested through the power device 122 and the injection device 121, and meanwhile, after the fault is injected, the fault injection testing device 110 obtains response information of the circuit to be tested from an output end of the circuit to be tested, where the response information is an actual reaction of the circuit to be tested after the fault is injected, for example, the response information may be system work log information of the circuit to be tested after the fault is injected in the circuit to be tested, the system work log information includes information representing a working state of the circuit to be tested, and the system work log information may also include information representing whether the circuit to be tested can implement its function and how to implement its function. According to the system working log information of the circuit to be tested after fault injection, whether the safety mechanism of the circuit to be tested can successfully identify and feed back the fault occurring in the circuit to be tested can be determined.
S305c, obtaining a test result of the circuit to be tested according to the response information and the test criterion in the target test case.
In the implementation manner, the actual reaction of the circuit to be tested after the fault is injected can be determined according to the response information, the expected reaction of the circuit to be tested after the fault is injected can be determined according to the test criterion, and the test result is that the target test case is successfully tested under the condition that the actual reaction is consistent with the expected reaction. In the case that the actual reaction and the predicted reaction are not consistent, the test result is that the target test case fails.
Therefore, the fault injection device can be controlled to automatically inject the fault into the circuit to be tested in the fault injection mode in the target test case, and the fault does not need to be manually injected. Meanwhile, the injection device can be effectively moved through the power device, so that the injection device can perform fault injection at a target fault injection position in the circuit to be tested, and the efficiency is improved.
In one implementation, after each fault injection test, the test result of the obtained fault injection test is stored in a fault injection test record. It can also be understood that the record of the fault injection test further includes a label associated with each candidate tuple in the record, and each label includes other information describing the fault injection test, for example, test time of the fault injection test, information describing a target test case, a fault mode corresponding to the target test case of the fault injection test, and the like. Each test result stored in the fault injection test record may also be assigned a unique identifier, for example, a numerical ID, which may be used to characterize the order in which each target test case is executed. An operator may quickly determine test results of previously tested fault injection tests from multiple dimensions in a log of fault injection tests.
In one implementation, the fault injection test records may be stored in a database to allow an operator to quickly search and analyze the fault injection test results.
S301-S305, generating a target test case corresponding to the tuple to be tested of the circuit to be tested according to the preset corresponding relation between the candidate tuples and the test case elements; the tuple under test is one of a plurality of candidate tuples. And carrying out fault injection test on the circuit to be tested according to the target test case. On one hand, because the test case is automatically generated, the personal experience of technicians is not needed, and the objectivity and the accuracy of the test case can be improved. On the other hand, because the test case is automatically executed, the manual operation of technicians is not needed, and the technical problems of long test period and low test efficiency of fault injection test in the related technology can be solved.
It should be noted that, since the circuit under test is formed by electrically connecting a plurality of devices to each other, the plurality of devices can be divided into two types, wherein one type is a device (hereinafter referred to as a first type device) which can affect the circuit under test to realize its function when it fails, and the other type is a device (hereinafter referred to as a second type device) which can not affect the circuit under test to realize its function when it fails. When a plurality of candidate tuples are determined, at least one of a sending device and a receiving device in the candidate tuples is a first-type device, and since the second-type device cannot influence a circuit to be tested, fault injection testing of the candidate tuples, in which the receiving device and the sending device are the second-type devices, is meaningless, and only the frequency of the fault injection testing is increased, the testing cost is increased, and the testing efficiency is influenced.
The above description has been directed primarily to the embodiments of the present application from a methodological perspective. It is to be understood that the fault injection test apparatus includes at least one of a hardware structure and a software module corresponding to each function in order to implement the above-described functions. Those of skill in the art will readily appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiment of the present application, the fault injection testing apparatus may be divided into the functional units according to the above method example, for example, each functional unit may be divided corresponding to each function, or two or more functions may be integrated into one processing unit. The integrated unit may be implemented in the form of hardware, or may also be implemented in the form of a software functional unit. It should be noted that, in the embodiment of the present application, the division of the unit is schematic, and is only one logic function division, and when the actual implementation is realized, another division manner may be provided.
For example, fig. 6 shows a block diagram of a fault injection testing apparatus according to an exemplary embodiment of the present application. The fault injection test device comprises:
a test case determining unit 610 configured to execute a target test case corresponding to a tuple to be tested of the circuit to be tested according to a preset corresponding relationship between the candidate tuples and the test case elements; the target test case comprises target test case elements corresponding to the identification of the signal of the tuple to be tested, the sending device of the tuple to be tested and the receiving device of the tuple to be tested, and the tuple to be tested is one of a plurality of candidate tuples;
and the test case execution unit 620 is configured to execute the fault injection test on the circuit to be tested according to the target test case.
For example, in conjunction with FIG. 3, the test case determination unit 610 may be configured to perform steps 301-304 shown in FIG. 3, and the test case execution unit 620 may be configured to perform step 305 shown in FIG. 3.
Optionally, the test case element includes at least one of a failure mode, a failure injection mode, and a test criterion.
Optionally, the preset correspondence includes a first correspondence between a transceiver of the candidate tuple and the fault mode, a second correspondence between the transceiver of the candidate tuple and the fault injection mode, and a third correspondence between the signal category corresponding to the identifier of the signal of the fault mode, the fault injection mode, and the candidate tuple and the test criterion, where the transceiver is a transmitter or a receiver. The test case determining unit 610 is specifically configured to determine, based on the first corresponding relationship, a target failure mode corresponding to the transceiver device of the tuple to be tested; determining a target fault injection mode corresponding to the transceiver of the tuple to be tested based on the second corresponding relation; determining a target test criterion according to the signal type, the target fault mode and the target fault injection mode corresponding to the identifier of the signal of the tuple to be tested based on the third corresponding relation; and generating a target test case, wherein the target test case comprises a target fault mode, a target fault injection mode and a target test criterion.
Optionally, before generating the target test case corresponding to the tuple to be tested of the circuit to be tested according to the preset corresponding relationship between the multiple candidate tuples and the multiple test case elements, the test case determining unit 610 is further configured to: acquiring design information of a circuit to be tested, wherein the design information comprises signal transmission relations among different devices of the circuit to be tested; a plurality of candidate tuples is determined according to the signal transmission relationship.
Optionally, the test case determining unit 610 is further configured to: determining two devices with a signal transmission relation in a circuit to be tested and N different signals transmitted between the two devices as N signal tuples; wherein N is an integer greater than or equal to 2; determining a plurality of candidate tuples according to the M signal tuples, wherein if a receiving device of a first signal tuple in the M signal tuples is a sending device of a second signal tuple and the influence of a signal in the first signal tuple and a signal in the second signal tuple on a circuit to be tested is the same, generating one candidate tuple according to the first signal tuple and the second signal tuple, wherein the sending device of the candidate tuple is the sending device of the first signal tuple, the receiving device of the candidate tuple is the receiving device of the second signal tuple, and M is an integer larger than N.
Optionally, the tuple to be tested satisfies one or more of the following conditions: the fault mode in the test case corresponding to the tuple to be tested is a preset fault mode; the signal category corresponding to the signal in the tuple to be detected is a preset signal category; the identification of the signal in the tuple to be detected is a preset identification; the receiving device in the tuple to be tested is a first appointed device; and/or the sending device in the tuple to be tested is the second designated device.
Optionally, the candidate tuple corresponds to fault injection position information, the test case includes a fault injection mode and a test criterion, and the test case execution unit 620 is specifically configured to: controlling an injection device to inject a fault at a target fault injection position in a target fault injection mode in a target test case; the target fault injection position is the position indicated by the fault injection position information corresponding to the tuple to be detected; acquiring response information of a circuit to be tested after a fault is injected; and obtaining a test result of the circuit to be tested according to the response information and the target test criterion in the target test case. For example, in conjunction with FIG. 5, the test case execution unit 620 may be used to perform steps 305 a-305 c as shown in FIG. 5.
Optionally, the fault injection position information corresponding to each candidate tuple is determined according to the identifier of the signal, the position coordinate information of each pin of the sending device, and the position coordinate information of each pin of the receiving device, where the fault injection position information is used to determine a fault injection position of the test case corresponding to the candidate tuple in the circuit to be tested.
For the detailed description of the above alternative modes, reference may be made to the foregoing method embodiments, which are not described herein again. In addition, for the explanation and the description of the beneficial effects of any fault injection testing apparatus provided above, reference may be made to the corresponding method embodiment described above, and details are not repeated.
By way of example, in conjunction with fig. 7, the functions implemented by part or all of the test case determination unit 610 and the test case execution unit 620 in the fault injection testing apparatus may be implemented by the processor 710 in fig. 7 executing the program code in the memory 720 in fig. 7.
Fig. 7 is a block diagram illustrating a structure of a fault injection testing apparatus according to an exemplary embodiment of the present application. The computer device can be an electronic device such as a smart phone, a tablet computer, an electronic book, a portable personal computer, an intelligent wearable device and the like. The computer device in the present application may comprise one or more of the following components: a processor 710, a memory 720.
Processor 710 may include one or more processing cores. The processor 710 connects various parts within the overall terminal using various interfaces and lines, performs various functions of the terminal and processes data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 720 and calling data stored in the memory 720. Alternatively, the processor 710 may be implemented in hardware using at least one of Digital Signal Processing (DSP), field-programmable gate array (FPGA), and Programmable Logic Array (PLA). The processor 710 may integrate one or more of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a modem, and the like. Wherein, the CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing the content required to be displayed by the screen 730; the modem is used to handle wireless communications. It is understood that the modem may not be integrated into the processor 710, but may be implemented by a communication chip.
Memory 720 may include Random Access Memory (RAM) or read-only memory (ROM). Optionally, the memory 720 includes a non-transitory computer-readable medium. The memory 720 may be used to store instructions, programs, code sets, or instruction sets. The memory 720 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for implementing at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the above method embodiments, and the like, and the operating system may be an Android (Android) system (including an Android system depth development-based system), an IOS system developed by apple inc (including an IOS system depth development-based system), or other systems. The data storage area can also store data (such as a phone book, audio and video data, chat record data) created by the terminal in use and the like.
In addition, those skilled in the art will appreciate that the configurations of the computer apparatus shown in the above-described figures are not meant to be limiting, and that the computer apparatus may include more or fewer components than those shown, or some of the components may be combined, or a different arrangement of components. For example, the terminal further includes a radio frequency circuit, a shooting component, a sensor, an audio circuit, a wireless fidelity (WiFi) component, a power supply, a bluetooth component, and other components, which are not described herein again.
The embodiment of the present application further provides a fault injection testing system, including: a processor, a memory, a power device, and an injection device; the memory is used for storing computer instructions; the processor is connected with the memory and used for executing computer instructions to realize the methods provided by the various embodiments; the power device is connected with the processor and the injection device and is used for controlling the power device to move under the control of the processor; and the injection device is used for injecting the fault at the target fault injection position in a target fault injection mode.
The embodiment of the present application further provides a computer-readable storage medium, where at least one computer instruction is stored in the computer-readable storage medium, and the at least one computer instruction is loaded and executed by a processor to implement the fault injection testing method according to the above embodiments. For the explanation and the description of the beneficial effects of any of the computer-readable storage media provided above, reference may be made to the corresponding embodiments described above, and details are not repeated here.
The embodiment of the application also provides a chip. The chip is integrated with a control circuit and one or more ports for realizing the functions of the fault injection testing device. Optionally, the functions supported by the chip may refer to the above, and are not described herein again. Those skilled in the art will appreciate that all or part of the steps for implementing the above embodiments may be implemented by a program instructing the associated hardware to perform the steps. The program may be stored in a computer-readable storage medium. The storage medium mentioned above may be a read-only memory, a random access memory, or the like. The processing unit or processor may be a central processing unit, a general purpose processor, an Application Specific Integrated Circuit (ASIC), a microprocessor (DSP), a Field Programmable Gate Array (FPGA) or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof.
The embodiments of the present application also provide a computer program product containing instructions, which when executed on a computer, cause the computer to execute any one of the methods in the above embodiments. The computer program product includes one or more computer instructions. The procedures or functions according to the embodiments of the present application are all or partially generated when the computer program instructions are loaded and executed on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored on a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wire (e.g., coaxial cable, fiber optic, digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). Computer-readable storage media can be any available media that can be accessed by a computer or data storage device including one or more available media integrated servers, data centers, and the like. The available media may be magnetic media (e.g., floppy disks, hard disks, tapes), optical media (e.g., DVDs), or semiconductor media (e.g., SSDs), among others.
It should be noted that the above devices for storing computer instructions or computer programs provided in the embodiments of the present application, such as, but not limited to, the above memories, computer readable storage media, communication chips, and the like, all have non-volatility (non-volatility). Those skilled in the art will recognize that, in one or more of the examples described above, the functions described in the embodiments of the present application may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable storage medium. Computer-readable storage media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.
The above description is intended only to illustrate the alternative embodiments of the present application, and should not be construed as limiting the present application, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims (10)

1. A fault injection test method is applied to a circuit to be tested, the circuit to be tested comprises a plurality of candidate tuples, each candidate tuple comprises an identification of a signal and a sending device and a receiving device of the signal, and the method comprises the following steps:
generating a target test case corresponding to the tuple to be tested of the circuit to be tested according to the preset corresponding relation between the candidate tuples and the test case elements; the target test case comprises a target test case element corresponding to the identification of the signal of the tuple to be tested, the sending device of the tuple to be tested and the receiving device of the tuple to be tested, and the tuple to be tested is one of the candidate tuples.
2. The fault injection testing method of claim 1, wherein the test case elements comprise at least one of a fault pattern, a fault injection manner, and a test criterion.
3. The fault injection testing method according to claim 2, wherein the preset correspondence includes a first correspondence between the transceiver device of the candidate tuple and the fault mode, a second correspondence between the transceiver device of the candidate tuple and the fault injection manner, and a third correspondence between a signal type corresponding to the identifier of the signal of the fault mode, the fault injection manner, and the candidate tuple and the testing criterion, wherein the transceiver device is the transmitter device or the receiver device;
the determining a target test case corresponding to the tuple to be tested of the circuit to be tested according to the preset corresponding relationship between the candidate tuples and the test case elements comprises the following steps:
determining a target failure mode corresponding to the transceiver of the tuple to be tested based on the first corresponding relation;
determining a target fault injection mode corresponding to the transceiver of the tuple to be tested based on the second corresponding relation;
based on the third corresponding relation, determining a corresponding target test criterion according to a signal type corresponding to the identifier of the signal of the tuple to be tested, the target fault mode and the target fault injection mode;
and generating the target test case, wherein the target test case comprises the target fault mode, the target fault injection mode and the target test criterion.
4. The fault injection testing method according to claim 1, wherein before generating the target test case corresponding to the tuple to be tested of the circuit to be tested according to the preset correspondence between the candidate tuples and the test case elements, the method further comprises:
acquiring design information of the circuit to be tested, wherein the design information comprises signal transmission relations among different devices of the circuit to be tested;
determining the plurality of candidate tuples according to the signal transmission relationship.
5. The fault injection testing method of claim 4, wherein said determining the plurality of candidate tuples according to the signal transmission relationship comprises:
determining two devices with signal transmission relations in the circuit to be tested and N different signals transmitted between the two devices as N signal tuples; wherein N is an integer greater than or equal to 2;
determining the candidate tuples according to M signal tuples, wherein if a receiving device of a first signal tuple in the M signal tuples is a sending device of a second signal tuple, and the influence of a signal in the first signal tuple and a signal in the second signal tuple on the circuit to be tested is the same, one candidate tuple is generated according to the first signal tuple and the second signal tuple, the sending device of the candidate tuple is a sending device of the first signal tuple, the receiving device of the candidate tuple is a receiving device of the second signal tuple, and M is an integer greater than N.
6. The fault injection test method according to any one of claims 1 to 5, wherein the tuple under test satisfies one or more of the following conditions:
the fault mode corresponding to the tuple to be tested is a preset fault mode;
the signal category corresponding to the signal in the tuple to be tested is a preset signal category;
the identification of the signal in the tuple to be detected is a preset identification;
the receiving device in the tuple to be tested is a first appointed device;
and/or the sending device in the tuple to be tested is a second designated device.
7. The fault injection test method according to any one of claims 1 to 6, wherein the method further comprises:
and carrying out fault injection test on the circuit to be tested according to the target test case.
8. The fault injection testing method of claim 7, wherein the candidate tuple corresponds to fault injection location information, and the performing the fault injection test on the circuit under test according to the target test case comprises:
controlling an injection device to inject a fault at a target fault injection position in the target fault injection mode; the target fault injection position is a position indicated by the fault injection position information corresponding to the tuple to be detected;
acquiring response information of the circuit to be tested after the fault is injected;
and obtaining a test result of the circuit to be tested according to the response information and the target test criterion.
9. The fault injection testing method according to claim 8, wherein the fault injection position information corresponding to each candidate tuple is determined according to the identifier of the signal, the position coordinate information of each pin of the transmitting device, and the position coordinate information of each pin of the receiving device, where the fault injection position information is used to determine a fault injection position of the test case corresponding to the candidate tuple in the circuit to be tested.
10. A fault injection test system, comprising: a processor, a memory, a power device, and an injection device;
the memory is to store computer instructions;
the processor, coupled to the memory, configured to execute the computer instructions to implement the fault injection testing method of any of claims 1-9;
the power device is connected with the processor and the injection device and is used for controlling the power device to move under the control of the processor;
and the injection device is used for injecting the fault at the target fault injection position in a target fault injection mode.
CN202211049234.6A 2022-08-30 2022-08-30 Fault injection test method and system Pending CN115616372A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117130945A (en) * 2023-10-26 2023-11-28 中国证券登记结算有限责任公司 Test method and device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117130945A (en) * 2023-10-26 2023-11-28 中国证券登记结算有限责任公司 Test method and device
CN117130945B (en) * 2023-10-26 2024-02-09 中国证券登记结算有限责任公司 Test method and device

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