CN115552383A

CN115552383A - Flash memory data management method, storage device controller and storage device

Info

Publication number: CN115552383A
Application number: CN202080100778.3A
Authority: CN
Inventors: 李楠; 伦志远; 周威
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-08-03
Filing date: 2020-08-03
Publication date: 2022-12-30
Also published as: WO2022027170A1

Abstract

The embodiment of the application provides a flash memory data management method, a storage device controller and a storage device. The method comprises the following steps: acquiring intrinsic parameters of a target block in a flash memory medium during erasing operation, wherein the intrinsic parameters comprise the execution time of the erasing operation; predicting the running state of the target block according to the intrinsic parameters and preset intrinsic parameter thresholds, wherein the running state comprises a normal state and an abnormal state; and performing subsequent data management on the target block according to the predicted running state. In the method provided by the embodiment, the intrinsic parameters of the target block in the flash memory medium during the erasing operation are acquired, and then the running state of the target block is predicted according to the intrinsic parameters and the preset intrinsic parameter threshold, so that the health degree of each block in the flash memory medium is evaluated, and the block is subjected to subsequent data management according to the running state determined by each block, so that the risk of data loss is reduced, and the data storage reliability of the flash memory medium is improved.

Description

Flash memory data management method, storage device controller and storage device

Technical Field

The present application relates to the field of storage technologies, and in particular, to a flash memory data management method, a storage device controller, and a storage device.

Background

NAND Flash (NAND Flash) is a mainstream non-volatile storage medium at present, and has been widely applied to smart phones, enterprise-level solid state disks, servers, cloud storage and the like.

In erasing and writing data on a target block in a NAND Flash, the industry usually only happens when the target block fails, for example: when a write failure (PSF for short) or an Erase failure (esase Status Fail for short) occurs, marking the target block as a bad block, thereby performing data management on the target block.

It can be seen that the current ways of determining the bad blocks are all based on the failure behavior that has occurred, and data processing is performed on the bad blocks after the failure behavior occurs, so that the risk of data loss of the bad blocks is high.

Disclosure of Invention

The application provides a flash memory data management method, a storage device controller and a storage device, so that the risk of data loss in a flash memory medium is reduced, and the data storage reliability of the flash memory medium is improved.

In a first aspect, an embodiment of the present application provides a flash memory data management method, including: acquiring intrinsic parameters of a target block in a flash memory medium during erasing operation, wherein the intrinsic parameters comprise the execution time of the erasing operation; predicting the running state of the target block according to the intrinsic parameters and preset intrinsic parameter thresholds, wherein the running state comprises a normal state and an abnormal state; and performing subsequent data management on the target block according to the predicted running state.

In the implementation mode, the intrinsic parameters of the target block in the flash memory medium during erasing operation are obtained, and then the running state of the target block is predicted according to the intrinsic parameters and the preset intrinsic parameter threshold, so that the health degree of each block in the flash memory medium is evaluated, and subsequent data management is performed on each block according to the predicted running state of the block, so that the risk of data loss is reduced, and the data storage reliability of the flash memory medium is improved.

In a possible design, if the prediction is an abnormal state, the performing subsequent data management on the target block according to the predicted operation state may include: the write operation or the program operation to the target block is stopped.

In the implementation manner, when the target block is determined to be in the abnormal state, the writing operation or the programming operation on the target block is stopped, so that failure of newly written data is avoided, the risk of data loss is further reduced, and the data storage reliability of the flash memory medium is improved.

In a possible design, if the prediction is an abnormal state, the performing subsequent data management on the target block according to the predicted operation state may include: data migration is performed on the stored data in the target block.

In the implementation mode, before the target block fails, the data transfer is performed on the storage data in the target block, so that the risk of data loss is further reduced, and the reliability of data storage is improved.

In one possible design, the target block may also be marked as a bad block if the prediction is an abnormal condition.

In the implementation mode, the failure is predicted in advance through the intrinsic parameters of the target block during the erasing operation and is processed correspondingly in advance, so that the extra operation generated after the failure occurs is reduced, the risk of data loss is further reduced, and the data storage reliability of the flash memory medium is improved.

In one possible design, the erase/write operation includes a program operation, and the intrinsic parameters include a program latency of the target block performing the program operation; and if the programming latency is greater than the preset programming time upper limit value or the programming latency is less than the preset programming time lower limit value, predicting that the running state is an abnormal state. .

In this implementation, the operating state of the target block is predicted by comparing the programming latency with a preset programming time range, and if the predicted operating state is an abnormal state, the target block may be marked as a bad block after the operating state of the target block is determined according to the intrinsic parameters and preset intrinsic parameters. Therefore, failure is predicted in advance and correspondingly processed in advance through intrinsic parameters of the target block during erasing operation, extra operation generated after failure occurrence is reduced, the risk of data loss is further reduced, and the data storage reliability of the flash memory medium is improved.

In one possible design, the programming latency includes word line programming time of each word line in the target block, if at least one word line programming time is greater than a preset word line programming time upper limit value, the operation state is predicted to be an abnormal state, the preset programming time upper limit value includes the preset word line programming time upper limit value, and the preset intrinsic parameter threshold includes the preset word line programming time upper limit value of each word line in the target block.

In one possible design, the intrinsic parameters further include erase times, and the upper limit value and the lower limit value of the preset programming time are determined according to the corresponding normal programming time for each erase time.

In one possible design, the erase operation includes an erase operation, and the intrinsic parameters include an erase latency for the target block to perform the erase operation; and if the erasing latency is greater than the preset erasing time upper limit value, predicting that the running state is an abnormal state.

In this implementation, the erase latency is compared with the preset erase time upper limit value to determine the operating state of the target block, and if the predicted operating state is an abnormal state, the target block may be marked as a bad block after the operating state of the target block is predicted according to the intrinsic parameters and the preset intrinsic parameters. Therefore, failure is predicted in advance and correspondingly processed in advance through intrinsic parameters of the target block during erasing operation, extra operation generated after failure occurrence is reduced, the risk of data loss is further reduced, and the data storage reliability of the flash memory medium is improved.

In one possible design, if the erase latency is greater than the preset erase time upper limit, the erase operation bit error number is read, and if the bit error number is greater than the preset bit error number, the operating state is predicted to be an abnormal state.

In a second aspect, an embodiment of the present application further provides a storage device controller, including: a processor and a buffer; the processor acquires intrinsic parameters of a target block in the flash memory medium during erasing operation from the buffer, wherein the intrinsic parameters comprise the execution time of the erasing operation; the processor predicts the running state of the target block according to the intrinsic parameters and preset intrinsic parameter thresholds, and stores the running state into a buffer, wherein the running state comprises a normal state and an abnormal state; and the processor manages data of the target block according to the predicted running state.

In one possible design, if the running state of the target block acquired by the processor from the buffer is an abnormal state, the processor stops writing or programming the target block.

In one possible design, if the running state of the target block acquired by the processor from the buffer is an abnormal state, the processor is used for performing data transfer on the storage data in the target block.

In one possible design, if the running state of the target block obtained by the processor from the buffer is an abnormal state, the processor marks the target block as a bad block in the buffer.

In one possible design, the erase/write operation includes a program operation, and the intrinsic parameters include a programming latency of the target block performing the program operation; and if the programming latency is greater than the preset programming time upper limit value or the programming latency is less than the preset programming time lower limit value, determining that the running state is an abnormal state.

In a possible design, the intrinsic parameters further include erase times, and the upper limit value and the lower limit value of the preset programming time are determined according to the corresponding normal programming time for each erase time.

In one possible design, the erase operation includes an erase operation, and the intrinsic parameters include an erase latency for the erase operation performed on the target block; and if the erasing latency is greater than the preset erasing time upper limit value, predicting the running state to be an abnormal state.

In a third aspect, an embodiment of the present application further provides a storage device, including: a flash memory medium and the storage device controller of any one of the aspects provided in the third aspect; the storage device controller is used for carrying out data management on each block in the flash memory medium.

The application provides a flash memory data management method, a storage device controller and a storage device, which are characterized in that intrinsic parameters of a target block in a flash memory medium during erasing operation are obtained, and then the running state of the target block is predicted according to the intrinsic parameters and a preset intrinsic parameter threshold value, so that the health degree of each block in the flash memory medium is evaluated, subsequent data management is carried out on the block according to the predicted running state of each block, the risk of data loss is reduced, and the data storage reliability of the flash memory medium is improved.

Drawings

FIG. 1 is a schematic diagram of a NAND Flash organization architecture provided in an embodiment of the present application;

FIG. 2 is a schematic diagram of a storage system architecture provided by an embodiment of the present application;

fig. 3 is a schematic flowchart illustrating a flash data management method according to an embodiment of the present application;

fig. 4 is a schematic flowchart of a flash memory data management method according to a second embodiment of the present application;

FIG. 5 is a graph illustrating programming latency test results according to one embodiment of the present application;

FIG. 6 is a graph illustrating programming latency test results according to another embodiment of the present application;

FIG. 7 is a voltage distribution diagram of the portion of the S1 region shown in FIG. 6;

fig. 8 is a schematic flowchart of a flash memory data management method according to a third embodiment of the present application;

FIG. 9 is a diagram illustrating a bit error test result according to an embodiment of the present application;

fig. 10 is a schematic flowchart of a flash memory data management method according to a fourth embodiment of the present application;

fig. 11 is a schematic structural diagram of a storage device controller according to a fifth embodiment of the present application;

fig. 12 is a schematic structural diagram of a storage device according to a fifth embodiment of the present application.

Detailed Description

In the modern electronic information industry, memories have been very important as carriers for storing data in electronic devices. Currently, the memories on the market are mainly divided into: volatile memory and non-volatile memory. The NAND Flash is a mainstream non-volatile storage medium at present, and has been widely applied to smart phones, enterprise solid state disks, servers, cloud storage and the like. The data storage device can store data for a long time after power failure, and has the advantages of high data transmission speed, low production cost, large storage capacity and the like.

Currently, mainstream NAND Flash manufacturers adopt a 3D multilayer stacking architecture; as the number of stacked layers increases, more and more memory cells (cells) are squeezed into a small space, mutual interference/leakage between the cells increases significantly, and the risk of reliability of the storage medium increases. The inherent errors in the flash memory become more and more serious due to the reduction of the distance between the memory cells and the reduction of the thickness of the oxide layer, the traditional error correction code method cannot meet the reliability requirement of the flash memory, and the reliability problem of the flash memory becomes an important subject in the current memory research field.

Before the NAND Flash reaches the maximum erasure (PE) life specification, the media may have critical read-write errors due to process defects (defects), resulting in data loss, or requiring the system to consume additional processes to recover the data. In addition, in the early application of new generation media, the greater the probability of early media failure and the greater the risk of data loss, since production/testing/parameter tuning is not fully optimized.

Fig. 1 is a schematic diagram of a NAND Flash organization architecture provided in an embodiment of the present application. As shown in fig. 1, the NAND chip 100 divides the memory cell into several flash memory chips (planes) after removing some control units on the periphery, for example: a first plane110 and a second plane120. Each of the planes may be subdivided into different blocks (blocks), for example, the first plane110 includes a first block 110B. In the using process, if a program/erase/read failure occurs, the block needs to be marked as a bad block, namely, a bad block, wherein the minimum unit of the isolation failure unit is one block. With continued reference to FIG. 1, in the NAND chip organization, the blocks are divided into different strings (strings), and the strings are divided into different Word Lines (WL) in the following. The minimum unit of the erase operation is a block, and the minimum unit of the program operation is a WL.

The industry typically only erases target blocks in NAND Flash, for example: when a write failure or an erase failure occurs, the target block is marked as a bad block. The data lost due to the write failure is then recovered by additional means.

Fig. 2 is a schematic diagram of a storage system architecture according to an embodiment of the present application. As shown in fig. 2, the memory system provided in this embodiment mainly includes three core modules: the system comprises a Controller (Controller), a Cache (Cache) and a storage medium (NAND Flash), wherein the Controller is a control brain of the whole storage system and is used for processing read-write commands of the solid state disk, managing data distribution, managing the NAND Flash and the like. The NAND flash part may be composed of 1 chip (die) or more, and is a physical carrier for the final storage of data. The buffer part is used for buffering data sent by the controller or read from the buffer. In the SSD storage system, a Redundant Array of Independent Disks (RAID) die is added to protect data.

With continued reference to fig. 2, one of the die may be used to perform an exclusive or operation on the data in the remaining die and then write the data into the RAID die, and after a media failure occurs, the lost data is recovered by reading the data at other positions on the same stripe; in addition, a data writing cache mode is adopted, and the data can be written into the cache firstly, and the cache is released after the data is successfully written into the NAND.

When a program failure marks a bad block, such as recovery using RAID technology, the amount of data to be read and the processing time increase in the background of the longer RAID stripe, and if a high-reliability cache is used, the media cost increases. In addition, some blocks that Erase successfully do not represent that the block is still a good block, and some word line to substrate leakage/shorts (WL-Channel leak/short) do not feed back an Erase failure (Erase fail), only a severe failure will result in an Erase failure. These slight leakage currents can cause Erase state tailing, which results in an Uncorrected Code word (UNC) due to overlap between the Erase state (Erase state) and the program state (7 states, which are a/B/C/D/E/F/G) after the next programming, and such Erase state tailing can not cause program failure and cannot be sensed from the program state. Even with high reliability, therefore, data loss may still occur when writing to NAND memory by releasing the buffer after programming is successful.

The embodiment of the application aims to predict/evaluate the state of the target block through some intrinsic parameters during NAND erasing, so as to predict failure in advance, perform corresponding advanced processing, perform corresponding data management on each block in the flash memory medium, and further reduce the risk of data loss.

The technical mode provided by the embodiment of the application is to utilize the intrinsic characteristics of the NAND Flash mediumMainly using programming latency (T) _program For short, T _PROG ) Erase latency (T) _erase For short, T _ERS ) And detecting an error number of blank pages (erased page FBC check) after erasing to judge the health state of the NAND medium, and predicting/processing impending failure in advance through subsequent operations.

Fig. 3 is a schematic flowchart of a flash memory data management method according to an embodiment of the present disclosure. As shown in fig. 3, the flash memory data management method provided in this embodiment includes:

step 101, obtaining intrinsic parameters of a target block in a flash memory medium during erasing operation.

The NAND Flash medium mainly comprises 3 basic operations: read operation (Read), program operation (Program), erase operation (Erase). In addition to the stability of Read time, NAND erase operation and program operation time may vary with the degree of wear of the medium, especially when some weak leakage occurs, the current erase operation or program operation may not necessarily show a state failure, but may show a large variation in erase operation or program operation time. Therefore, the prediction of the operation state of the target block in the flash memory medium can be performed by obtaining the intrinsic parameters of the target block during the erasing operation, wherein the intrinsic parameters include the operation time required for completing the erasing operation.

And 102, predicting the running state of the target block according to the intrinsic parameters and preset intrinsic parameter thresholds.

After the intrinsic parameters of the target block during the erasing operation are obtained, the running state of the target block can be predicted according to the intrinsic parameters of the NAND medium and the intrinsic parameters and a preset intrinsic parameter threshold, wherein the running state includes a normal state and an abnormal state. Therefore, the health degree of the NAND medium is evaluated by monitoring the programming latency and the erasing latency of the NAND so as to predict the occurrence of target block failure in advance.

The embodiment of the application can be a software management scheme, and the whole set of application strategy is realized through a storage system controller. Referring to fig. 2, the programming latency and the erasing latency may be detected by the controller according to the execution time of the programming operation and the erasing operation, and the number of blank page errors after erasing may be detected by the controller according to the read operation to read the blank page data. And the controller can compare the offline preset operation time or the blank page error number threshold, if the failure is predicted to occur, the controller defines the block as a bad block, ignores the bad block in the subsequent operation and does not perform the operation any more.

For the comparison between the intrinsic parameter and the preset intrinsic parameter threshold, the following three sub-schemes may be included, respectively:

1. presetting programming operation failure by programming latency presetting;

2. predicting an over-programming problem by programming latency;

3. failure is predicted by erasure latency and FBC check after erasure.

In actual operation, the above three sub-schemes may be combined arbitrarily and then predicted, or only a single scheme may be used.

And 103, performing subsequent data management on the target block according to the predicted running state.

After predicting the operating state of the target block according to the intrinsic parameters and the preset intrinsic parameter threshold, the controller may perform subsequent data management on the target block according to the predicted operating state of the target block.

If the predicted operating state of the target block is an abnormal state, it indicates that the target block has a high failure risk, and therefore, in order to reduce the risk of data loss, the write operation or the program operation on the target block may be stopped, and the failure of newly written data is avoided. However, if the predicted operating state of the target block is an abnormal state, which indicates that the target block has a low risk of failure, the reliability of data stored in the target block is high, and thus, the write operation or the program operation may be continued on the target block.

In addition, when the predicted running state of the target block is an abnormal state, in order to further ensure the risk of loss of data already existing in the target block, data transfer can be performed on the stored data in the target block.

In the process of erasing data, the controller may predict the operation status of each block by obtaining the associated identification code of the block, where the block predicted to be in an abnormal status may be marked as a bad block, for example, the bad block identification may be performed by configuring the identification bits of the block as specific fields.

In this embodiment, the health degree of each block in the flash memory medium is evaluated by acquiring the intrinsic parameter of the target block in the flash memory medium during the erasing operation and then predicting the running state of the target block according to the intrinsic parameter and the preset intrinsic parameter threshold, so as to perform subsequent data management on each block according to the predicted running state of the block, thereby reducing the risk of data loss and improving the data storage reliability of the flash memory medium.

On the basis of the above embodiment, if the predicted operation state is an abnormal state, after the operation state of the target block is predicted according to the intrinsic parameters and the preset intrinsic parameters, the target block may be marked as a bad block. Therefore, failure is predicted in advance and corresponding advanced treatment is carried out through intrinsic parameters of the target block during erasing operation, extra operation generated after failure occurs is reduced, the risk of data loss is further reduced, and the data storage reliability of the flash memory medium is improved.

In addition, after the target block is marked as a bad block, data transfer can be performed on the storage data in the target block. Therefore, before the target block fails, the data in the target block is moved, so that the risk of data loss is further reduced, and the reliability of data storage is improved.

Fig. 4 is a flowchart illustrating a flash data management method according to a second embodiment of the present application. As shown in fig. 4, the flash memory data management method provided in this embodiment includes:

step 201, obtaining intrinsic parameters of a target block in the flash memory medium during erasing operation.

Since the program operation time varies depending on the degree of wear of the medium, the current program operation may not necessarily show a state failure, but may show a large variation in the program operation time, particularly when some weak leakage occurs, wherein the program latency may be obtained by the controller detecting the execution time of the program operation.

Therefore, in this step, the prediction of the operating state of the target block in the flash memory medium can be performed by acquiring the programming latency of the target block when the programming operation is performed.

Step 202, determining whether the programming latency is within a preset programming time range. If yes, go to step 204; if the determination result is negative, step 203 is executed.

In this step, after the programming latency is obtained, the programming latency may be compared with a preset programming time range, so as to predict the operating state of the target block. The preset programming time range may be determined according to a normal programming time range.

And step 203, predicting that the running state is an abnormal state.

If the programming latency is greater than the preset programming time upper limit value or the programming latency is less than the preset programming time lower limit value, the operation state can be predicted to be an abnormal state.

When the latency is greater than the preset upper limit of the programming time, the word line programming time of each word line in the target block can be acquired. And the programming latency includes word line programming time of each word line in the target block, if at least one word line programming time is greater than a preset word line programming time upper limit value, the operation state is predicted to be an abnormal state, and the preset programming time upper limit value includes the preset word line programming time upper limit value.

Specifically, leakage between word lines (WL-WL) or between word lines and channels (WL-channel) may be only slight in an initial stage of occurrence, and programming failure may not occur immediately.

Fig. 5 is a graph illustrating programming latency test results according to an embodiment of the present application. As shown in fig. 5, the horizontal axis represents the number of erase and write cycles of the target block, the vertical axis represents the programming latency, 4 groups of four WLs share the WL metal layer but different channels on the same layer (layer), and the programming sequence is a loop from top to bottom. It can be seen that the programming latency is slowly reduced with the increase of the number of erase-write cycles, but the programming time of the first WL and the second WL is suddenly and abnormally increased by the number of erase-write cycles being around 7500, but no programming failure occurs, and when the programming is performed to the third WL, the programming failure occurs, i.e. the fourth WL cannot continue to program. Referring to fig. 5, L10 is a programming latency test curve corresponding to the first WL, L20 is a programming latency test curve corresponding to the second WL, L30 is a programming latency test curve corresponding to the third WL, and L40 is a programming latency test curve corresponding to the fourth WL.

Furthermore, in a specific experiment, for the case where a program operation failure occurred in the test, the program time abnormality of the previous WL occurred all before the occurrence. Therefore, this type of abnormal rise in programming latency is a very obvious abnormal signal and therefore can be used to detect the occurrence of a programming failure in advance.

When the programming latency is less than the preset programming time lower limit value, the operation state can also be predicted to be an abnormal state. The intrinsic parameters may further include erase times, a preset upper programming time limit and a preset lower programming time limit, which are determined according to the corresponding normal programming time for each erase time.

Specifically, as the number of wear of the flash memory medium increases, the defects in the oxide layer gradually increase after the tunnel oxide layer is subjected to repeated voltage stress, so that electrons can more easily enter a charge trap layer (charge trap layer) through the defects, and the programming speed is increased and the programming latency is decreased in response to the programming latency. The programming speed is accelerated to a certain threshold value, so that the number of electrons acquired by each voltage pulse is increased, the programming precision is reduced, the particle performance is over-programmed in response, namely the threshold voltage after programming is higher than the preset value, and finally the response is that the read data is increased by mistake, and even the UNC is caused.

Through testing, the flash memory medium with the over-programming phenomenon is found to have the programming latency period far shorter than that of other normal media. Fig. 6 is a graph illustrating the results of programming latency tests according to another embodiment of the present application. As shown in fig. 6, the vertical axis represents the programming latency, and the horizontal axis represents the maximum number of errors per page (page). It can be seen from the figure that the programming latency of the page with the increased Bit error Count (FBC), i.e., the S1 region shown in the figure, is in a smaller interval.

The threshold voltage distributions of these FBC larger pages can be analyzed for the S1 region in fig. 6. FIG. 7 is a voltage distribution diagram of the portion of the S1 region shown in FIG. 6. As shown in FIG. 7, a significant over-programming problem can be observed, and the increase in the number of errors caused by such over-programming is due to the rise in the valley of the voltage, which cannot be recovered even by a bias read. In fig. 7, the horizontal axis represents the value of the threshold voltage, the vertical axis represents the number of memory cells under the threshold voltage, all the memory cell distributions under one word line of the normal triple-layer cell (TLC) are in 8 states, except the erase state, the memory cell distributions are respectively in an a/B/C/D/E/F/G state from left to right as shown in fig. 7, L1 represents the threshold voltage distribution of the page with the larger error number in the total S1 area of fig. 6, and L2/L3 is the threshold voltage distribution of the page with the normal error number.

Thus, the trend of decreasing programming latency can be used to estimate or predict the health of the storage medium, and samples can be measured off-line, such as: the change rule of the programming latency along with the PE times and the programming latency threshold value causing the over-programming problem are applied to online monitoring. When the programming latency falls to a certain threshold, the corresponding target block is processed in advance.

And step 204, predicting that the running state is a normal state.

In this embodiment, the operating state of the target block is predicted by comparing the programming latency with a preset programming time range, and if the predicted operating state is an abnormal state, the target block may be marked as a bad block after predicting the operating state of the target block according to the intrinsic parameters and the preset intrinsic parameters. Therefore, failure is predicted in advance and corresponding advanced treatment is carried out through intrinsic parameters of the target block during erasing operation, extra operation generated after failure occurs is reduced, the risk of data loss is further reduced, and the data storage reliability of the flash memory medium is improved.

And step 205, performing subsequent data management on the target block according to the predicted running state.

After determining the operating state of the target block according to the intrinsic parameters and the preset intrinsic parameter threshold, the controller may perform subsequent data management on the target block according to the predicted operating state of the target block.

If the predicted running state of the target block is an abnormal state, it indicates that the target block has a high failure risk, and therefore, in order to reduce the risk of data loss, the write operation or the program operation on the target block may be stopped, and the failure of newly written data is avoided. However, if the predicted operating state of the target block is an abnormal state, which indicates that the target block has a low risk of failure, the reliability of data stored in the target block is high, and therefore, the write operation or the program operation may be continued on the target block. In addition, the target block may be marked as a bad block for the purpose of subsequently identifying the target block.

It should be noted that, when the running state of the target block is predicted to be an abnormal state, the target block may be marked as a bad block, or only the write operation or the program operation performed on the target block is stopped, or only the data stored in the target block is transferred, or any combination of the above three manners.

Fig. 8 is a schematic flowchart of a flash memory data management method according to a third embodiment of the present application. As shown in fig. 8, the flash memory data management method provided in this embodiment includes:

step 301, obtaining intrinsic parameters of a target block in the flash memory medium during erasing operation.

Since the erase operation time varies with the degree of wear of the medium, particularly when some weak leakage occurs, the current erase operation may not necessarily show a status failure, but may show a large variation in erase operation time, wherein the erase latency may be obtained by the controller detecting the execution time of the program operation.

Therefore, in this step, the operation state of the target block in the flash memory medium can be predicted by acquiring the erasing latency of the target block during the erasing operation.

Step 302, determine whether the erase latency is greater than a preset erase time upper limit. If yes, go to step 303; if the determination result is negative, go to step 304.

And step 303, predicting that the running state is an abnormal state.

And if the erasing latency is greater than the preset erasing time upper limit value, predicting the running state to be an abnormal state. Optionally, after it is determined that the erasure latency is greater than the preset erasure time upper limit value, the erasure operation bit error number continues to be read, and if the bit error number is greater than the preset bit error number, the operation state is predicted to be an abnormal state.

In particular, due to the high potential difference generated during erase, many tunnel Oxide (tunnel Oxide) breakdowns can occur during the erase cycle. The WL-Channel leakage may decrease the Erase voltage, causing an abnormal increase in Erase latency, and the leaky WL may produce an Erase tail, which may not feedback Erase failure due to a single WL Erase tail, resulting in overlap of Erase state and program a state during subsequent programming, causing data unrecoverable, or directly causing program failure in the next programming cycle.

Fig. 9 is a diagram illustrating a bit error count test result according to an embodiment of the present application. As shown in fig. 9, the data indicates that the erase operation before the program failure occurred does not feedback the erase failure, but the erase FBC (round dots are FBC values after erase, vertical axis is FBC, horizontal axis is number of erase cycles) reading has shown an anomaly, and the program failure occurred in the next program cycle (cross dots are FBC values after program, where the number of errors read is very high due to program failure). Therefore, the failure can be predicted in advance by judging the change of the erasing time, and if the erasing time is abnormally prolonged, reading the FBC number of the erasing state, monitoring the erasing state trailing caused by slight leakage and the like.

And step 304, predicting that the running state is a normal state.

In this embodiment, the operating state of the target block is predicted by comparing the erase latency with the preset erase time upper limit value, and if the predicted operating state is an abnormal state, the target block may be marked as a bad block after the operating state of the target block is predicted based on the intrinsic parameters and the preset intrinsic parameters. Therefore, failure is predicted in advance and corresponding advanced treatment is carried out through intrinsic parameters of the target block during erasing operation, extra operation generated after failure occurs is reduced, the risk of data loss is further reduced, and the data storage reliability of the flash memory medium is improved.

And 305, performing subsequent data management on the target block according to the predicted running state.

The specific implementation manner of step 305 may refer to the specific description of step 205 in the embodiment shown in fig. 4, and is not described herein again.

Fig. 10 is a schematic flowchart of a flash memory data management method of a flash memory according to a fourth embodiment of the present application. As shown in fig. 8, the flash memory data management method provided in this embodiment includes:

step 401, selecting the word line of the target block and starting writing data.

And step 402, recording the programming latency after the programming is finished.

In a programming operation, when a target block is programmed, the controller records a programming time and an erase-write cycle number for each WL, and compares the programming latency measured offline with a preset programming time range of the erase-write cycle number after wear.

Step 403, determining whether the programming latency is within a preset programming time range. If yes, go to step 405, and if no, go to step 404.

In this step, after the program latency is acquired, the program latency may be compared with a preset program time range, so as to predict the operating state of the target block. The preset programming time range may be determined according to a normal programming time range.

Step 404, determine whether the programming latency is greater than the upper limit of the preset programming time. If the determination result is yes, step 410 is executed, and if the determination result is no, step 4041 is executed.

When the latency is greater than the preset upper limit value of the programming time, the word line programming time of each word line in the target block can be acquired. The programming latency period includes word line programming time of each word line in the target block, if at least one word line programming time is greater than a preset word line programming time upper limit value, the operation state is predicted to be an abnormal state, and the preset programming time upper limit value includes the preset word line programming time upper limit value.

Step 4041, read verify.

Step 4042, determine whether the read verification passes. If the determination result is negative, step 410 is executed, and if the determination result is positive, step 405 is executed.

When the programming latency is less than the preset programming time lower limit value, the operation state can also be predicted to be an abnormal state. And determining the upper limit value and the lower limit value of the preset programming time according to the corresponding normal programming time under each erasing frequency. When the programming latency reaches a certain threshold, the corresponding target block is processed in advance.

Step 405, continue with the next word line programming.

And step 406, performing an erasing operation on the target block, and recording an erasing latency.

Step 407, determining whether the erasure latency is greater than a preset erasure time upper limit. If the determination result is no, step 409 is executed, and if the determination result is yes, step 4081 is executed.

Step 4081, read erase operation bit error number.

Step 4082, determine that the bit error number is greater than the predetermined bit error number. If the determination result is no, step 409 is executed, and if the determination result is yes, step 410 is executed.

During programming operation, when the target starts to be programmed, the controller records the programming time and the erasing and writing cycle number of each WL, compares the programming time and the erasing and writing cycle number with the relation between the programming time and the abrasion cycle number measured offline, when the current programming latency is detected to be within a preset programming time safety range corresponding to the current cycle value, the WL is considered to be in a healthy state, the next operation can be continued, and when the current programming time is detected to be greater than the preset programming time safety range of the cycle value, the target block is directly considered to be a bad block, the bad block is marked, and necessary data moving is carried out. When the current programming time is detected to be smaller than the preset programming time safety range of the cycle value, the target block is considered to be in a risk state, read verify (read verify) is immediately carried out on the programmed WL to determine whether the FBC is increased, and if the FBC is found to exceed a certain threshold value, the FBC is marked as a bad block.

During the erasing operation, when the target block is subjected to the erasing operation, the controller records the erasing latency, compares the erasing latency with the relation between the off-line measured erasing time and the abrasion cycle number, when the erasing latency is found to exceed the erasing time safety interval of the current cycle value, the controller issues a reading instruction, reads the error number of the blank page subjected to erasing on the specified page, and if the error number of the found bits is greater than the error number of the preset bits, the target block is marked as the bad block.

And step 409, updating the erasing cycle times.

Step 410, mark the target block as bad block.

Fig. 11 is a schematic structural diagram of a storage device controller according to a fifth embodiment of the present application. As shown in fig. 11, the storage device controller 500 provided in the present embodiment includes: a processor 501 and a buffer 502; the processor 501 obtains intrinsic parameters of a target block in the flash memory medium during an erase operation from the buffer 502, where the intrinsic parameters include execution time of the erase operation; then, the processor 501 predicts the running state of the target block according to the intrinsic parameter and a preset intrinsic parameter threshold, and stores the running state into the buffer 502, where the running state includes a normal state and an abnormal state; next, the processor 501 performs data management on the target block according to the predicted operation state.

In one possible design, if the running state of the target block acquired by the processor 501 from the buffer 502 is an abnormal state, the processor 501 stops the write operation or the program operation on the target block.

In one possible design, if the running state of the target block acquired by the processor 501 from the buffer 502 is an abnormal state, the processor 501 is configured to perform data transfer on the storage data in the target block.

In one possible design, if the running state of the target block obtained by the processor 501 from the buffer 502 is an abnormal state, the processor 501 marks the target block as a bad block in the buffer 502.

In one possible design, the erase/write operation includes a program operation, and the intrinsic parameters include a programming latency of the target block performing the program operation; and if the programming latency is greater than the preset programming time upper limit value or the programming latency is less than the preset programming time lower limit value, predicting that the running state is an abnormal state.

In one possible design, the erase operation includes an erase operation, and the intrinsic parameters include an erase latency for the target block to perform the erase operation; and if the erasing latency is greater than the preset erasing time upper limit value, predicting the running state to be an abnormal state.

Fig. 12 is a schematic structural diagram of a storage device according to a fifth embodiment of the present application. As shown in fig. 12, the storage device provided in the present embodiment includes a flash memory medium and the storage device controller shown in fig. 11. The flash media portion may be composed of 1 die or multiple dies, which is the physical carrier where the data is ultimately stored. The storage device controller is used for carrying out data management on each block in the flash memory medium.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

A flash memory data management method, comprising:

acquiring intrinsic parameters of a target block in a flash memory medium during erasing operation, wherein the intrinsic parameters comprise the execution time of the erasing operation;

predicting the running state of the target block according to the intrinsic parameters and a preset intrinsic parameter threshold, wherein the running state comprises a normal state and an abnormal state;

and performing data management on the target block according to the predicted running state.
The method of claim 1, wherein if the abnormal state is predicted, the managing data of the target block according to the predicted operating state comprises:

and stopping writing or programming operation on the target block.
The method according to claim 1 or 2, wherein if the abnormal state is predicted, performing subsequent data management on the target block according to the running state comprises:

and carrying out data transfer on the storage data in the target block.
The method according to claim 2 or 3, wherein the subsequent data management of the target block according to the running state further comprises:

and marking the target block as a bad block.
The method according to any one of claims 1-4, wherein the erase/write operation includes a program operation, and the intrinsic parameters include a programming latency of the target block performing the program operation;

and if the programming latency is greater than a preset programming time upper limit value or the programming latency is less than a preset programming time lower limit value, predicting the running state to be the abnormal state.
The method according to claim 5, wherein the programming latency includes a word line programming time of each word line in the target block, and if at least one of the word line programming times is greater than a preset word line programming time upper limit value, the operating state is predicted to be the abnormal state, the preset programming time upper limit value includes the preset word line programming time upper limit value, and the preset intrinsic parameter threshold value includes a preset word line programming time upper limit value of each word line in the target block.
The method of claim 5, wherein the intrinsic parameters further include erase times, and the upper and lower predetermined program time limits are determined according to corresponding normal program times for each erase time.
The method according to any of claims 1-4, wherein the erase/write operation includes an erase operation, and the intrinsic parameters include an erase latency for the target block to perform the erase operation;

and if the erasing latency is greater than a preset erasing time upper limit value, predicting the running state to be the abnormal state.
The method of claim 8, wherein if the erase latency is greater than a preset erase time upper limit, reading the erase operation bit error number, and if the bit error number is greater than a preset bit error number, predicting the operation status as the abnormal status.
A storage device controller, comprising: a processor and a buffer;

the processor acquires intrinsic parameters of a target block in a flash memory medium during erasing operation from the buffer, wherein the intrinsic parameters comprise the execution time of the erasing operation;

the processor determines the running state of the target block according to the intrinsic parameters and preset intrinsic parameter thresholds, and stores the running state into the buffer, wherein the running state comprises a normal state and an abnormal state;

and the processor performs data management on the target block according to the predicted running state.
The storage device controller of claim 10, wherein if the running status of the target block retrieved from the buffer by the processor is the abnormal status, the processor stops writing or programming the target block.
The storage device controller according to claim 10 or 11, wherein if the running status of the target block acquired by the processor from the buffer is the abnormal status, the processor is configured to perform data transfer on the storage data in the target block.
The storage device controller according to claim 11 or 12, wherein if the running status of the target block obtained by the processor from the buffer is the abnormal status, the processor marks the target block in the buffer as a bad block.
The controller according to any one of claims 10-13, wherein the erasure operation includes a program operation, and the intrinsic parameters include a programming latency for the target block to perform the program operation;

and if the programming latency is greater than a preset programming time upper limit value or the programming latency is less than a preset programming time lower limit value, predicting the running state to be the abnormal state.
The memory device controller according to claim 14, wherein the programming latency includes a word line programming time of each word line in the target block, and the operating state is predicted to be the abnormal state if there is at least one word line programming time greater than a preset word line programming time upper limit value, the preset programming time upper limit value includes the preset word line programming time upper limit value, and the preset intrinsic parameter threshold includes a preset word line programming time upper limit value of each word line in the target block.
The controller according to claim 14, wherein the intrinsic parameters further include erase times, and the upper and lower preset programming time limits are determined according to corresponding normal programming times for the respective erase times.
The memory device controller of any of claims 10-13, wherein the erase operation comprises an erase operation, and the intrinsic parameters comprise an erase latency for the target block to perform the erase operation;

and if the erasing latency is greater than a preset erasing time upper limit value, predicting the running state to be the abnormal state.
The controller according to claim 17, wherein if the erase latency is greater than a preset erase time upper limit value, the erase operation bit error count is read, and if the bit error count is greater than a preset bit error count, the operating state is predicted to be the abnormal state.
A storage device, comprising: a flash memory medium and a storage device controller according to any one of claims 10 to 18; the storage device controller is used for performing data management on each block in the flash memory medium.