CN115550116B - Combined optimization system for tap coefficients of feedforward equalizer at sending end and receiving end - Google Patents
Combined optimization system for tap coefficients of feedforward equalizer at sending end and receiving end Download PDFInfo
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- CN115550116B CN115550116B CN202211519149.1A CN202211519149A CN115550116B CN 115550116 B CN115550116 B CN 115550116B CN 202211519149 A CN202211519149 A CN 202211519149A CN 115550116 B CN115550116 B CN 115550116B
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
- H04L25/03025—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception using a two-tap delay line
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03343—Arrangements at the transmitter end
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Abstract
The invention relates to the technical field of serial transceivers, and discloses a combined optimization system for tap coefficients of a feedforward equalizer at a sending end and a receiving end, which is applied to a chip, wherein a circuit in the chip comprises: a serializer, a pre-drive stage, an output drive stage with a feed-forward equalizer, a channel, a continuous-time linear equalizer, an analog-to-digital converter, a digital signal processing module, a clock and data recovery circuit, a clock circuit, and a feed-forward equalizer tap coefficient adjustment module. The invention combines the tap coefficients of the feedforward equalizer at the sending end and the receiving end, so that the setting of the tap coefficients of the feedforward equalizer at the sending end is more suitable for the channel damage condition in the current application, the power consumption of the equalizing circuit is greatly reduced, the equalizing effect of the signal is improved, and the error rate of the signal is reduced.
Description
Technical Field
The invention relates to the technical field of serial transceivers, which is used for carrying out feedforward equalization on signals of the serial transceivers and reducing the error rate of the signals, in particular to a combined optimization system of tap coefficients of a feedforward equalizer at a sending end and a receiving end.
Background
The serial transceiver has the main problems that various intersymbol crosstalk exists after a high-speed signal at a sending end is influenced by a channel, so that the 0/1 of the signal is difficult to distinguish, if the signal is not subjected to equalization processing, the signal received by the receiving end has a great number of error codes, and in order to reduce the error code rate of a transmission signal, various equalizers are required to eliminate various types of intersymbol crosstalk in a channel impulse response with limited bandwidth;
the signal equalization means of the serial transceiver can be seen from a sending end and a receiving end respectively, the main equalization means of the sending end is a feed-forward equalizer, the main equalization means of the receiving end has three kinds, namely a continuous time linear equalization amplifier, a feed-forward equalizer and a decision feedback equalizer, the feed-forward equalizer and the decision feedback equalizer in the receiving end can be realized in an analog mode and a digital mode respectively according to the fact that the receiving end is based on a Slicer form or an analog-to-digital converter form, and tap coefficients of the feed-forward equalizer and the decision feedback equalizer in the receiving end are converged by self-adaptation of a minimum mean square algorithm to cope with the condition of different signal damages;
however, the feedforward equalizer at the transmitting end is not aware of the damage of the transmission channel, and its tap coefficient is often only preset, and the transmitted pulse is pre-distorted in advance to offset the distortion caused by the channel, but the preset tap coefficient is not necessarily suitable for the transmission characteristic of the current channel, so that the best equalization effect cannot be achieved.
Disclosure of Invention
The invention aims to provide a combined optimization system for tap coefficients of a feedforward equalizer at a sending end and a receiving end, because equalization is necessary in a high-speed communication link, particularly in a copper channel, a signal transmission line shows a low-pass filtering characteristic, the channel has large attenuation on high-frequency components of signals in the transmission process, the attenuation on low-frequency components is reduced, the signal quality is reduced, and if equalization compensation is not carried out on the signals, the error rate of the system is greatly increased;
the feedforward equalizer is the most commonly used equalization technology in a high-speed serial port system, in order to relieve the equalization pressure of a receiving end, a sending end of the high-speed serial port system usually uses the feedforward equalizer technology to pre-equalize signals, two basic types of feedforward equalization of the sending end are pre-emphasis and de-emphasis, and the pre-emphasis technology enhances high-frequency components of the signals at the sending end of a transmission line so as to compensate for overlarge attenuation of the high-frequency components in the transmission process;
the signal frequency is mainly determined by the speed of signal level change, so that the high-frequency components of the signal mainly appear at the rising edge and the falling edge of the signal, and the pre-emphasis technology is to enhance the amplitude of the signal at the rising edge and the falling edge; the idea of the de-emphasis technique is similar to that of the pre-emphasis technique, but the implementation method is slightly different, the pre-emphasis is to increase the amplitudes of the rising edge and the falling edge of the signal, and the amplitudes of other places are unchanged; the de-emphasis is to keep the amplitude of the rising edge and the falling edge of the signal unchanged, the signal at other places is weakened, the signal swing amplitude after de-emphasis compensation is smaller than that after pre-emphasis compensation, the eye diagram height is low, the power consumption is small, and the electromagnetic radiation is small.
In order to achieve the purpose, the invention provides the following technical scheme: the feedforward equalization method of the sending end, whether using pre-emphasis and de-emphasis, is realized by Finite Impulse Response (FIR) filter, i.e. adding the delayed signals according to different weights (C0, C1, C2, …, CN), controlling the size of the weight can adjust the equalization intensity, the essence of the feedforward equalizer is to use a high-pass filter to improve the high-frequency component of the signal, realize the compensation of the channel, and the expression of the filter coefficient is as follows:
compared with the method that the feedforward equalizer at the receiving end can automatically converge the coefficients of the feedforward equalizer taps according to the channel loss and the crosstalk characteristics, the feedforward equalizer at the transmitting end cannot set the most appropriate coefficient size due to the lack of information of subsequent channels, and the common method is to preset a coefficient size combination, but the method may not achieve the most appropriate equalization on signals;
in the invention, a feedforward equalizer at a sending end adopts 3-order taps, namely a front tap (Pre-Cursor), a Main tap (Main-Cursor) and a rear tap (Post-Cursor); the feedforward equalizer at the receiving end adopts 8 taps, and besides one main tap, a plurality of front taps and rear taps are also adopted. In a transceiver fully integrated system, the coefficients of a feedforward equalizer at a receiving end can automatically converge according to the quality of signals, and the loss condition of the signals caused by a channel can be reflected by the coefficients; the coefficient of the main tap, the previous tap and the next tap in the feedforward equalizer of the receiving end can be fed back to the 3-order tap of the feedforward equalizer of the sending end through a coefficient feedback system, so that the setting of the coefficient of the 3-order tap of the feedforward equalizer of the sending end is the optimal condition according to the condition under the current channel, and after the setting of the coefficient of the feedforward equalizer of the sending end is finished, the convergence of the coefficient of the feedforward equalizer of the receiving end is carried out again.
The invention provides a combined optimization system for tap coefficients of a feedforward equalizer at a sending end and a receiving end, which has the beneficial effects that:
1. the invention utilizes the tap coefficient of the automatic convergence of the feedforward equalizer at the receiving end in the serial transceiver to help set the tap coefficient of the feedforward equalizer at the sending end, thereby realizing a feedforward equalization scheme with smaller power consumption and better equalization effect;
2. the invention combines the tap coefficients of the feedforward equalizer at the sending end and the receiving end, so that the setting of the tap coefficients of the feedforward equalizer at the sending end is more suitable for the channel damage condition in the current application, the power consumption of the equalizing circuit is greatly reduced, the equalizing effect of the signal is improved, and the error rate of the signal is reduced.
Drawings
FIG. 1 is a block diagram of a serial transceiver module provided by an implementation of the present invention;
FIG. 2 is a circuit diagram of a serializer provided in an implementation of the invention;
FIG. 3 is a circuit diagram of a predrive stage provided by an implementation of the present invention;
FIG. 4 is a circuit diagram of an output driver stage with a feed-forward equalizer provided by an implementation of the present invention;
FIG. 5 is a circuit diagram of a continuous-time linear equalizer provided by an implementation of the present invention;
FIG. 6 is a circuit diagram of an analog-to-digital converter provided by an implementation of the present invention;
FIG. 7 is a circuit diagram of a digital signal processing module provided in accordance with an embodiment of the present invention;
FIG. 8 is a circuit diagram of a clock and data recovery circuit provided by an implementation of the present invention;
FIG. 9 is a circuit diagram of a clock circuit provided by an implementation of the present invention;
fig. 10 is a circuit diagram of a feed forward equalizer tap coefficient adjustment module provided by an implementation of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, the present invention provides a technical solution: a sending end and receiving end feedforward equalizer tap coefficient joint optimization system, the system is applied to the chip 100, 64 routes of parallel data input in the implementation mode are serialized to 1 route of serial signal and the sending end adopts a 3-tap feedforward equalizer, other quantities of parallel data under different rate distribution schemes and the feedforward equalizers with different tap quantities of the sending end can adopt the sending end and receiving end feedforward equalizer tap coefficient joint optimization system of the invention;
specifically, the system for jointly optimizing the tap coefficients of the feedforward equalizers at the sending end and the receiving end in the serial receiver in the chip comprises: serializer 110, pre-drive stage 120, output drive stage with feedforward equalizer 130, channel 140, continuous-time linear equalizer 150, analog-to-digital converter 160, digital signal processing module 170, clock and data recovery circuit 180, clock circuit 190, and feedforward equalizer tap coefficient adjustment module 200.
In this embodiment, please refer to fig. 2; serializer 110 includes 64 to 4 serializing circuits 111,4 to 1 serializing circuit 112,3 order FIR generator 113 and frequency dividing circuit 114 for providing corresponding clocks to the serializing circuits, 64 to 4 serializing circuits 111 receives 64 parallel data transmitted from the digital system and serializes the data in sequence according to the clock signals, the 4 parallel signals after the serializing are then sent to 4 to 1 serializing circuits 112,4 to 1 serializing circuit 112 to serialize the 4 parallel signals transmitted from 64 to 4 serializing circuits 111 into 1 serial signal, in order to provide input signals to the feed-forward equalizer finally having 3-order taps, it is also necessary to generate Pre serializing signal, in ma serializing signal and Post serializing signal through 3-order generators, frequency dividing circuit 114 receives four-phase quadrature clock from clock circuit 190 and divides the clock frequency to 64 to 4 serializing circuits 111.
In this embodiment, please refer to fig. 3; because the transistor size of the final output stage is very large, and the transistor size of the serialization circuit is very small, the transistor of the final output stage may not be driven, so the Pre-driving stage 120 is required to Pre-drive the Pre-serialization signal, the Main serialization signal and the Post serialization signal, the Pre-driving stage 120 is Pre-driven by using the inverters with the size being amplified step by step, each inverter is composed of a PMOS (P-Metal-Oxide-Semiconductor) tube and an NMOS (N-Metal-Oxide-Semiconductor) tube; the sizes of PMOS tubes of P1, P2, P3 and P4 are amplified step by step, the sizes of NMOS tubes of N1, N2, N3 and N4 are amplified step by step, and the size of a phase inverter formed by P4 and N4 at the last stage can drive the last output stage; a feedback resistor Rf is added in the inverter chain to form the balance of Sub-UI (Sub Unit interval), so that the rising speed of the output signal of the inverter is increased.
In this embodiment, please refer to fig. 4; the output driver stage with feed forward equalizer 130 includes a common mode feedback circuit 131, a resistor array 132, and a current mode logic driver stage 133; the common mode feedback circuit 131 is composed of a common mode extraction circuit 1311 and an operational amplifier 1312; the common mode extraction circuit 1311 uses two resistors R with large resistance to be placed between the differential output terminals Voutp and Voutn of the current-mode logic driver stage 133, extracts the common mode level VCM differentially output by the current-mode logic driver stage 133, and sends the common mode level VCM to the operational amplifier 1312 together with the reference voltage VREF set by the reference voltage generation circuit, the operational amplifier 1312 sends a bias voltage Vb to the cascode transistor of the current-mode logic driver stage 133, and adjusts the bias voltage of the cascode transistor to adjust the current of the current-mode logic driver stage 133, so that the common mode level VCM differentially output by the current-mode logic driver stage 133 is equal to the reference voltage VREF set by the reference voltage generation circuit; therefore, the desired output swing of the current-mode logic driver stage 133 can be output only by adjusting the magnitude of VREF; the conventional structure is avoided, in which the output swing of the current-mode logic driving stage 133 is determined by the product of the current and the resistance;
if the actual process resistor is not calibrated, a large deviation exists, if the resistor deviation is generated, the accuracy of the output swing of the current mode logic driving stage 133 and the performance of output impedance matching are greatly reduced, the resistor array 132 consists of a resistor 1321 and a switch 1322, the switch 1322 receives a resistor calibration control code sent by the resistor calibration module, the switch is switched according to the control code, when a gate signal of the switch 1322 is a high level 1, the PMOS transistor is turned off, and the lower resistor does not play a role; when the grid signal of the switch 1322 is low level 0, the PMOS tube is opened, the resistors below are connected in parallel in the total resistor array, the final resistance value R is obtained by connecting all the resistors opened by the PMOS switch in parallel, and the accurate resistor can realize good impedance matching effect;
the current mode logic driving stage 133 is composed of a current mode logic driving stage 1331 for Pre-driving the Pre-serialization signal, a current mode logic driving stage 1332 for Pre-driving the Main serialization signal, and a current mode logic driving stage 1333 for Pre-driving the Post-Post serialization signal, so as to form the effect of a 3-order feed-forward equalizer; the signal input end of the output driving stage 130 based on the common mode feedback is connected with the high-speed serial signal driven by the Pre-driving stage 120, and the serial signal has three paths of signals, namely a Pre-driven Pre serialization signal, a Pre-driven Main serialization signal and a Pre-driven Post serialization signal; there is a delay of a unit interval between these three signals, these three signals will all access to the driving stage corresponding to the current-mode logic driving stage 133, but the weight of the current-mode logic driving stage connected to each signal is different, for the current-mode logic driving stage 1332 of the Main serialized signal after Pre-driving, its weight is 16, for the current-mode logic driving stage 1331 of the Pre-driven Pre serialized signal and the current-mode logic driving stage 1333 of the Post-Pre-driven Post-Post serialized signal, its weight has three stages 1,2,4; the balance gating switch receives gating switch setting input from outside, and current mode logic driving stages of Pre signals and Post signals of different balance gears can be added through the opening or closing of the switches from S1 to S6; if the third gear is completely turned off, no equalization effect exists, only the main path signal is output, and if the third gear is completely turned on, the maximum equalization effect is achieved; the Post-Pre-drive Pre-serialization signal, the Post-Pre-drive Main serialization signal and the Post-Pre-drive Post-serialization signal current mode logic driving stage are composed of input differential pair transistors, pre-charge pair transistors and cascode bias pair transistors, the grid electrodes of the input differential pair transistors are the signal input ends of the common mode feedback output driving stage 130, and are connected with the high-speed serial signals driven by the Pre-driving stage 120, the inputs of a Pre-serialization signal path are Vin1 and Vin2, the inputs of a Main serialization signal path are Vin3 and Vin4, and the inputs of a Post-serialization signal path are Vin5 and Vin6; the cascode tube biases the gate of the pair tube to be connected to the output bias voltage Vb of the operational amplifier 1312 to adjust the current of the current mode logic driving stage 133 so that the common mode level VCM differentially output by the current mode logic driving stage 133 is equal to the reference voltage VREF set by the reference voltage generating circuit; a Post-pre-drive Main serialized signal and a Post-pre-drive Post serialized signal.
In this embodiment, please refer to fig. 5; the continuous-time linear equalizer 150 includes an attenuator 151, a transconductance stage 152, and a transimpedance amplifier 153; the transmission characteristic of the channel 140 is low-pass, so that the low-frequency signal received by the receiver usually has a relatively large amplitude, and the attenuator 151 attenuates or amplifies ac signals of different frequencies to different extents according to the principle of ac source degradation; the conventional continuous-time linear equalizer 150 usually obtains higher high-frequency gain on a load by connecting an inductor and a resistor in series, so as to cancel the influence of the parasitic capacitance of the input of the later stage; however, in an integrated circuit, the use of inductors usually sacrifices a very large layout area; in the scheme, an active inductor is equivalently formed through the design of the transconductance stage 152 and the transimpedance amplifier 153, so that the bandwidth of people is expanded, and more flexibility is brought; the transconductance stage 152 mainly functions to convert an input voltage into a current through transistors in a PN complementary form, and here, output current is adjusted by adjusting the number of parallel circuits; the common-mode feedback is used for adjusting the bias voltage of the current tube to ensure that the output common mode of the final transimpedance amplifier 153 is positioned in the middle of the quantization voltage of the analog-to-digital converter, and the system is ensured to be in the best performance.
In this embodiment, please refer to fig. 6; the analog-to-digital converter 160 includes a four-channel successive approximation type analog-to-digital converter 161 and a frequency division by 8 circuit 162; the successive approximation type analog-to-digital converters 161 of the four channels receive the equalization signal sent by the continuous time linear equalizer 150; the four divide-by-8 circuits 162 receive the sampling clock from the clock and data recovery circuit 180, perform frequency division on the sampling clock, send the divided clock to the corresponding successive approximation analog-to-digital converter 161, and the successive approximation analog-to-digital converter 161 quantizes the equalized signal in sequence according to the frequency division clock and sends 32 quantized digital signals to the digital signal processing module 170.
In this embodiment, please refer to fig. 7; the digital signal processing module 170 includes a deserializer 171, a feed-forward equalizer 172, and a decision feedback equalizer 173; the deserializer 171 receives the 32 quantized signals from the adc 160 and deserializes them into 64 quantized signals; the feedforward equalizer 172 with 8 tap coefficients equalizes the 64 paths of quantized signals, sends the equalized 64 paths of quantized signals to the decision feedback equalizer 173, and sends the main tap and the coefficients of the previous tap and the next tap of the main tap to the feedforward equalizer tap coefficient adjustment module 200; the decision feedback equalizer 173 performs decision feedback equalization on the equalized 64 paths of quantized signals received from the feedforward equalizer 172, discriminates the signals, outputs the results of the decision, and transmits Data <1 > and Error <1 >.
In this embodiment, please refer to fig. 8; clock and data recovery circuit 180 includes Mueller-Muller phase detector 181, decimation module 182, and proportional path gain module 183, integral path gain module 184, frequency integrator 185, phase integrator 186, and phase interpolator 187; the Mueller-Muller phase detector 181 receives and judges the Data <1 > and Error <1 > signals transmitted from the digital signal processing module 170 to generate 64 channels of Up or Down signals, and the extraction module 182 extracts the 64 channels of Up or Down signals to extract 1 channel of Up or Down signals. The proportional path gain module 183, the integral path gain module 184 and the frequency integrator 185 combine to filter the 1 Up or Down signal; the phase integrator 186 integrates the filtered result to obtain the required phase selection of the phase interpolator 187; phase interpolator 187 interpolates the clock to generate 128 selectable phases in the form of octagon phase interpolation, and selects a phase according to the phase selection result to generate a corresponding sampling clock to be supplied to analog-to-digital converter 160.
In this embodiment, please refer to fig. 9; the clock circuit 190 includes a quadrature clock generation circuit 191, a duty cycle calibration circuit 192, a quadrature error calibration circuit 193, a duty cycle/quadrature error detection circuit 194, and duty cycle/quadrature error calibration logic 195; the quadrature clock generating circuit 191 receives an input reference clock and generates a four-phase quadrature clock, and the four-phase quadrature clock is calibrated by the duty ratio calibration circuit 192 and the quadrature error calibration circuit 193 to output a high-quality four-phase quadrature clock after calibration. Meanwhile, the four-phase quadrature clock is sent back to the duty ratio/quadrature error detection circuit 194 to detect the duty ratio and the quadrature error condition of the four-phase clock, and the detected result is sent to the duty ratio/quadrature mis-calibration logic 195, and the duty ratio/quadrature mis-calibration logic 195 performs judgment according to the detected result, so as to adjust the number of the switches of the duty ratio calibration circuit 192 and the quadrature error calibration circuit 193, and enable the output four-phase quadrature clock to have excellent duty ratio and quadrature performance.
In this embodiment, please refer to fig. 10; the feed forward equalizer tap coefficient adjustment module 200 includes a coefficient decoder 201; the coefficient decoder 201 receives the Pre1 tap coefficient, the Main tap coefficient and the Post1 tap coefficient from the feedforward equalizer 172 in the digital signal processing module 170, and converts the coefficients into switching signals of S1 to S6 in the output driver stage 130 with the feedforward equalizer at the transmitting end; the switching signals of S1-S3 are used for adjusting the balance size of the current mode logic driving stage 1331 of the Pre-driven Pre-serialization signal, and the switching signals of S4-S6 are used for adjusting the balance size of the current mode logic driving stage 1333 of the Pre-driven Post-serialization signal; the tap coefficient of the 3-order feedforward equalizer at the sending end is set to be consistent with the tap coefficient of the corresponding order of the feedforward equalizer at the receiving end, so that the feedforward equalization capability at the sending end is more suitable for the current loss condition of the channel 140, the feedforward equalization tap coefficient digitally realized at the receiving end does not need to provide the equalization capability, and the integral power consumption of the system is further reduced.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (8)
1. A joint optimization system for tap coefficients of a feedforward equalizer at a sending end and a receiving end is characterized in that: the system is applied on a chip (100), and the circuit in the chip (100) comprises: a serializer (110), a pre-drive stage (120), an output drive stage (130) with a feed-forward equalizer, a channel (140), a continuous-time linear equalizer (150), an analog-to-digital converter (160), a digital signal processing module (170), a clock and data recovery circuit (180), a clock circuit (190), and a feed-forward equalizer tap coefficient adjustment module (200);
the digital signal processing module (170) comprises a deserializer (171), a feed-forward equalizer (172) and a decision feedback equalizer (173);
the deserializer (171) receives 32 paths of quantized signals sent by the analog-to-digital converter (160) and deserializes the signals into 64 paths of quantized signals, the feedforward equalizer (172) with 8 tap coefficients equalizes the 64 paths of quantized signals, the equalized 64 paths of quantized signals are sent to the decision feedback equalizer (173), and meanwhile, the coefficients of the main tap and the former tap and the latter tap of the main tap are sent to the feedforward equalizer tap coefficient adjusting module (200), the decision feedback equalizer (173) conducts decision feedback equalization on the equalized 64 paths of quantized signals sent by the feedforward equalizer (172), judges the signals, outputs the judged result, and transmits Data <1 > and Error <1 > required by the clock and Data recovery circuit (180);
the feed-forward equalizer tap coefficient adjustment module (200) comprises a coefficient decoder (201);
the coefficient decoder (201) receives a Pre1 tap coefficient, a Main tap coefficient and a Post1 tap coefficient which are sent by a feedforward equalizer (172) in the digital signal processing module (170), and converts the coefficients into switching signals of S1-S6 in an output driving stage (130) with the feedforward equalizer at a sending end; the switching signals of S1-S3 are used for adjusting the equalization size of a current mode logic driving stage (1331) of the Pre-driven Pre-serialization signal, and the switching signals of S4-S6 are used for adjusting the equalization size of a current mode logic driving stage (1333) of the Pre-driven Post-serialization signal, so that the tap coefficient of a 3-order feedforward equalizer at the sending end is set to be consistent with the tap coefficient of the corresponding order of a feedforward equalizer at the receiving end.
2. The joint optimization system for the tap coefficients of the feedforward equalizer at the transmitting end and the receiving end according to claim 1, wherein: the serializer (110) comprises 64 to 4 serializing circuits (111), 4 to 1 serializing circuits (112), 3-order FIR generators (113) and frequency dividing circuits (114) supplying corresponding clocks to the serializing circuits;
the 64-to-4 serializing circuit (111) receives 64 paths of parallel data transmitted by a digital system and serializes the 64 paths of parallel data in sequence according to a clock signal, 4 paths of parallel signals after the serializing is finished are sent to the 4-to-1 serializing circuit (112), the 4-to-1 serializing circuit (112) continues to serialize the 4 paths of parallel signals transmitted by the 64-to-4 serializing circuit (111) into 1 path of serial signals, a Pre serializing signal, a Main serializing signal and a Post serializing signal are generated through a 3-order FIR generator, the frequency dividing circuit (114) receives a four-phase orthogonal clock sent by the clock circuit (190) and divides the four-phase orthogonal clock into 64-to-4 serializing circuits (111).
3. The joint optimization system for the tap coefficients of the feedforward equalizer at the transmitting end and the receiving end according to claim 2, wherein: the Pre-driving stage (120) Pre-drives a Pre-serialization signal, a Main serialization signal and a Post serialization signal, the Pre-driving stage (120) Pre-drives the Pre-serialization signal, the Main serialization signal and the Post serialization signal by adopting phase inverters with the size amplified step by step, each phase inverter consists of a PMOS tube and an NMOS tube, the sizes of the PMOS tubes of P1, P2, P3 and P4 are amplified step by step, the sizes of the NMOS tubes of N1, N2, N3 and N4 are amplified step by step, the size of the phase inverter consisting of P4 and N4 at the last stage can drive the last output stage, a feedback resistor Rf is added in a phase inverter chain to form the balance of a Sub-UI, and the rising speed of the output signal of the phase inverter is improved.
4. The joint optimization system for the tap coefficients of the feedforward equalizer at the transmitting end and the receiving end according to claim 3, wherein: the output driver stage (130) with feedforward equalizer comprises a common-mode feedback circuit (131), a resistor array (132) and a current-mode logic driver stage (133);
the common-mode feedback circuit (131) is composed of a common-mode extraction circuit (1311) and an operational amplifier (1312);
the common mode extraction circuit (1311) uses two resistors R to be placed between the differential output terminals Voutp and Voutn of the current-mode logic driver stage (133), extracts the common mode level VCM differentially output by the current-mode logic driver stage (133), and sends the common mode level VCM to the operational amplifier (1312) together with the reference voltage VREF set by the reference voltage generation circuit, the operational amplifier (1312) sends a bias voltage Vb to the cascode transistor of the current-mode logic driver stage (133), and adjusts the bias voltage of the cascode transistor to adjust the current of the current-mode logic driver stage (133), so that the common mode level differentially output by the current-mode logic driver stage (133) is equal to the reference voltage VREF set by the reference voltage generation circuit;
the resistor array (132) is composed of resistors (1321) and switches (1322);
the switch (1322) receives a resistance calibration control code sent by the resistance calibration module, the switch is switched according to the control code, when a grid signal of the switch (1322) is high level 1, the PMOS tube is switched off, the lower resistance does not act, when the grid signal of the switch (1322) is low level 0, the PMOS tube is switched on, the lower resistance is connected in parallel to the total resistance array, and the final resistance value R is obtained by connecting all the resistors switched on by the PMOS switch in parallel;
the current mode logic driving stage (133) consists of a current mode logic driving stage (1331) for Pre-driving a Pre-serialization signal, a current mode logic driving stage (1332) for Pre-driving a Main serialization signal and a current mode logic driving stage (1333) for Pre-driving a Post-Post serialization signal, and the effect of a 3-order feedforward equalizer is formed;
the signal input end of the output driving stage (130) with the feedforward equalizer is connected with a high-speed serial signal driven by the Pre-driving stage (120), and the serial signal has three paths of signals which are a Pre-driven Pre serialization signal, a Pre-driven Main serialization signal and a Pre-driven Post serialization signal respectively;
the balance gating switch receives the externally input gating switch setting, and the current mode logic driving stages of the Pre signal and the Post signal of different balance gears can be added through the opening or closing of the S1 to S6 switches.
5. The joint optimization system for the tap coefficients of the feedforward equalizer at the transmitting end and the receiving end according to claim 4, wherein: the continuous-time linear equalizer (150) comprises an attenuator (151), a transconductance stage (152) and a transimpedance amplifier (153);
the attenuator (151) attenuates or amplifies alternating current signals with different frequencies to different degrees according to the alternating current source electrode degradation principle, an active inductor is formed by the transconductance stage (152) and the transimpedance amplifier (153), the transconductance stage (152) converts input voltage into current through transistors in a PN complementary form, output current adjustment is performed in the mode of adjusting the parallel number of circuits, and finally the output common mode of the transimpedance amplifier (153) is ensured to be in the middle of the quantization voltage of the analog-to-digital converter through the common mode feedback adjustment of the bias voltage of a current tube.
6. The joint optimization system for the tap coefficients of the feedforward equalizer at the transmitting end and the receiving end according to claim 5, wherein: the analog-to-digital converter (160) comprises a four-channel successive approximation type analog-to-digital converter (161) and an 8-frequency division circuit (162);
the successive approximation type analog-to-digital converters (161) of the four channels receive an equalization signal sent by the continuous time linear equalizer (150), the four 8-division circuits (162) receive a clock and a sampling clock sent by the data recovery circuit (180), perform frequency division operation on the sampling clock, send the divided clock to the corresponding successive approximation type analog-to-digital converters (161), and the successive approximation type analog-to-digital converters (161) quantize the equalization signal in sequence according to the frequency division clock and send 32 paths of quantized digital signals to the digital signal processing module (170).
7. The joint optimization system for the tap coefficients of the feedforward equalizer at the transmitting end and the receiving end according to claim 6, wherein: said clock and data recovery circuit (180) comprises a Mueller-Muller phase detector (181), a decimation module (182) and a proportional path gain module (183), an integral path gain module (184), a frequency integrator (185), a phase integrator (186) and a phase interpolator (187);
the Mueller-Muller phase detector (181) receives Data <1 > and Error <1 > signals transmitted by the digital signal processing module (170) and judges the signals to generate 64 paths of Up or Down signals, the extraction module (182) extracts the 64 paths of Up or Down signals to extract 1 path of Up or Down signals, the proportional path gain module 183, the integral path gain module (184) and the frequency integrator (185) are combined to filter the 1 path of Up or Down signals, the phase integrator (186) integrates the filtering result to obtain the required phase selection of the phase interpolator (187), the phase interpolator (187) interpolates the clock in an octagonal phase interpolation form to generate 128 selectable phases, and selects the phase according to the phase selection result to generate a corresponding sampling clock to be sent to the analog-to-digital converter (160).
8. The joint optimization system for the tap coefficients of the feedforward equalizer at the transmitting end and the receiving end according to claim 7, wherein: the clock circuit (190) includes a quadrature clock generation circuit (191), a duty cycle calibration circuit (192), a quadrature error calibration circuit (193), a duty cycle/quadrature error detection circuit (194), and duty cycle/quadrature error calibration logic (195);
the quadrature clock generating circuit (191) receives an input reference clock and generates a four-phase quadrature clock, the four-phase quadrature clock outputs a calibrated high-quality four-phase quadrature clock after being calibrated by the duty ratio calibrating circuit (192) and the quadrature error calibrating circuit (193), the four-phase quadrature clock is sent back to the duty ratio/quadrature error detecting circuit (194), the duty ratio and the quadrature error of the four-phase clock are detected, the detected result is sent to the duty ratio/quadrature error calibrating logic (195), and the duty ratio/quadrature error calibrating logic (195) judges according to the detected result and further adjusts the number of the switching switches of the duty ratio calibrating circuit (192) and the quadrature error calibrating circuit (193).
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