CN115547981A

CN115547981A - Semiconductor packaging structure

Info

Publication number: CN115547981A
Application number: CN202111397813.5A
Authority: CN
Inventors: 刘兴治; 曾峥; 郭哲宏
Original assignee: MediaTek Inc
Current assignee: MediaTek Inc
Priority date: 2021-06-30
Filing date: 2021-11-19
Publication date: 2022-12-30
Also published as: TW202303904A; TWI764852B

Abstract

A semiconductor package structure includes a front-side rewiring layer, a stack structure, a back-side rewiring layer, a first IP core, and a second IP core. The stack structure is disposed over the front-side rewiring layer and includes a first semiconductor die and a second semiconductor die over the first semiconductor die. The back heavy wiring layer is configured on the stack structure. The first IP core is arranged in the stack structure and is electrically coupled with the front-side heavy wiring layer through a first routing channel. The second IP core is arranged in the stack structure and is electrically coupled with the rear redistribution layer through a second routing channel, wherein the second routing channel is separated from the first routing channel and is electrically insulated from the front redistribution layer.

Description

Semiconductor packaging structure

Technical Field

The present invention relates to semiconductor packaging technologies, and in particular, to a semiconductor package structure.

Background

As the demand for more functions and smaller devices increases, a package-on-package (PoP) technology of vertically stacking two or more packages becomes more and more popular. PoP technology reduces the line length between different components (e.g., controller and storage device). This provides better electrical performance because shorter interconnect wiring results in faster signal propagation and reduces noise and crosstalk defects.

While existing semiconductor package structures are generally adequate, they are not satisfactory in every aspect. For example, meeting the channel requirements for integrating different components into one package is a challenge. Therefore, there is a need for further improvements in semiconductor packaging structures to provide flexibility in channel design.

Disclosure of Invention

According to some embodiments, a semiconductor package structure is provided. The semiconductor packaging structure comprises a front-side rewiring layer, a stack structure, a rear-side rewiring layer, a first IP core and a second IP core. The stack structure is disposed over the front-side rewiring layer and includes a first semiconductor die and a second semiconductor die over the first semiconductor die. The rear heavy wiring layer is arranged above the stack structure. The first IP core is arranged in the stack structure and is electrically coupled to the front redistribution layer through a first routing channel. The second IP core is arranged in the stack structure and is electrically coupled with the rear redistribution layer through a second routing channel, wherein the second routing channel is separated from the first routing channel and is electrically insulated from the front redistribution layer.

According to some embodiments, a semiconductor wiring structure is provided. The semiconductor wiring structure comprises a first packaging structure, a first wiring channel and a second wiring channel. The first encapsulation structure has a front side and a back side and includes a stack structure having a first IP core and a second IP core. The first routing channel electrically couples the first IP core to a first redistribution layer on a front side of the first package structure. The second routing channel independently electrically couples the second IP core to a second redistribution layer on the back side of the first package structure, wherein the second routing channel is separate from the first routing channel and is electrically insulated from the first redistribution layer.

These and other objects of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures and drawings.

Drawings

The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements. When a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly indicated.

Fig. 1 is a cross-sectional view of an exemplary semiconductor package structure, in accordance with some embodiments;

2A-2D are cross-sectional views of stack structures in example semiconductor package structures, according to some embodiments;

fig. 3 is a cross-sectional view of an exemplary semiconductor package structure, in accordance with some embodiments;

fig. 4 is a cross-sectional view of an exemplary semiconductor package structure, in accordance with some embodiments;

fig. 5 is a cross-sectional view of an exemplary semiconductor package structure, in accordance with some embodiments;

fig. 6 is a cross-sectional view of an exemplary semiconductor package structure, in accordance with some embodiments; and

fig. 7 is a cross-sectional view of an example semiconductor package structure, according to some embodiments.

Detailed Description

The following description is of the best contemplated mode for carrying out the invention. This description is made for the purpose of illustrating the general principles of the present invention and should not be taken in a limiting sense. The scope of the invention is to be determined by reference to the appended claims.

The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and relative dimensions do not correspond to actual dimensions in the practice of the invention.

Semiconductor package structures and semiconductor wiring structures are described according to some embodiments of the present disclosure. The semiconductor package structure provides a separate routing channel for a device (device) and an IP core (e.g., a memory device and an IP core), so that the flexibility of the routing channel design can be improved.

Fig. 1 is a cross-sectional view of a semiconductor package structure 100 according to some embodiments of the present disclosure. Additional features may be added to the semiconductor package structure 100. Some of the features described below may be replaced or eliminated with respect to different embodiments. To simplify the illustration, only a portion of the semiconductor package structure 100 is shown.

As shown in fig. 1, the semiconductor package structure 100 includes a first package structure 100a and a second package structure 100b that are vertically stacked, according to some embodiments. The first package structure 100a has a front side (frontside) and a back side (backsside) opposite to the front side. The first package structure 100a has a first redistribution layer 102 on its front side and a second redistribution layer 124 on its back side. Accordingly, the first rewiring layer 102 may also be referred to as a front-side rewiring layer 102, and the second rewiring layer 124 may also be referred to as a rear-side rewiring layer 124.

The first redistribution layer 102 includes one or more conductive layers and passivation layers, where the one or more conductive layers may be disposed in the one or more passivation layers. The conductive layer may comprise a metal, such as copper, titanium, tungsten, aluminum, or the like, or combinations thereof. In some embodiments, the passivation layer includes a polymer layer, such as Polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy, and the like, or a combination thereof. Alternatively, the passivation layer may include a dielectric layer, such as silicon oxide, silicon nitride, silicon oxynitride, the like, or combinations thereof. The material of the second redistribution layer 124 may be similar to that of the first redistribution layer 102, and is not described herein again.

As shown in fig. 1, first redistribution layer 102 includes more conductive and passivation layers than second redistribution layer 124, according to some embodiments. The first redistribution layer 102 may be thicker than the second redistribution layer 124, but the disclosure is not limited thereto. For example, second redistribution layer 124 may be thicker than or substantially equal to first redistribution layer 102.

In some embodiments, the first package structure 100a includes a plurality of conductive structures 104 located below the first redistribution layer 102 and electrically coupled to the first redistribution layer 102. In some embodiments, the conductive structures 104 comprise a conductive material, e.g., the metallic conductive structures 104 may comprise micro-bumps, controlled collapse chip connection (C4) bumps, ball Grid Array (BGA) balls, or the like, or combinations thereof.

In some embodiments, the first package structure 100a includes a stacked structure including a first semiconductor die 106 and a second semiconductor die 112 vertically stacked above the first redistribution layer 102. According to some embodiments, the first semiconductor die 106 and the second semiconductor die 112 each independently package a system-on-a-chip device (SoC), a logic device, a memory device, a Radio Frequency (RF) device, the like, or any combination thereof. For example, the first semiconductor die 106 and the second semiconductor die 112 may each independently include a Micro Control Unit (MCU) die, a microprocessor unit (MPU) die, a Power Management Integrated Circuit (PMIC) die, a Global Positioning System (GPS) device, a Central Processing Unit (CPU) die, a Graphics Processing Unit (GPU) die, an Input Output (IO) die, a Dynamic Random Access Memory (DRAM) IP core, a Static Random Access Memory (SRAM), a High Bandwidth Memory (HBM), or the like, or any combination thereof.

Although two semiconductor dies, first semiconductor die 106 and second semiconductor die 112, are shown in fig. 1, more than two semiconductor dies are possible. For example, the stack structure may include three semiconductor dies stacked vertically. Alternatively, the stack structure can include four semiconductor dies, wherein two semiconductor dies are vertically stacked above one semiconductor die and another semiconductor die is disposed above the semiconductor die and adjacent to the two semiconductor dies. In some embodiments, the stack structure further includes one or more passive components (not shown), such as resistors, capacitors, inductors, and the like, or combinations thereof.

Referring to fig. 1, a first semiconductor die 106 includes a plurality of vias 108 electrically coupled to the first redistribution layer 102. The vias 108 may be formed of a conductive material such as a metal. For example, the vias 108 may be formed of copper. In fig. 1, the via 108 has substantially vertical sidewalls and extends from the top surface of the first semiconductor die 106 to the bottom surface of the first semiconductor die 106, although the disclosure is not limited thereto. The vias 108 in the first semiconductor die 106 can have other configurations and numbers.

In some embodiments, the first package structure 100a includes a third redistribution layer 110 between the first redistribution layer 102 and the second redistribution layer 124. As shown in fig. 1, the third redistribution layer 110 may be disposed between the top surface of the first semiconductor die 106 and the bottom surface of the second semiconductor die 112, and may extend beyond the sidewalls of the first semiconductor die 106 and the sidewalls of the second semiconductor die 112. The third redistribution layer 110 may be electrically coupled to the first semiconductor die 106, the vias 108 in the first semiconductor die 106, and the second semiconductor die 112.

The material of the third redistribution layer 110 may be similar to that of the first redistribution layer 102, and is not described herein again. As shown in fig. 1, the first rewiring layer 102 includes more conductive and passivation layers than the third rewiring layer 110, and the third rewiring layer 110 includes more conductive and passivation layers than the second rewiring layer 124, but the present disclosure is not limited thereto. For example, the second redistribution layer 124 may include more conductive and passivation layers than the first and third redistribution layers 102 and 110.

By providing the third redistribution layer 110, additional routing channels can be formed between the first semiconductor die 106 and the second semiconductor die 112, which facilitates layout planning flexibility and saves die bump fan-out width, as described below and illustrated in fig. 2A-2D.

Fig. 2A is a cross-sectional view of a stack structure 200a in the semiconductor package structure 100, according to some embodiments. For simplicity, only a portion of the stack structure 200a is shown. In some embodiments, the stack structure 200a includes a first semiconductor die 106 and a second semiconductor die 112.

The first semiconductor die 106 has an active surface 106a and a back surface 106b opposite to the active surface 106a. The second semiconductor die 112 has an active surface 112a and a backside surface 112b opposite to the active surface 112 a. The first semiconductor die 106 and the second semiconductor die 112 may be stacked face-to-face (FtF). That is, the active surface 112a of the second semiconductor die 112 is proximate to the active surface 106a of the first semiconductor die 106.

Referring to fig. 2A, a first Intellectual Property (IP) core 101 and a second IP core 103 may be disposed on an active surface 106a of a first semiconductor die 106. In some embodiments, first IP core 101 is used to control second package structure 100b (shown in fig. 1), and second IP core 103 is used to control other components electrically coupled to first redistribution layer 102.

According to some embodiments, since the third redistribution layer 110 is disposed between the first semiconductor die 106 and the second semiconductor die 112, an additional routing channel may be formed therebetween. Thus, signals from first IP core 101 and signals from second IP core 103 may pass through different trace channels, e.g., as shown by

paths

101P and 103P, respectively. Specifically, the trace channel of first IP core 101 (represented by path 101P) may pass through third redistribution layer 110 (shown in fig. 1), and the trace channel of second IP core 103 (represented by path 103P) may pass through via 108 in first semiconductor die 106 and first redistribution layer 102 (shown in fig. 1).

That is, compared with the case where the routing channel of first IP core 101 and the routing channel of second IP core 103 both pass through first redistribution layer 102, the present invention provides respective routing channels for first IP core 101 and second IP core 103. In this way, the routing channels can be optimized individually to meet different channel requirements. In addition, the routing channel of first IP core 101 does not affect the routing channel of second IP core 103, thereby increasing the flexibility of channel design.

As shown in fig. 2A, the first IP core 101 and the second IP core 103 are separately disposed side by side, but the disclosure is not limited thereto. For example, according to some other embodiments, the first IP core 101 may be placed in the second IP core 103. Alternatively, first IP core 101 and second IP core 103 can be disposed near different edges of first semiconductor die 102. In addition, there may be more than two IP cores.

Fig. 2B is a cross-sectional view of a stack structure 200B in the semiconductor package structure 100, according to some embodiments. To simplify the figure, only a portion of the stack structure 200b is shown. The stack structure 200b may include the same or similar components as the stack structure 200a shown in fig. 2A, and for simplicity, those components will not be discussed in detail. In the following embodiments, the first IP core 101 is disposed on the active surface 112a of the second semiconductor die 112, and the second IP core 103 is disposed on the active surface 106a of the first semiconductor die 106.

As shown in fig. 2B, signals from first IP core 101 and signals from second IP core 103 may pass through different trace channels, e.g., as shown by path 101P and path 103P, respectively. Specifically, the trace channel of first IP core 101 (represented by path 101P) may pass through third redistribution layer 110 (shown in fig. 1), and the trace channel of second IP core 103 (represented by path 103P) may pass through via 108 in first semiconductor die 106 and first redistribution layer 102 (shown in fig. 1).

Fig. 2C is a cross-sectional view of a stack structure 200C in the semiconductor package structure 100, according to some embodiments. For simplicity of the schematic, only a portion of the stack structure 200c is shown. The stack structure 200c may include the same or similar components as the stack structure 200a shown in fig. 2A, and for simplicity those components will not be discussed in detail. In the following embodiments, the first semiconductor die 106 and the second semiconductor die 112 may face to back (FtB) stacks. That is, the active surface 112a of the second semiconductor die 112 is proximate to the backside surface 106b of the first semiconductor die 106.

As shown in fig. 2C, the first IP core 101 and the second IP core 103 are disposed on the active surface 106a of the first semiconductor die 106. Signals from first IP core 101 and signals from second IP core 103 may pass through different routing channels. E.g., indicated by path 101P and path 103P, respectively. Specifically, a routing channel (represented by path 101P) of first IP core 101 can pass through via 108 and third redistribution layer 110 in first semiconductor die 106 (as shown in fig. 1), and a routing channel (represented by path 103P) of second IP core 103 can pass through first redistribution layer 102 (as shown in fig. 1).

Fig. 2D is a cross-sectional view of a stack structure 200D in the semiconductor package structure 100, according to some embodiments. To simplify the illustration, only a portion of the stack structure 200d is shown. The stack structure 200d may include the same or similar components as the stack structure 200a shown in fig. 2A and for simplicity those components will not be discussed in detail. In the following embodiments, the first IP core 101 is disposed on the active surface 112a of the second semiconductor die 112, and the second IP core 103 is disposed on the active surface 106a of the first semiconductor die 106.

As shown in fig. 2D, signals from first IP core 101 and signals from second IP core 103 may pass through different trace channels, e.g., as shown by path 101P and path 103P, respectively. Specifically, the trace channel of first IP core 101 (represented by path 101P) may pass through third rerouting layer 110 (shown in fig. 1), and the trace channel of second IP core 103 (represented by path 103P) may pass through first rerouting layer 102 (shown in fig. 1).

Referring to fig. 1, a plurality of conductive structures 114 are formed between the third redistribution layer 110 and the second semiconductor die 112, according to some embodiments. The conductive structure 114 may electrically couple the second semiconductor die 112 to the third redistribution layer 110. The trace channels can also include conductive structures 114 depending on the trace channel design and the location of the IP cores.

In some embodiments, the conductive structure 114 includes a conductive material, such as a metal. The conductive structures 114 may include micro-bumps, controlled collapse chip connection (C4) bumps, ball Grid Array (BGA) balls, and the like, or combinations thereof.

In some embodiments, an underfill material 116 is formed between the second semiconductor die 112 and the third redistribution layer 110 and fills the gaps between the conductive structures 114 to provide structural support. An underfill material 116 may surround each conductive structure 114. In some embodiments, the underfill material 116 is formed of a polymer, such as an epoxy. After forming the conductive structure 114 between the second semiconductor die 112 and the third redistribution layer 110, the underfill material 116 may be applied by capillary force. The underfill material 116 may then be cured by any suitable curing process.

As shown in fig. 1, the first package structure 100a includes a molding material 118 surrounding the second semiconductor die 112 and the underfill material 116, and covering a portion of the top surface of the third redistribution layer 110. In some embodiments, the molding material 118 abuts sidewalls of the second semiconductor die 112 and a top surface of the third redistribution layer 110. The molding material 118 can protect the second semiconductor die 112 from the environment, thereby preventing damage to the second semiconductor die 112 due to, for example, stress, chemicals, and/or moisture.

The molding material 118 may include a non-conductive material such as a moldable polymer, epoxy, resin, or the like, or combinations thereof. In some embodiments, the molding material 118 is applied in a liquid or semi-liquid form and then cured by any suitable curing process, such as a thermal curing process, a UV curing process, or the like, or combinations thereof. The molding material 118 may be shaped or molded with a mold (not shown).

The molding material 118 can then be partially removed by a planarization process, such as Chemical Mechanical Polishing (CMP), until the top surface of the second semiconductor die 112 is exposed. In some embodiments, the top surface of the molding material 118 and the top surface of the second semiconductor die 112 are substantially coplanar. As shown in fig. 1, the sidewalls of the molding material 118 can be coplanar with the sidewalls of the first semiconductor die 106.

In some embodiments, a plurality of conductive pillars 120 are formed adjacent the stacked structure (including the first semiconductor die 106 and the second semiconductor die 112) and the molding material 118. Conductive pillars 120 may include metal pillars, such as copper pillars, for example. In some embodiments, conductive pillars 120 are formed by an electroplating process or any other suitable process. As shown in fig. 1, conductive pillars 120 may have substantially vertical sidewalls.

As shown in fig. 1, the conductive pillars 120 may be disposed between the first and second redistribution layers 102 and 124, and may be disposed on the top and bottom surfaces of the third redistribution layer 110. Conductive pillars 120 may be electrically coupled to first redistribution layer 102, second redistribution layer 124, and third redistribution layer 110.

The position and number of the conductive pillars 120 may be adjusted according to the trace design of the first package structure 100 a. For example, in some other embodiments, conductive pillars 120 are disposed between second redistribution layer 124 and third redistribution layer 110, but not between first redistribution layer 102 and third redistribution layer 110. The second redistribution layer 124 is electrically coupled to the third redistribution layer 110 through the conductive pillars 120, and the third redistribution layer 110 is electrically coupled to the first redistribution layer 102 through the vias 108 in the first semiconductor die 106.

As shown in fig. 1, four conductive pillars 120 are disposed on opposite sides of the stack structure, but the disclosure is not limited thereto. For example, the number of conductive pillars 120 on opposite sides of the stack structure may be different. Alternatively, conductive pillars 120 may be disposed on one side of the stack structure.

As shown in fig. 1, the first package structure 100a includes a molding material 122 surrounding the stack structure (including the first semiconductor die 106 and the second semiconductor die 112), the molding material 118, and the conductive pillar 120. Molding material 122 may fill conductive pillars 120 and gaps between the stack structure and conductive pillars 120.

As shown in fig. 1, the molding material 122 abuts sidewalls of the first semiconductor die 106 and the molding material 118 and covers a top surface of the first redistribution layer 102, a bottom surface of the second redistribution layer 124, and top and bottom surfaces of the third redistribution layer 110. Molding material 122 may protect the stack structure and conductive pillars 120 from the environment, thereby preventing damage to the stack structure and conductive pillars 120 due to, for example, stress, chemicals, and/or moisture.

In some embodiments, the molding material 122 comprises a non-conductive material, such as a moldable polymer, epoxy, resin, or the like, or combinations thereof. In some embodiments, the molding material 122 is applied in a liquid or semi-liquid form and then cured by any suitable curing process, such as a thermal curing process, a UV curing process, or the like, or combinations thereof. The molding material 122 may be shaped or molded with a mold (not shown).

The molding material 122 may then be partially removed by a planarization process, such as Chemical Mechanical Polishing (CMP), until the top surfaces of the conductive pillars 120 are exposed. In some embodiments, the top surfaces of the molding material 122 and the conductive pillars 120 are substantially coplanar. As shown in the figure. As shown in fig. 1, sidewalls of the molding material 122 may be coplanar with at least one of sidewalls of the first, second, and third redistribution layers 102, 124, and 110.

As shown in fig. 1, a second redistribution layer 124 may be disposed over the stack structure and cover the top surface of the second semiconductor die 112, the top surface of the conductive pillar 120, and the top surface of the molding material 122.

As shown in fig. 1, according to some embodiments, the second package structure 100b is disposed over the first package structure 100a and is electrically coupled to the second redistribution layer 124 through a plurality of conductive structures 126. In some embodiments, conductive structure 126 comprises a conductive material, such as a metal. The conductive structures 126 may include micro-bumps, controlled collapse chip connection (C4) bumps, ball Grid Array (BGA) balls, and the like, or combinations thereof.

As shown in fig. 1, the second package structure 100b includes a substrate 128, according to some embodiments. The substrate 128 may have a wiring structure therein. In some embodiments, the routing structure of the substrate 128 includes conductive layers, conductive vias, conductive pillars, the like, or combinations thereof. The wiring structure of the substrate 128 may be formed of a metal, such as copper, titanium, tungsten, aluminum, or the like, or a combination thereof.

The wiring structure of the substrate 128 may be disposed in an inter-metal dielectric (IMD) layer. In some embodiments, the IMD layer may be formed of an organic material (e.g., a polymer substrate), a non-organic material (e.g., silicon nitride, silicon oxide, silicon oxynitride, etc.), or a combination thereof. Any desired semiconductor components may be formed in the substrate 128 and on the substrate 128. However, for simplicity of illustration, only the planar substrate 128 is shown.

As shown in fig. 1, the second package structure 100b includes

semiconductor components

130 and 132 over a substrate 128, according to some embodiments.

Semiconductor devices

130 and 132 may include a memory die such as a Dynamic Random Access Memory (DRAM). For example, the

semiconductor devices

130 and 132 may be Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) dies for mobile systems. In embodiments where the second package structure 100b includes a memory device, the IP core (e.g., the first IP core 101) for the second package structure 100b may be referred to as a memory IP core.

Semiconductor components

130 and 132 may include the same or different devices. In some embodiments, the second package structure 100b further includes one or more passive components (not shown), such as resistors, capacitors, inductors, and the like, or combinations thereof.

First IP core 101 in the stack structure (shown in fig. 2A-2D) may be electrically coupled to second package structure 100b by a first routing channel that includes third redistribution layer 110, conductive pillars 120, and second redistribution layer 124. A second IP core 103 in the stack structure (as shown in fig. 2A-2D) may be electrically coupled to conductive structure 104 through a second routing channel that includes first rerouting layer 110. In an embodiment, depending on the location of the IP core, the first routing channel or the second routing channel can also include the via 108 and/or the conductive structure 114 in the first semiconductor die 106, as described above.

In other words, the routing channels between the IP core and second package structure 100b may be separated from other routing channels, such as a routing channel between another IP core and conductive structure 104. Specifically, according to some embodiments, the routing channel between the IP core and the second package structure 100b is electrically insulated from the first redistribution layer 110. Therefore, different routing channels can be optimized respectively, and the flexibility of channel design is increased.

Fig. 3 is a cross-sectional view of a semiconductor package structure 300 according to some embodiments of the present disclosure. It is noted that the semiconductor package structure 300 may include the same or similar components as the semiconductor package structure 100 shown in fig. 1. For simplicity, these components will not be discussed in detail. In the following embodiments, the routing channel includes a conductive pillar 134 over the first semiconductor die 106 and adjacent to the second semiconductor die 112.

According to some embodiments, the conductive pillars 134 are electrically coupled to the second redistribution layer 124, the first semiconductor die 106, and the vias 108 in the first semiconductor die 106. In embodiments where the IP core for the second package structure 100b is formed at the bottom of the first semiconductor die 106, the routing channel between the IP core and the second package structure 100b can include the vias 108 in the first semiconductor die 106, the conductive pillars 134, and the second redistribution layer 124. In embodiments where an IP core for the second package structure 100b is formed on top of the first semiconductor die 106, the routing channel between the IP core and the second package structure 100b includes the conductive pillars 134 and the second redistribution layer 124.

Conductive pillars 134 may comprise metal pillars, such as copper pillars. In some embodiments, conductive pillars 134 are formed by an electroplating process or any other suitable process. Conductive pillars 134 may have substantially vertical sidewalls. As shown in fig. 3, the conductive pillars 134 may be surrounded by the molding material 118. The conductive pillars 134 may have substantially vertical sidewalls and may extend from a bottom surface of the molding material 118 to a top surface of the molding material 118.

The positions and the number of the conductive pillars 134 may be adjusted according to the wiring design of the first package structure 100 a. For example, more than one conductive pillar 134 can be disposed over the first semiconductor die 106 and can be disposed adjacent to one side or an opposite side of the second semiconductor die 112. In addition, the semiconductor package structure 300 may further include one or more redistribution layers, such as the third redistribution layer 110 in fig. 1.

Fig. 4 is a cross-sectional view of a semiconductor package structure 400 according to some embodiments of the present disclosure. It is noted that the semiconductor package structure 400 may include the same or similar components as the semiconductor package structure 100 shown in fig. 1. For simplicity, these components will not be discussed in detail. In the following embodiments, the routing channel includes a via 136 in the second semiconductor die 112.

The vias 136 can be electrically coupled to the second redistribution layer 124, the conductive structure 114, the first semiconductor die 106, and the vias 108 in the first semiconductor die 106. In embodiments where the IP core for the second package structure 100b is formed at the bottom of the first semiconductor die 106, the routing channel between the IP core and the second package structure 100b may include the via 108, the conductive structure 114, the via 136, and the second redistribution layer 124 in the first semiconductor die 106. In embodiments where an IP core for the second package structure 100b is formed on top of the first semiconductor die 106, the routing channel between the IP core and the second package structure 100b may include the conductive structure 114, the via 136, and the second rerouting layer 124.

In embodiments where the IP core for the second package structure 100b is formed at the bottom of the second semiconductor die 112, the routing channel between the IP core and the second package structure 100b may include the via 136 and the second redistribution layer 124. In embodiments where the IP core for the second package structure 100b is formed on top of the second semiconductor die 112, the routing channel between the IP core and the second package structure 100b may include the second redistribution layer 124 and the vias 136 may be omitted.

In these embodiments, the routing channels between the second redistribution layer 124 and the IP core do not extend beyond the first semiconductor die 106 and the second semiconductor die 112. In particular, the routing channel between the second redistribution layer 124 and the IP core passes through the area shielded by the first semiconductor die 106 and/or the second semiconductor die 112.

Vias 136 may be formed of any conductive material, such as a metal. For example, the vias 136 are formed of copper. As shown in fig. 4, the via 136 may have substantially vertical sidewalls and may extend from the top surface of the second semiconductor die 112 to the bottom surface of the second semiconductor die 112, although the disclosure is not limited thereto. The vias 136 in the second semiconductor die 112 can have other configurations.

The positions and the number of the through holes 136 may be adjusted according to the wiring design of the first package structure 100 a. For example, more than one via 136 may be provided in the second semiconductor die 112. Alternatively, the semiconductor package structure 400 may further include one or more redistribution layers (e.g., the third redistribution layer 110 in fig. 1) and/or one or more conductive pillars (e.g., the conductive pillars 134 in fig. 3).

Fig. 5 is a cross-sectional view of a semiconductor package structure 500 according to some embodiments of the present disclosure. It is noted that the semiconductor package structure 500 may include the same or similar components as the semiconductor package structure 100 shown in fig. 1. For simplicity, these components will not be discussed in detail. In the following embodiments, the larger first semiconductor die 106 is disposed over the smaller second semiconductor die 112.

As shown in fig. 5, the second semiconductor die 112 can include a plurality of vias 138 that can be electrically coupled to the first redistribution layer 102, the conductive structures 114, and the vias 108 in the first semiconductor die 106. Vias 138 may be formed of any conductive material, such as a metal. For example, the via 138 may be formed of copper. As shown in fig. 5, the vias 138 can each have substantially vertical sidewalls and can extend from the top surface of the second semiconductor die 112 to the bottom surface of the second semiconductor die 112. However, the vias 138 in the second semiconductor die 112 may have other configurations and numbers.

The vias 138 can be electrically coupled to the first redistribution layer 102, the conductive structures 114, the first semiconductor die 106, and the vias 108 in the first semiconductor die 106. In embodiments where the IP core for the second package structure 100b is formed at the bottom of the second semiconductor die 112, the routing channel between the IP core and the second package structure 100b can include the via 138 in the second semiconductor die 112, the conductive structure 114, the via 108 in the first semiconductor die 106, and the second redistribution layer 124. In embodiments where the IP core for the second package structure 100b is formed on top of the second semiconductor die 112, the routing channel between the IP core and the second package structure 100b can include the conductive structure 114, the via 108 in the first semiconductor die 106, and the second redistribution layer 124.

In embodiments where the IP core for the second package structure 100b is formed at the bottom of the first semiconductor die 106, the routing channel between the IP core and the second package structure 100b may include the via 108 in the first semiconductor die 106 and the second redistribution layer 124. In embodiments where the IP core for the second package structure 100b is formed on top of the first semiconductor die 106, the routing channel between the IP core and the second package structure 100b may include the second redistribution layer 124 and the vias 108 may be omitted.

As shown in fig. 5, the first package structure 100a can include one or more conductive pillars 140 under the first semiconductor die 106 and adjacent to the second semiconductor die 112. Conductive posts 140 are optional. The conductive posts 140 may include metal posts, such as copper posts. In some embodiments, conductive pillars 140 are formed by an electroplating process or any other suitable process.

The conductive pillars 140 may be electrically coupled to the first redistribution layer 102, the first semiconductor die 106, and the vias 108 of the first semiconductor die 106. Referring to fig. 5, each conductive post 140 may have substantially vertical sidewalls. The conductive pillars 140 may be surrounded by the molding material 118 and extend from a top surface of the molding material 118 to a bottom surface of the molding material 118.

The positions and the number of the conductive pillars 140 may be adjusted according to the wiring design of the first package structure 100 a. As shown in fig. 5, two conductive pillars 140 are disposed adjacent to opposite sides of the second semiconductor die 112, but the disclosure is not limited thereto. For example, the number of conductive pillars 140 on opposite sides of the stack structure may be different. Alternatively, the conductive pillars 140 may be disposed at one side of the stack structure.

Fig. 6 is a cross-sectional view of a semiconductor package structure 600 according to some embodiments of the present disclosure. It is noted that the semiconductor package structure 600 may include the same or similar components as the semiconductor package structure 100 shown in fig. 1. For simplicity, these components will not be discussed in detail. In the following embodiment, the stack structure includes a plurality of

semiconductor components

142, 144, 146 located above the first semiconductor die 106 and adjacent to the second semiconductor die 112.

The

semiconductor components

142, 144, 146 may include active components. For example, the

semiconductor components

142, 144, 146 may each independently include a system-on-a-chip device (SoC), a logic device, a memory device, a Radio Frequency (RF) device, etc., or any combination thereof. For example, the

semiconductor components

142, 144, 146 may each independently include a Micro Control Unit (MCU) device, a microprocessor unit (MPU) device, a Power Management Integrated Circuit (PMIC) device, a Global Positioning System (GPS) device, a Central Processing Unit (CPU) die, a Graphics Processing Unit (GPU) die, an Input Output (IO) die, a Dynamic Random Access Memory (DRAM) IP core, a Static Random Access Memory (SRAM), a High Bandwidth Memory (HBM), etc., or any combination thereof.

In some other embodiments, the

semiconductor components

142, 144, 146 include passive components, such as resistors, capacitors, inductors, and the like, or combinations thereof. The

semiconductor components

142, 144, 146 may include the same or different devices.

The

semiconductor elements

142, 144, 146 may be electrically coupled to the first semiconductor die 106. Each of the

semiconductor components

142, 144, 146 may be surrounded and covered by the molding material 118. It should be noted that the locations and numbers of the

semiconductor assemblies

142, 144, 146, the first semiconductor die 106, and the second semiconductor die 112 are merely exemplary, and the disclosure is not limited thereto.

For example, the

semiconductor components

142, 144, 146 may be vertically stacked. Alternatively, the stack structure may include two semiconductor components stacked vertically. In other embodiments, the stack structure may include four semiconductor devices, wherein two semiconductor devices are vertically stacked above one semiconductor device and another semiconductor device is disposed above the one semiconductor device and adjacent to the two semiconductor devices.

The semiconductor package structure 600 may further include one or more redistribution layers (e.g., the third redistribution layer 110 in fig. 1), one or more conductive pillars (e.g., the conductive pillars 134 in fig. 3), and/or one or more vias (e.g., the vias 136 in fig. 4) in the semiconductor chip according to the routing design of the first package structure 100 a.

Fig. 7 is a cross-sectional view of a semiconductor package structure 700 according to some embodiments of the present disclosure. It is noted that the semiconductor package structure 700 may include the same or similar components as the semiconductor package structure 600 shown in fig. 6. For simplicity, these components will not be discussed in detail. In the following embodiment, the stack structure includes a plurality of

semiconductor components

142, 144, 146 below the first semiconductor die 106 and adjacent to the second semiconductor die 112.

The

semiconductor devices

142, 144, 146 may be similar to the

semiconductor devices

142, 144, 146 in fig. 6, and thus are not described herein again. The

semiconductor devices

semiconductor components

142, 144, 146 may be surrounded and covered by the molding material 118. It should be noted that the numbers and positions of the

semiconductor elements

142, 144, 146, the first semiconductor die 106 and the second semiconductor die 112 in the present embodiment are merely illustrative, and the disclosure is not limited thereto.

For example, the

semiconductor components

142, 144, 146 may be vertically stacked. Alternatively, the stack structure may include two semiconductor components stacked vertically. In other embodiments, the stacked structure may include four semiconductor devices, wherein two semiconductor devices are vertically stacked above one semiconductor device and another semiconductor device is disposed above and adjacent to the two semiconductor devices.

The semiconductor package structure 700 may further include one or more redistribution layers (e.g., the third redistribution layer 110 in fig. 1), one or more conductive pillars (e.g., the conductive pillars 134 in fig. 3), and/or one or more vias (e.g., the vias 136 in fig. 4) in the semiconductor die according to the routing design of the first package structure 100 a.

In summary, by providing one or more redistribution layers, one or more conductive pillars, and/or one or more vias in a semiconductor die in a package structure, a separate routing channel from an IP core in the package structure to another package structure can be achieved. Therefore, the routing channels can be optimized independently, and the flexibility of channel design is increased.

While the invention has been described by way of examples and preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (which will be apparent to those skilled in the art). Accordingly, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims

1. A semiconductor package structure, comprising:

a front heavy wiring layer;

a stack structure disposed over the front-side redistribution layer and including a first semiconductor die and a second semiconductor die over the first semiconductor die;

a back heavy wiring layer disposed on the stack structure;

a first IP core disposed in the stack structure and electrically coupled to the front redistribution layer through a first routing channel; and

and a second IP core arranged in the stack structure and electrically coupled to the rear redistribution layer through a second routing channel, wherein the second routing channel is separated from the first routing channel and is electrically insulated from the front redistribution layer.

2. The semiconductor package according to claim 1, further comprising a package structure disposed above the backside redistribution layer and electrically coupled to the second IP core through the second routing channel.

3. The semiconductor package structure according to claim 1, wherein the second trace path includes:

a conductive post adjacent to the stack structure and electrically coupled to the backside redistribution layer; and

a third redistribution layer located between the top surface of the first semiconductor die and the bottom surface of the second semiconductor die and electrically coupled to the conductive pillar.

4. The semiconductor package structure of claim 3, wherein the second trace path further comprises a plurality of vias in the first semiconductor die.

5. The semiconductor package according to claim 3, further comprising a molding material surrounding the conductive pillars and the stack structure, wherein sidewalls of the molding material are coplanar with sidewalls of the third redistribution layer.

6. The semiconductor package structure of claim 1, wherein the second trace channel comprises a conductive pillar disposed above the first semiconductor die and adjacent to the second semiconductor die.

7. The semiconductor package according to claim 6, further comprising a molding material surrounding the conductive pillar and the second semiconductor die, wherein sidewalls of the molding material are coplanar with sidewalls of the first semiconductor die.

8. The semiconductor package structure of claim 6, wherein the second trace path further comprises a via in the first semiconductor die.

9. The semiconductor package structure of claim 1, wherein the second routing channel comprises a first via in the second semiconductor die.

10. The semiconductor package structure of claim 9, wherein the second routing channel further comprises a second via in the first semiconductor die.

11. The semiconductor package according to claim 1, further comprising a conductive pillar disposed below the second semiconductor die and adjacent to the first semiconductor die, wherein the conductive pillar electrically couples the second semiconductor die to the front-side redistribution layer.

12. The semiconductor package according to claim 11, further comprising a molding material surrounding the conductive pillar and the first semiconductor die, wherein sidewalls of the molding material are coplanar with sidewalls of the second semiconductor die.

13. The semiconductor package structure of claim 1, wherein the second trace path passes through a region shielded by the first semiconductor die and/or the second semiconductor die.

14. A semiconductor wiring structure comprising:

a first package structure having a front side and a back side and comprising a stack structure having a first IP core and a second IP core;

a first routing channel electrically couples the first IP core to a first redistribution layer located on a front side of the first package structure; and

a second routing channel independently electrically couples the second IP core to a second redistribution layer located on the back side of the first package structure, wherein the second routing channel is separate from and electrically insulated from the first routing channel.

15. The semiconductor wiring structure of claim 14, further comprising a second encapsulation structure disposed on the second redistribution layer, wherein the second encapsulation structure receives the control signal from the second IP core through the second routing channel.

16. The semiconductor wiring structure of claim 14, wherein the stack structure comprises a first semiconductor die and a second semiconductor die stacked vertically, and the first IP core and the second IP core are each independently disposed in the first semiconductor die or the second semiconductor die.

17. The semiconductor wiring structure of claim 16, wherein the second wiring channel is included in the first semiconductor die and electrically couples the second semiconductor die to the second semiconductor die

A via of the redistribution layer.

18. The semiconductor wiring structure of claim 16, wherein the second wiring via comprises a conductive pillar adjacent the first semiconductor die and electrically coupling the second semiconductor die to the second redistribution layer.

19. The semiconductor wiring structure of claim 16, wherein the second wiring channel comprises a third redistribution layer extending between the first semiconductor die and the second semiconductor die.

20. The semiconductor wiring structure of claim 19, wherein the second routing channel comprises a conductive pillar adjacent to the stack structure and electrically coupling the second redistribution layer and the third redistribution layer.