CN115541068A - Pressure sensor and method for manufacturing the same - Google Patents

Abstract

The application discloses a pressure sensor and a manufacturing method thereof, wherein the pressure sensor comprises a substrate, the substrate comprises a first capacitor area, a first doping area is formed in the substrate within a preset depth range of the first capacitor area, the first doping area is used as a first polar plate of a first capacitor, and a first cavity is arranged in the substrate; the second polar plate is arranged on one side of the substrate, in the orthographic projection of the substrate, the first polar plate, the second polar plate and the first cavity are at least partially overlapped, and the first cavity is positioned between the first polar plate and the second polar plate. According to the scheme, the substrate is doped to form the first polar plate in the substrate and form the first cavity in the substrate, compared with the prior art, a conductive film layer for forming the first polar plate and a sacrificial layer for forming the first cavity are not required to be deposited, so that the preparation process steps are simplified, and the manufacturing cost is reduced.

Description

Pressure sensor and method for manufacturing the same

Technical Field

The invention relates to the technical field of sensors, in particular to a pressure sensor and a manufacturing method thereof.

Background

The pressure sensor is a device capable of converting a pressure signal into an electrical signal, and can be classified into four main types, namely, a piezoresistive type, a capacitive type, a resonant type, a piezoelectric type and the like. For a pressure sensor, it includes an upper plate, a lower plate, and a vacuum chamber disposed between the upper and lower plates.

At present, when a pressure sensor is manufactured, a conductive film layer needs to be deposited on a substrate, the conductive film layer is patterned to form a lower plate, a sacrificial layer is deposited on the lower plate, and then the sacrificial layer is etched to form a vacuum cavity. Because the conductive film layer and the additional sacrificial layer need to be deposited in the preparation process, and then part of the conductive film layer and the additional sacrificial layer are etched and removed, the preparation process steps are increased, and the manufacturing cost is increased.

Disclosure of Invention

It is desirable to provide a pressure sensor and a method of manufacturing the same that at least reduces the manufacturing cost of the pressure sensor.

In a first aspect, the present invention provides a pressure sensor comprising:

the substrate comprises a first capacitor area, a first doped area is formed in the substrate within a preset depth range of the first capacitor area, the first doped area is used as a first polar plate of a first capacitor, and a first cavity is arranged in the substrate;

the second polar plate is arranged on one side of the substrate, in the orthographic projection of the substrate, the first polar plate, the second polar plate and the first cavity are at least partially overlapped, and the first cavity is positioned between the first polar plate and the second polar plate.

As an implementation manner, the substrate further includes a second capacitor region, a second doped region is formed in the predetermined depth range of the second capacitor region in the substrate, the second doped region serves as a third electrode plate of a second capacitor, and a second cavity is formed in the substrate;

the third polar plate is arranged on one side of the substrate, in the orthographic projection of the substrate, the third polar plate, the fourth polar plate and the second cavity are at least partially overlapped, and the second cavity is positioned between the third polar plate and the fourth polar plate;

and a rigid supporting layer is arranged on one side of the fourth polar plate, which is far away from the third polar plate.

As an implementation manner, the first doping region and the second doping region are prepared by the same implantation process.

As an implementation, the first cavity and the second cavity are prepared by the same etching process.

As an implementation manner, the second electrode plate and the fourth electrode plate are arranged in the same layer.

As an implementation manner, the first electrode plate is electrically connected with a first electrode, and the first electrode is insulated from the substrate; the second electrode plate is electrically connected with the second electrode.

As an implementation manner, the third electrode plate is electrically connected with a third electrode, and the third electrode is insulated from the substrate; the fourth electrode plate is electrically connected with the fourth electrode.

As an implementation manner, the first cavity and the second cavity are both parallelogram cavities, each surface of each parallelogram cavity is a crystal surface, and the acute included angle between adjacent crystal surfaces is 69-72 degrees.

As an implementation, the acute included angle is 70.52 °.

As an implementation manner, one of the substrate and the first doped region is N-type, and the other is P-type; and/or the presence of a gas in the gas,

one of the substrate and the second doped region is N-type, and the other is P-type.

In a second aspect, the present invention provides a method for manufacturing the pressure sensor, including:

providing a substrate, wherein the substrate comprises a first capacitance area;

forming a first doping area in a preset depth range of the first capacitor area of the substrate through an implantation process, wherein the first doping area is used as a first polar plate of a first capacitor;

forming a first cavity on one side of the substrate through an etching process;

and forming a second polar plate on one side of the substrate, wherein in the orthographic projection of the substrate, the first polar plate, the second polar plate and the first cavity are at least partially overlapped, and the first cavity is positioned between the first polar plate and the second polar plate.

As an implementation, the substrate further includes a second capacitance region;

forming a second doped region in a predetermined depth range of the second capacitor region of the substrate through the implantation process, wherein the second doped region is used as a third electrode plate of a second capacitor;

forming a second cavity on one side of the substrate through the etching process;

and forming a fourth polar plate on one side of the substrate, wherein in the orthographic projection of the substrate, the third polar plate, the fourth polar plate and the second cavity are at least partially overlapped, and the second cavity is positioned between the third polar plate and the fourth polar plate.

As an implementation manner, the forming of the first cavity on one side of the substrate by the etching process and the forming of the second cavity on one side of the substrate by the etching process specifically include:

etching the top of the substrate to form an etching hole, wherein the depth of the etching hole is smaller than the preset depth range;

forming an etching protective layer at least on the side wall and the bottom surface of the etching hole;

after the etching protective layer is formed, continuously etching the etching hole until the first doping area and the second doping area are reached;

and etching the substrate by the etching hole by adopting a crystal face self-stop etching mode to form the first cavity and the second cavity.

As an implementation manner, after the first cavity and the second cavity are formed, the etching hole is filled to seal the etching hole.

As an implementation manner, a rigid support layer is formed on the fourth polar plate;

forming a via hole on the rigid support layer, and forming a conductive piece in the via hole, wherein the conductive piece is electrically connected with the fourth polar plate;

and forming a fourth electrode on one side of the rigid supporting layer, which is far away from the fourth substrate, wherein the fourth electrode is electrically connected with the conductive piece.

According to the scheme, the substrate is doped to form the first polar plate in the substrate and form the first cavity in the substrate, compared with the prior art, a conductive film layer for forming the first polar plate and a sacrificial layer for forming the first cavity are not required to be deposited, so that the preparation process steps are simplified, and the manufacturing cost is reduced.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings:

fig. 1 is a schematic structural diagram of a pressure sensor according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a pressure sensor according to another embodiment of the present invention;

FIG. 3 is an equivalent circuit diagram of FIG. 2;

FIG. 4 is a schematic structural diagram of a pressure sensor according to yet another embodiment of the present invention;

fig. 5 is a schematic structural diagram of a first cavity according to an embodiment of the present invention;

FIG. 6 is a flow chart of a method of manufacturing a pressure sensor provided by an embodiment of the present invention;

fig. 7-15 are schematic structural diagrams illustrating a manufacturing process of a pressure sensor according to an embodiment of the present invention;

fig. 16-28 are schematic structural diagrams illustrating a manufacturing process of a pressure sensor according to still another embodiment of the invention.

Detailed Description

The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.

The "patterning process" described in the embodiments of the present invention includes processes of depositing a film, coating a photoresist, mask exposure, development, etching, and stripping a photoresist, and is a well-established manufacturing process in the related art. The "photolithography process" referred to in this embodiment includes coating film layer, mask exposure, and development, and is a well-established manufacturing process in the related art. The deposition may be performed by known processes such as sputtering, evaporation, chemical vapor deposition, etc., the coating may be performed by known coating processes, the etching may be performed by known methods, and the growth epitaxy may be performed by known methods, which are not particularly limited herein.

In the description of the embodiments of the present invention, it should be understood that "thin film" refers to a layer of thin film made of a material by a deposition, coating or growth process on a layer (e.g., a substrate). The "thin film" may also be referred to as a "layer" if it does not require a patterning process or a photolithography process throughout the fabrication process. If a patterning process or a photolithography process is required for the "thin film" in the entire manufacturing process, the "thin film" is referred to as a "thin film" before the patterning process, and the "layer" after the patterning process. The "layer" after the patterning process or the photolithography process includes at least one "pattern". For example, and without limitation, the thickness of the films referred to herein may be below 100 μm.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

As shown in fig. 1, the present invention provides a pressure sensor, including:

the capacitor comprises a substrate 1, wherein the substrate 1 comprises a first capacitor area A, a first doping area 2 is formed in the substrate 1 within a preset depth range of the first capacitor area A, the first doping area 2 is used as a first polar plate of a first capacitor C1, and a first cavity 7 is arranged in the substrate 1;

for example, but not limited to, the substrate 1 is a silicon substrate.

The first doped region 2 may be formed in the substrate 1 by implantation, and the implantation depth may be controlled by controlling the implantation process parameters, such as power, time, and the like, so as to realize a predetermined depth range of the first capacitor region a in the substrate 1, and the first doped region 2 is formed.

The first cavity 7 provides a space for the second plate 5 to deform.

The second plate 5 is disposed on one side of the substrate 1, in an orthographic projection of the substrate 1, the first plate, the second plate 5 and the first cavity 7 are at least partially overlapped, and the first cavity 7 is located between the first plate and the second plate 5.

The first pole plate, the second pole plate 5 and the first cavity 7 are at least partially overlapped, so that the first pole plate and the second pole plate 5 form a capacitor, at least a part of the overlapped position is overlapped with the first cavity 7, when the pressure sensor senses pressure, the second pole plate 5 deforms in the first cavity 7, the distance between the first pole plate and the second pole plate 5 becomes small, as the capacitance value is negatively correlated with the distance between the first pole plate and the second pole plate 5, the capacitance value of the pressure sensor becomes large as the distance between the first pole plate and the second pole plate 5 becomes small, and the pressure value can be obtained through the corresponding relation between the variation of the capacitance value and the pressure value.

According to the scheme, the substrate 1 is doped to form the first polar plate in the substrate 1 and form the first cavity 7 in the substrate 1, compared with the prior art, a conductive film layer for forming the first polar plate and a sacrificial layer for forming the first cavity 7 do not need to be deposited, so that the preparation process steps are simplified, and the manufacturing cost is reduced.

As an implementation manner, as shown in fig. 2, in order to improve the detection accuracy of the pressure sensor, the substrate 1 further includes a second capacitor region B, a second doped region 10 is formed in the substrate 1 within a predetermined depth range of the second capacitor region B, the second doped region 10 serves as a third plate of a second capacitor C2, and a second cavity 11 is formed in the substrate 1;

a third plate, disposed on one side of the substrate 1, wherein in an orthogonal projection of the substrate 1, the third plate, the fourth plate 12 and the second cavity 11 are at least partially overlapped, and the second cavity 11 is located between the third plate and the fourth plate 12;

one side of the fourth polar plate 12, which is far away from the third polar plate, is provided with a rigid supporting layer 13, that is, the rigid supporting layer 13 is arranged on the fourth polar plate 12, and pressure is applied to the rigid supporting layer 13, so that the rigid supporting layer is not deformed, and the fourth polar plate 12 is further ensured not to be deformed to the second cavity 11, so that the second capacitor C2 is a capacitor with a constant capacitance value.

Wherein the first cavity 7 and the second cavity 11 are both closed cavities. For example, but not limited to, the enclosed cavity may be a vacuum cavity.

In the above solution, as shown in fig. 3, the pressure sensor further includes a first capacitor C1 whose capacitance value can be changed according to the pressure and a second capacitor C2 whose capacitance value is constant, when the pressure sensor is used, one of the plates of the first capacitor C1 and one of the plates of the second capacitor C2 may be electrically connected together, of course, in other examples, the two capacitors may not be connected together, and the actual capacitance value of the pressure sensor is the measured capacitance value, that is, the current capacitance value (the capacitance value between the contacts ab) of the first capacitor C1 minus the capacitance value (the capacitance value between the contacts cd) of the second capacitor C2.

As an implementation manner, in order to improve the manufacturing efficiency, simplify the manufacturing process, and reduce the manufacturing cost, the first doping region 2 and the second doping region 10 are manufactured by the same implantation process, that is, the first doping region 2 and the second doping region 10 are manufactured by the same manufacturing process simultaneously.

As an implementation manner, in order to improve the manufacturing efficiency, simplify the manufacturing process, and reduce the manufacturing cost, the first cavity 7 and the second cavity 11 are manufactured by the same etching process, that is, the first cavity 7 and the second cavity 11 are manufactured by the same manufacturing process and are manufactured synchronously.

As an implementation manner, in order to improve the manufacturing efficiency, simplify the manufacturing process, and reduce the manufacturing cost, the second electrode plate 5 and the fourth electrode plate 12 are disposed in the same layer, that is, the second electrode plate 5 and the fourth electrode plate 12 may be obtained by patterning the same film layer.

As a practical way, the first electrode plate is electrically connected with a first electrode 3, and the first electrode 3 is insulated from the substrate 1; the second electrode plate 5 is electrically connected to the second electrode 6.

For example, the first electrode 3 may be insulated from the substrate 1 by adopting a structure, as shown in fig. 1, the first electrode 3 is arranged in a region of the first electrode plate exposed outside the substrate 1, and the first electrode 3 is arranged with a smaller width, so that the first electrode 3 is located in the orthographic projection of the first electrode plate, and a gap 4 is arranged between the first electrode 3 and the substrate 1 in the width direction, so as to realize the insulation between the first electrode 3 and the substrate 1, and by adopting this structure, since the width of the first electrode 3 is smaller and it is necessary to ensure that a gap is arranged between the first electrode 3 and the substrate 1 in the width direction, the process precision required for forming the first electrode 3 is higher; as shown in fig. 2, in order to reduce the requirement of process precision when forming the first electrode 3, so as to reduce the manufacturing cost, an insulator 8 is formed at a side of the first cavity 7 close to the region of the first electrode plate exposed outside the substrate 1, and in the case of providing the insulator 8, the width of the first electrode 3 can be made relatively large, so that the requirement of process precision when manufacturing is reduced, and the manufacturing cost is further reduced; as shown in fig. 4, an insulating layer may be further formed in a region of the first plate exposed outside the substrate 1, and the insulating layer further covers at least a portion of the substrate 1, a via hole is formed on the insulating layer, and the first electrode 3 is formed in the via hole.

As a practical way, the third electrode plate is electrically connected with a third electrode 9, and the third electrode 9 is insulated from the substrate 1; the fourth electrode plate 12 is electrically connected to the fourth electrode 15.

For the insulation structure between the third electrode 9 and the substrate 1, reference may be made to the insulation structure between the first electrode 3 and the substrate 1, which is not described herein again.

As an implementation manner, as shown in fig. 5, in this embodiment, the first cavity 7 and the second cavity 11 are formed on the substrate 1 by etching through a self-stop etching process, so that the first cavity 7 and the second cavity 11 are both parallelogram cavities, each surface of each parallelogram cavity is a crystal plane 20, and an acute included angle between adjacent crystal planes 20 is 70.52 °.

As an implementation manner, one of the substrate 1 and the first doped region 2 is N-type, and the other is P-type; so as to form a PN junction between the substrate 1 and the first doped region 2 to prevent conduction between the substrate 1 and the first doped region 2, when the first doped region 2 is P-type and the substrate 1 is N-type, a negative voltage can be applied to the first electrode 3 to prevent conduction between the substrate 1 and the first doped region 2 when in use, and when the first doped region 2 is N-type and the substrate 1 is P-type, a positive voltage can be applied to the first electrode 3 to prevent conduction between the substrate 1 and the first doped region 2 when in use, and/or,

one of the substrate 1 and the second doped region 10 is N-type, and the other is P-type, so as to form a PN junction between the substrate 1 and the second doped region 10, thereby preventing conduction between the substrate 1 and the second doped region 10, when the second doped region 10 is P-type and the substrate 1 is N-type, a negative voltage can be applied to the third electrode 9 during use, thereby preventing conduction between the substrate 1 and the second doped region 10, and when the second doped region 10 is N-type and the substrate 1 is P-type, a positive voltage can be applied to the third electrode 9 during use, thereby preventing conduction between the substrate 1 and the second doped region 10.

In a second aspect, as shown in fig. 6, the present invention provides a method for manufacturing the pressure sensor, including:

s1: providing a substrate 1, wherein the substrate 1 comprises a first capacitor area A;

s2: forming a first doped region 2 in a predetermined depth range of the first capacitor region a of the substrate 1 through an implantation process, wherein the first doped region 2 serves as a first plate of a first capacitor C1;

s3: forming a first cavity 7 on one side of the substrate 1 through an etching process;

s4: a second polar plate 5 is formed on one side of the substrate 1, in the orthographic projection of the substrate 1, the first polar plate, the second polar plate 5 and the first cavity 7 are at least partially overlapped, and the first cavity 7 is positioned between the first polar plate and the second polar plate 5.

As an implementation manner, the substrate 1 further includes a second capacitance region a; that is, the substrate 1 includes a first capacitance region a and a second capacitance region B;

forming a second doped region 10 in a predetermined depth range of the second capacitor region B of the substrate 1 through the implantation process, wherein the second doped region 10 serves as a third plate of a second capacitor C2; that is, the second doped region 10 is formed at the same time as the first doped region 2 is formed on the substrate 1 through the same implantation process.

Forming a second cavity 11 on one side of the substrate 1 through the etching process; that is, the second cavity 11 is formed at the same time as the first cavity 7 is formed by the same etching process.

A fourth plate 12 is formed on one side of the substrate 1, in an orthogonal projection of the substrate 1, the third plate and the fourth plate 12 at least partially overlap with the second cavity 11, and the second cavity 11 is located between the third plate and the fourth plate 12.

As an implementation manner, the forming of the first cavity 7 on one side of the substrate 1 by the etching process, and the forming of the second cavity 11 on one side of the substrate 1 by the etching process specifically include:

etching the top of the substrate 1 to form an etching hole 17, wherein the depth of the etching hole 17 is smaller than the preset depth range;

forming an etching protective layer 18 on at least the sidewall and the bottom of the etching hole 17;

after the etching protection layer 18 is formed, continuing to etch the etching hole 17 until the first doping region 2 and the second doping region 10 are reached; for example, but not limited to, etching the Etching hole 17 by Deep Reactive Ion Etching (DRIE), during Etching, the Etching protection layer 18 at the bottom of the Etching hole 17 is etched away, and the Etching protection layer 18 at the sidewall of the Etching hole 17 is remained, so that, when the first cavity 7 and the second cavity 11 are formed subsequently, the substrate 1 is etched only in the depth interval of the Etching hole 17, that is, the Etching hole 17 is etched for the second time, so as to form the first cavity 7 and the second cavity 11.

And etching the substrate 1 by using the etching hole 17 in a crystal plane self-stop etching manner to form the first cavity 7 and the second cavity 11.

As a practical matter, after the first cavity 7 and the second cavity 11 are formed, the etching hole 17 is filled to seal the etching hole 17.

As a practical way, a rigid support layer 13 is formed on the fourth electrode plate 12;

forming a via hole on the rigid support layer 13, and forming a conductive member 14 in the via hole, wherein the conductive member 14 is electrically connected with the fourth polar plate 12;

on the side of the rigid support layer 13 facing away from the fourth substrate 12, a fourth electrode 15 is formed, and the fourth electrode 15 is electrically connected to the conductive member 14.

The invention will be illustrated below by specific examples of two of the manufacturing methods.

Example 1

As shown in fig. 7, a substrate 1 is provided, where the substrate 1 may be, for example, a P-type silicon substrate, the substrate 1 includes a first capacitor region a, and the substrate 1 is locally N-doped by an implantation process to improve conductivity of a doped position, where a first doped region 2 is formed in the substrate 1 within a predetermined depth range of the first capacitor region a, and the first doped region 2 serves as a first plate of a first capacitor C1;

as shown in fig. 8, forming a photoresist layer on the top of the substrate 1, exposing and developing the photoresist layer to be used as a mask, etching the top of the substrate 1 to form an Etching hole 17, for example, but not limited to, using Deep Reactive Ion Etching (DRIE) to etch and form the Etching hole 17, and removing the photoresist layer after Etching, wherein the depth of the Etching hole 17 is less than the predetermined depth range;

as shown in fig. 9, depositing an etching protection layer 18 on the sidewall and the bottom of the etching hole 17 by LPCVD (Low Pressure Chemical Vapor Deposition), wherein the material of the etching protection layer 18 may be, but is not limited to, silicon nitride or silicon oxide;

as shown in fig. 10, the etching of the etching hole 17 may be continued using DRIE until the first doping region 2 is reached;

as shown in fig. 11, a photoresist layer is formed on the top of the substrate 1, and is exposed and developed to be used as a mask 19, a crystal plane self-stop etching manner is adopted to form a first cavity 7, and the photoresist layer is removed after etching; the first cavity is a parallelogram cavity, each surface of the parallelogram cavity is a crystal plane, and the acute included angle of adjacent crystal planes is 70.52 degrees, of course, in other examples, the acute included angle may be other degrees according to actual conditions.

As shown in fig. 12, an insulating material, such as silicon oxide or silicon nitride, is deposited by LPCVD on the top surface of the substrate 1, wherein at least part of the deposited material is located in the etch holes 17 to fill the etch holes 17. After the etching hole 17 is sealed, removing the excess filling material on the surface of the substrate 1 by a Chemical Mechanical Polishing (CMP) method to expose the top surface of the substrate 1;

as shown in fig. 13, an electrode plate film is deposited on the top surface of the substrate 1 and patterned to form a second electrode plate 5; the electrode plate film can be made of polysilicon, metal and the like, and the metal is, for example, but not limited to, simple substances or alloys including aluminum, copper, silver, gold and the like;

as shown in fig. 14, at a position different from the second plate 5, the substrate 1 is etched, for example, by using ICP (inductively Coupled Plasma etching), until the first doped region 2 is exposed, and an insulator 8 is formed in the first doped region 2 exposed outside the substrate 1;

as shown in fig. 15, a first electrode 3 is formed on the first doped region 2, a second electrode 6 is formed on the second plate 5, the first electrode 3 is electrically connected to the first doped region 2, and the second electrode 6 is electrically connected to the second plate 5;

for example, an electrode film layer may be deposited by PVD (Physical Vapor Deposition) and patterned to obtain the first and second electrodes 3 and 6.

Example 2

As shown in fig. 16, a substrate 1 is provided, where the substrate 1 may be, for example, a P-type silicon substrate, the substrate 1 includes a first capacitor region a and a second capacitor region B, and the substrate 1 is locally N-doped by an implantation process to improve the conductivity of a doped position, where a first doped region 2 is formed in the substrate 1 within a predetermined depth range of the first capacitor region a, the first doped region 2 serves as a first plate of a first capacitor C1, a second doped region 10 is formed in the substrate 1 within a predetermined depth range of the second capacitor region B, and the second doped region 10 serves as a third plate of a second capacitor C2;

as shown in fig. 17, forming a photoresist layer on the top of the substrate 1, exposing and developing the photoresist layer to be used as a mask, etching the top of the substrate 1 to form an Etching hole 17, for example, but not limited to, using Deep Reactive Ion Etching (DRIE) to etch and form the Etching hole 17, and removing the photoresist layer after Etching, wherein the depth of the Etching hole 17 is less than the predetermined depth range;

as shown in fig. 18, an etching protection layer 18 is deposited on the sidewall and the bottom of the etching hole 17 by LPCVD (Low Pressure Chemical Vapor Deposition), the material of the etching protection layer 18 may be, but is not limited to, silicon nitride or silicon oxide;

as shown in fig. 19, DRIE may be used to continue etching down the etch holes 17 until the first doped region 2 and the second doped region 10 are reached;

as shown in fig. 20, a photoresist layer is formed on the top of the substrate 1, and is exposed and developed to be used as a mask 19, a crystal plane self-stop etching manner is adopted to form a first cavity 7 and a second cavity 11, and the photoresist layer is removed after etching;

as shown in fig. 21, an insulating material, such as silicon oxide or silicon nitride, is deposited on the top surface of the substrate 1 by LPCVD, wherein at least part of the deposited material is located in the etch holes 17 to fill the etch holes 17. After the etching hole 17 is sealed, removing the excess filling material on the surface of the substrate 1 by using a CMP (chemical mechanical Polishing) mode to expose the top surface of the substrate 1;

as shown in fig. 22, an electrode plate film is deposited on the top surface of the substrate 1 and patterned to form a second electrode plate 5 and a fourth electrode plate 12; the electrode plate film can be made of polysilicon, metal and the like, and the metal is, for example, but not limited to, simple substances or alloys including aluminum, copper, silver, gold and the like;

as shown in fig. 23, at a position different from the second plate 5 and the fourth plate 12, the substrate 1 is etched, for example, by using ICP (inductively Coupled Plasma etching), until the first doped region 2 and the second doped region 10 are exposed, and an insulator 8 is formed in both the first doped region 2 and the second doped region 10 exposed outside the substrate 1;

as shown in fig. 24, a first electrode 3 is formed on the first doped region 2, a second electrode 6 is formed on the second plate 5, the first electrode 3 is electrically connected to the first doped region 2, and the second electrode 6 is electrically connected to the second plate 5;

as shown in fig. 25, a third electrode 9 is formed in the second doped region 10, and the third electrode 9 is electrically connected to the second doped region 10;

in some examples, the first electrode 3, the second electrode 6, and the third electrode 9 may also be disposed in the same layer, for example, an electrode film layer may be deposited by PVD (Physical Vapor Deposition) and patterned to obtain the first electrode 3, the second electrode 6, and the third electrode 9;

as shown in fig. 26, a rigid support layer 13 is disposed on the fourth electrode plate 12, for example, but not limited to, the rigid support layer 13 may be a silicon nitride layer or a silicon oxide layer with a large thickness, and the rigid support layer 13 may be formed by CVD (Chemical Vapor Deposition);

as shown in fig. 27, a via is formed on rigid support layer 13 by DRIE, and a conductive member 14 is deposited in the via, said conductive member 14 being electrically connected to said fourth plate 12;

as shown in fig. 28, an electrode film layer is deposited by PVD on the side of the rigid support layer 13 away from the fourth substrate 12, and the electrode film layer is patterned to form a fourth electrode 15, and the fourth electrode 15 is electrically connected to the conductive member 14.

It will be understood that any orientation or positional relationship indicated above with respect to the terms "central," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," etc., is based on the orientation or positional relationship shown in the drawings and is for convenience in describing and simplifying the invention, and does not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and is therefore not to be considered limiting of the invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified.

The above description is only a preferred embodiment of the application and is illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the invention herein disclosed is not limited to the particular combination of features described above, but also encompasses other arrangements in which any combination of the above features or their equivalents is incorporated without departing from the spirit of the invention. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims (15)

1. A pressure sensor, comprising:

the substrate comprises a first capacitor area, a first doped area is formed in the substrate within a preset depth range of the first capacitor area, the first doped area is used as a first polar plate of a first capacitor, and a first cavity is arranged in the substrate;

the second polar plate is arranged on one side of the substrate, in the orthographic projection of the substrate, the first polar plate, the second polar plate and the first cavity are at least partially overlapped, and the first cavity is positioned between the first polar plate and the second polar plate.

2. The pressure sensor of claim 1, wherein the substrate further comprises a second capacitor region, a second doped region is formed in the substrate within a predetermined depth range of the second capacitor region, the second doped region serves as a third plate of the second capacitor, and a second cavity is formed in the substrate;

the third polar plate is arranged on one side of the substrate, in the orthographic projection of the substrate, the third polar plate, the fourth polar plate and the second cavity are at least partially overlapped, and the second cavity is positioned between the third polar plate and the fourth polar plate;

and a rigid supporting layer is arranged on one side of the fourth polar plate, which is far away from the third polar plate.

3. The pressure sensor of claim 2, wherein the first doped region and the second doped region are prepared by a same implantation process.

4. The pressure sensor of claim 2, wherein the first cavity and the second cavity are prepared by a same etching process.

5. The pressure sensor of claim 2, wherein the second plate is disposed in a same layer as the fourth plate.

6. The pressure sensor of any of claims 1-5, wherein the first plate is electrically connected to a first electrode, the first electrode being insulated from the substrate; the second electrode plate is electrically connected with the second electrode.

7. The pressure sensor of any of claims 2-5, wherein the third plate is electrically connected to a third electrode, the third electrode being insulated from the substrate; the fourth electrode plate is electrically connected with the fourth electrode.

8. The pressure sensor according to any one of claims 2 to 5, wherein the first cavity and the second cavity are both parallelogram cavities, and each face of the parallelogram cavity is a crystal face, and the acute included angle between adjacent crystal faces is 69-72 °.

9. A pressure sensor as claimed in claim 8, wherein the acute included angle is 70.52 °.

10. A pressure sensor according to any of claims 2 to 5, wherein one of the substrate and the first doped region is of N-type and the other is of P-type; and/or the presence of a gas in the gas,

one of the substrate and the second doped region is N-type, and the other is P-type.

11. A method of manufacturing a pressure sensor, comprising:

providing a substrate, wherein the substrate comprises a first capacitance area;

forming a first doped region in a preset depth range of the first capacitor region of the substrate through an implantation process, wherein the first doped region is used as a first polar plate of a first capacitor;

forming a first cavity on one side of the substrate through an etching process;

and forming a second polar plate on one side of the substrate, wherein in the orthographic projection of the substrate, the first polar plate, the second polar plate and the first cavity are at least partially overlapped, and the first cavity is positioned between the first polar plate and the second polar plate.

12. The method of manufacturing of claim 11, wherein the substrate further comprises a second capacitive region;

forming a second doped region in a predetermined depth range of the second capacitor region of the substrate through the implantation process, wherein the second doped region is used as a third electrode plate of a second capacitor;

forming a second cavity on one side of the substrate through the etching process;

and forming a fourth polar plate on one side of the substrate, wherein in the orthographic projection of the substrate, the third polar plate, the fourth polar plate and the second cavity are at least partially overlapped, and the second cavity is positioned between the third polar plate and the fourth polar plate.

13. The manufacturing method according to claim 12, wherein the forming of the first cavity on one of the sides of the substrate by the etching process and the forming of the second cavity on one of the sides of the substrate by the etching process are specifically:

etching the top of the substrate to form an etching hole, wherein the depth of the etching hole is smaller than the preset depth range;

forming an etching protective layer at least on the side wall and the bottom surface of the etching hole;

after the etching protective layer is formed, continuously etching the etching hole until the first doping area and the second doping area are reached;

and etching the substrate by the etching hole by adopting a crystal face self-stop etching mode to form the first cavity and the second cavity.

14. The manufacturing method according to claim 13, wherein the etching hole is filled to seal the etching hole after the first cavity and the second cavity are formed.

15. A method of manufacturing according to any one of claims 12 to 14, wherein a rigid support layer is formed on the fourth plate;

forming a via hole on the rigid support layer, and forming a conductive piece in the via hole, wherein the conductive piece is electrically connected with the fourth polar plate;

and forming a fourth electrode on one side of the rigid support layer, which is far away from the fourth substrate, wherein the fourth electrode is electrically connected with the conductive piece.

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