CN115525596A - Multi-master switching type high-speed interconnection backplane bus, control method thereof and processing system thereof - Google Patents
Multi-master switching type high-speed interconnection backplane bus, control method thereof and processing system thereof Download PDFInfo
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Abstract
The invention discloses a multi-master switching type high-speed interconnection backboard bus, a control method and a processing system thereof, wherein the multi-master switching type high-speed interconnection backboard bus comprises the following steps: the method comprises the following steps: a programmable bus protocol controller; the programmable bus protocol controller is electrically connected with a plurality of processors and a plurality of peripheral modules of the processing system respectively, receives control instructions of the processors, and converts one-to-one, one-to-many or many-to-one concurrent bus access of a plurality of processes into virtual end-to-end connection by performing virtual address conversion on the peripheral modules corresponding to the control instructions so as to improve the data transmission efficiency of the backplane bus. By adopting the star-shaped connection structure of the programmable bus protocol controller, the processors and the peripheral modules, the problem of bus resource limitation of concurrent access of the processors is solved, the data packet collision rate is reduced, a plurality of processors are allowed to simultaneously initiate bus access or a single processor is allowed to simultaneously initiate access of a plurality of external devices, and the multi-master access of the back panel bus realizes the aggregation of computing power of the processors.
Description
Technical Field
The invention relates to the field of processing system data transmission, in particular to a multi-master switching type high-speed interconnection backplane bus, a control method thereof and a processing system.
Background
In the field of industrial control, the backboard bus realizes the combination and interaction of the processor, the peripheral function module and the like in the same control unit, and is the basis and the premise for realizing the flexible configuration of the control unit. For complex and high-real-time control application scenes, the requirements of multiple main processors, multiple peripherals, concurrent access, high-speed exchange and synchronous transmission exist, so that a backplane bus is required to have strong data throughput capacity.
In a conventional industrial control system, a backplane bus generally adopts a master-slave mode, a time-sharing bus occupation mode and the like, which is not beneficial to flexible configuration of the system on one hand and has a performance bottleneck on the other hand.
In the existing multiprocessor system, a multiprocessor occupies a bus in a time-sharing manner and polls and accesses a peripheral function module in a chassis, so that the real-time performance of system data interaction is reduced to a certain extent. When a plurality of peripheral function modules send interrupts to different processors, bus access conflict is inevitably caused, so that interrupt response time is prolonged; when a plurality of processors access the bus concurrently, the bus congestion is caused, and the circulation of calculation and control can not be carried out until the bus is waited to be released, which causes the desynchronization of the calculation state of the plurality of processors, thereby reducing the comprehensive calculation power in unit time.
Compared with the situation, the multi-master switching high-speed interconnection backplane bus based on the programmable device can realize a multi-master processor array parallel computing architecture, and solves the problems that a conventional shared bus does not support concurrent access and the conventional interconnection bus is complex in structure, complicated in connection and free of flexible configuration and expansion. The method effectively improves the throughput rate of the bus, enhances the bandwidth of the bus, realizes the array operation and calculation power aggregation of a plurality of main processors, greatly optimizes the bus structure and is beneficial to the flexible configuration of the system.
In the conventional multiprocessor system, as shown in fig. 1, a shared backplane bus is generally used as the backplane bus; alternatively, as shown in fig. 2, an end-to-end interconnection type communication bus mode is employed. The bus-type backplane bus is shared, and the biggest bottleneck of the bus-type backplane bus in a multiprocessor system is that the processors cannot use the bus at the same time. The plurality of processors obtain the use right of the bus in turn through bus arbitration, which inevitably causes task delay of the processors and reduces the real-time property of data; in a shared bus type backboard bus system, when a main processor accesses a plurality of devices on a bus, the main processor also needs to access in a polling mode, and can not simultaneously read and write a plurality of peripheral modules, so that the sampling data is asynchronous; in addition, in the shared bus type backboard bus system, a corresponding bus protocol arbiter must be designed, which causes the bus protocol to be fixed and increases the hardware cost.
In the end-to-end interconnect type communication bus mode, an exclusive bus exists between the plurality of processors and the peripheral modules. The real-time performance of the system is improved, but the increase of the connecting lines among the processor systems is caused, the difficulty of the bus wiring of the system backboard is increased, the system cannot be flexibly expanded and configured due to the fact that a specific connecting line relation is needed, meanwhile, due to the fact that the processor and the peripheral modules are connected through the independent bus, when the processor needs to access the plurality of peripheral modules simultaneously, the processor needs to access the plurality of peripheral modules respectively in a polling mode, and the asynchronization of sampling data can be caused.
Disclosure of Invention
The invention aims to provide a multi-master switching type high-speed interconnected back plate bus, a control method and a processing system thereof, which solve the problem of bus resource limitation of concurrent access of multiple processors by adopting a star-shaped connection structure of a programmable bus protocol controller, the processors and peripheral modules, reduce the collision rate of data packets, allow multiple processors to simultaneously initiate bus access or a single processor to simultaneously initiate access of multiple peripheral devices and realize the aggregation of the computational power of the multiple processors; meanwhile, the exchange type interconnection bus structure can effectively reduce the complexity of a back plate bus, and enables the whole system to have better expansibility and flexible configuration capability, thereby being capable of being quickly applied to various industrial control application scenes.
To solve the above technical problem, a first aspect of an embodiment of the present invention provides a multi-master switching high-speed interconnect backplane bus, including: a programmable bus protocol controller;
the programmable bus protocol controller is respectively and electrically connected with a plurality of processors and a plurality of peripheral modules of the processing system,
the programmable bus protocol controller receives the control instructions of the processors, and converts the one-to-one, one-to-many or many-to-one concurrent bus access of the plurality of processes into virtual end-to-end connection by performing virtual address conversion on the plurality of peripheral modules corresponding to the control instructions, so as to improve the data transmission efficiency of the backplane bus.
Further, the programmable bus protocol controller includes: a programmable device;
and the programmable bus protocol controller realizes data interaction with the processors and the peripheral modules respectively through the I/O of the programmable device.
Further, the header of the message for controlling the command for one-time backplane communication access includes: the type of module from which the access was issued, slot number, destination address, and/or task priority.
Further, a storage unit is arranged in the programmable bus protocol controller, and the storage unit includes: an internal storage unit and/or an external storage unit;
the programmable device receives tasks and data sent by any processor and sends the tasks and data to the storage unit;
and the processor reads the task and the data at idle time and processes the task and the data.
Further, the other processors may read and process the tasks and data stored in the storage unit.
Accordingly, a second aspect of the embodiments of the present invention provides a method for controlling a multi-master switching high-speed interconnect backplane bus, which is used to control the multi-master switching high-speed interconnect backplane bus, and includes the following steps:
receiving control instructions of a plurality of processors of a processing system;
when the control instructions of the plurality of processors correspond to the same peripheral module, performing virtual address conversion on the peripheral module;
and judging whether the data of the peripheral module is valid data or not according to the use condition of the peripheral module, if so, mapping the peripheral access initiated by the processors to the virtual address of the peripheral module so as to realize the concurrent access of the processors to the peripheral module.
Accordingly, a third aspect of the embodiments of the present invention provides a method for controlling a multi-master switching high-speed interconnect backplane bus, for controlling the multi-master switching high-speed interconnect backplane bus, including the following steps:
receiving control instructions of a plurality of processors of a processing system;
when the control instructions of the plurality of processors correspond to the plurality of peripheral modules, the programmable bus protocol controller respectively performs virtual address conversion on the plurality of peripheral modules according to the control instructions of the plurality of processors;
the processors and the peripheral modules form a virtual one-to-one link so as to realize the concurrent access of the processors to the corresponding peripheral modules respectively.
Accordingly, a fourth aspect of the embodiments of the present invention provides a method for controlling a multi-master switching high-speed interconnect backplane bus, for controlling the multi-master switching high-speed interconnect backplane bus, including the following steps:
receiving a control instruction of a processing system processor;
when a control instruction of the processor corresponds to a plurality of peripheral modules, carrying out virtual address conversion on the plurality of peripheral modules;
and simultaneously accessing the peripheral modules according to the control instruction of the processor in an interrupt mode, integrating the return data of the peripheral modules into a data packet with complete synchronism by a programmable bus protocol controller, and sending the data packet to the processor.
Accordingly, a fifth aspect of an embodiment of the present invention provides a processing system, including: a plurality of treater and a plurality of peripheral module still include: any of the above multi-master switching high-speed interconnect backplanes;
and the processors and the peripheral modules perform data interaction through the multi-master switching type high-speed interconnection backboard.
The technical scheme of the embodiment of the invention has the following beneficial technical effects:
by adopting a star-shaped connection structure of the programmable bus protocol controller, the processors and the peripheral modules, the problem of bus resource limitation of concurrent access of the processors is solved, the data packet collision rate is reduced, a plurality of processors are allowed to simultaneously initiate bus access or a single processor is allowed to simultaneously initiate access of a plurality of external devices, and multi-master access of the back panel bus realizes the aggregation of computing power of the processors; meanwhile, the exchange type interconnection bus structure can effectively reduce the complexity of a back plate bus, and enables the whole system to have better expansibility and flexible configuration capability, thereby being capable of being quickly applied to various industrial control application scenes.
Drawings
FIG. 1 is a schematic diagram of a shared backplane bus in the prior art;
FIG. 2 is a schematic diagram of a prior art end-to-end interconnect-type communication bus concept;
FIG. 3 is a schematic diagram of a multi-master switching high-speed interconnect backplane bus according to an embodiment of the present invention;
FIG. 4 is a flowchart illustrating operations of a multi-master switching high-speed interconnect backplane bus according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating an access operation of a multiprocessor to multiple peripheral modules according to an embodiment of the present invention;
FIG. 6 is a diagram illustrating an access operation of a single processor to multiple peripheral modules according to an embodiment of the present invention;
fig. 7 is a schematic diagram of the computational power aggregation of the system provided by the embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings in conjunction with the following detailed description. It is to be understood that these descriptions are only illustrative and are not intended to limit the scope of the present invention. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present invention.
Fig. 3 is a schematic diagram of a multi-master switching high-speed interconnect backplane bus according to an embodiment of the present invention.
Fig. 4 is a flowchart illustrating an operation of a multi-master switching high-speed interconnect backplane bus according to an embodiment of the present invention.
Referring to fig. 3 and 4, a first aspect of the embodiments of the present invention provides a multi-master switching high-speed interconnect backplane bus, including: a programmable bus protocol controller. The programmable bus protocol controller is electrically connected with a plurality of processors and a plurality of peripheral modules of the processing system respectively; the programmable bus protocol controller receives control instructions of a plurality of processors, and converts one-to-one, one-to-many or many-to-one concurrent bus access of a plurality of processors into virtual end-to-end connection by performing virtual address conversion on a plurality of peripheral modules corresponding to the control instructions so as to improve the data transmission efficiency of the backplane bus.
In the multi-master switching type high-speed interconnection backplane bus, each processor, the peripheral module and the programmable bus protocol controller are connected in a star shape, and the communication among the processors, the peripheral module and the programmable bus protocol controller is bidirectional, so that a switching architecture is realized. Based on the exchange connection structure, the programmable bus protocol controller can convert various concurrent bus accesses into virtual end-to-end connection through virtual address conversion, and the bus efficiency is improved.
Fig. 5 is a diagram illustrating an access operation of a multiprocessor to multiple peripheral modules according to an embodiment of the present invention.
Fig. 6 is a schematic diagram illustrating an access operation of a single processor to multiple peripheral modules according to an embodiment of the present invention.
When a plurality of processors simultaneously initiate access operation to the back panel, the programmable bus protocol controller simultaneously judges messages sent to the bus by each processor, and optimized routing management is carried out according to destination addresses.
Specifically, referring to fig. 5, when a plurality of processors simultaneously initiate access operations to the backplane, if the peripheral function modules to be operated are not the same, the programmable bus protocol controller converts the virtual addresses according to the destination addresses of the operations, so that the processors and the peripherals to be accessed form a virtual one-to-one link. Thereby enabling multi-master concurrent access on the bus.
Specifically, referring to fig. 6, when one host processor accesses a plurality of peripheral function modules simultaneously, the programmable bus protocol controller performs virtual conversion on addresses of the accessed peripheral function modules according to the type of the bus command, and initiates access to the plurality of peripheral function modules simultaneously in an interrupt manner, and the bus protocol controls to integrate returned data into a packet of data with complete synchronism, and send the packet of data to the host processor initiating the access.
Specifically, when a plurality of processors access the same peripheral function module, the programmable bus protocol controller performs virtual address conversion on the peripheral function module, judges whether the data of the current peripheral function module is valid according to the use condition of the peripheral, and if the data of the current peripheral function module is valid, the peripheral access initiated by the plurality of processors is mapped to the same virtual address, so that on one hand, the concurrent access of the plurality of main processors to the single peripheral function module is realized, the bus access period is greatly reduced, and the bus performance is improved.
Further, the programmable bus protocol controller includes: a programmable device. The programmable bus protocol controller realizes data interaction with the plurality of processors and the plurality of peripheral modules respectively through the I/O of the programmable device. The programmable device realizes the main functions of data coding and decoding, protocol conversion, bus arbitration, access route distribution, data synchronization control and the like.
Further, the header of the message for controlling the one-time backplane communication access of the command includes: the type of module from which the access was issued, slot number, destination address, and/or task priority. The device accessing the bus is not limited to a specific communication form, and the conversion of the protocol is realized by the programmable device. The device accessing the local device needs to communicate according to a specified message format.
Fig. 7 is a schematic diagram of the computational power aggregation of the system provided by the embodiment of the invention.
In addition, referring to fig. 7, a memory unit is disposed in the programmable bus protocol controller, and includes: an internal storage unit and an external storage unit; the programmable device receives tasks and data sent by any processor and sends the tasks and data to the storage unit; the processor reads and processes the tasks and data at idle time.
Further, the other processors may read and process the tasks and data stored in the storage unit.
The programmable device manages a section of public memory area, each processor can read and write the public memory area through virtual address conversion, and the programmable bus protocol controller realizes sharing management of tasks and data, effectively improves the overall computing power of the system and realizes computing power aggregation of the system.
By arranging the storage unit, the aggregation of system computing power is realized. When the amount of computation tasks and data for one processor is too large, or when multiple concurrent tasks and data are to be processed simultaneously, the CPUs cannot process in parallel. At the moment, the processor transmits the tasks and the data to the cache of the programmable bus protocol controller through the bus, and other processors can directly read and write the cache space of the programmable bus protocol controller and carry out operation processing, so that the overall computing capacity of the system is effectively improved.
Compared with a shared bus type backboard bus, the technical scheme of the invention solves the problem of conflict when multiple processors access the backboard bus simultaneously, allows multiple processors to access the backboard bus concurrently, and improves the throughput rate of the bus and the real-time performance of the system; the system allows a one-to-many bus access mode, one processor can simultaneously operate a plurality of functional modules, the problem of asynchronous operation of the functional modules is solved, and the problem of multipath synchronous sampling can be effectively solved; the system also allows a many-to-many bus access mode, and the plurality of processors can simultaneously operate the corresponding functional modules, so that the problem that the CPU queues to occupy the bus in the bus mode of the shared backplane is solved, and the real-time performance of the system is improved. In addition, one processor module is supported to access a plurality of peripheral function modules simultaneously, and the data synchronism of the peripheral function modules is realized through the programmable bus protocol controller.
Accordingly, a second aspect of the embodiments of the present invention provides a method for controlling a multi-master switching high-speed interconnect backplane bus, which is used for controlling the multi-master switching high-speed interconnect backplane bus, and includes the following steps:
s110, control instructions of a plurality of processors of the processing system are received.
And S120, when the control instructions of the processors correspond to the same peripheral module, performing virtual address conversion on the peripheral module.
S130, judging whether the data of the peripheral module is valid data or not according to the use condition of the peripheral module, if so, mapping the peripheral access initiated by the processors to the virtual address of the peripheral module so as to realize the concurrent access of the processors to the peripheral module.
Accordingly, a third aspect of the embodiments of the present invention provides a method for controlling a multi-master switching high-speed interconnect backplane bus, for controlling the multi-master switching high-speed interconnect backplane bus, including the following steps:
s210, receiving control instructions of a plurality of processors of the processing system.
S220, when the control instructions of the processors correspond to the peripheral modules, the programmable bus protocol controller respectively performs virtual address conversion on the peripheral modules according to the control instructions of the processors.
And S230, enabling the processors and the peripheral modules to form a virtual one-to-one link so as to realize concurrent access of the processors to the corresponding peripheral modules respectively.
Accordingly, a fourth aspect of the embodiments of the present invention provides a method for controlling a multi-master switching high-speed interconnect backplane bus, which is used for controlling the multi-master switching high-speed interconnect backplane bus, and includes the following steps:
s310, receiving a control instruction of a processing system processor;
s320, when the control instruction of one processor corresponds to a plurality of peripheral modules, carrying out virtual address conversion on the plurality of peripheral modules;
s330, simultaneously accessing the plurality of peripheral modules according to the control instruction of the processor in an interrupt mode, integrating the return data of the plurality of peripheral modules into a data packet with complete synchronism by the programmable bus protocol controller, and sending the data packet to the processor.
Accordingly, a fifth aspect of an embodiment of the present invention provides a processing system, including: a plurality of treater and a plurality of peripheral module still include: any of the above multi-master switching high-speed interconnect backplanes; and the plurality of processors and the plurality of peripheral modules perform data interaction through the multi-master switching type high-speed interconnection backboard.
The embodiment of the invention aims to protect a multi-master switching type high-speed interconnection backboard bus, a control method and a processing system thereof, wherein the method comprises the following steps: the method comprises the following steps: a programmable bus protocol controller; the programmable bus protocol controller is electrically connected with a plurality of processors and a plurality of peripheral modules of the processing system respectively, receives control instructions of the processors, and converts one-to-one, one-to-many or many-to-one concurrent bus access of a plurality of processes into virtual end-to-end connection by performing virtual address conversion on the peripheral modules corresponding to the control instructions so as to improve the data transmission efficiency of the backplane bus. The technical scheme has the following effects: by adopting the star-shaped connection structure of the programmable bus protocol controller, the processors and the peripheral modules, the problem of bus resource limitation of concurrent access of the multiple processors is solved, the data packet collision rate is reduced, the multiple processors are allowed to simultaneously initiate bus access or a single processor simultaneously initiates access of multiple external devices, and the aggregation of computing power of the multiple processors is realized; meanwhile, the exchange type interconnection bus structure can effectively reduce the complexity of a back plate bus, and enables the whole system to have better expansibility and flexible configuration capability, thereby being capable of being quickly applied to various industrial control application scenes.
It is to be understood that the above-described embodiments of the present invention are merely illustrative of or explaining the principles of the invention and are not to be construed as limiting the invention. Therefore, any modifications, equivalents, improvements and the like which are made without departing from the spirit and scope of the present invention shall be included in the protection scope of the present invention. Further, it is intended that the appended claims cover all such variations and modifications as fall within the scope and boundaries of the appended claims or the equivalents of such scope and boundaries.
Claims (9)
1. A multi-master switching high-speed interconnect backplane bus comprising: a programmable bus protocol controller;
the programmable bus protocol controller is respectively and electrically connected with a plurality of processors and a plurality of peripheral modules of the processing system,
the programmable bus protocol controller receives the control instructions of the processors, and converts the one-to-one, one-to-many or many-to-one concurrent bus access of the plurality of processes into virtual end-to-end connection by performing virtual address conversion on the plurality of peripheral modules corresponding to the control instructions, so as to improve the data transmission efficiency of the backplane bus.
2. The multi-master switched high-speed interconnect backplane bus of claim 1,
the programmable bus protocol controller comprises: a programmable device;
and the programmable bus protocol controller realizes data interaction with the processors and the peripheral modules respectively through the I/O of the programmable device.
3. The multi-master switched high-speed interconnect backplane bus of claim 1,
the message header of the primary backboard communication access of the control instruction comprises: the type of module from which the access was issued, slot number, destination address, and/or task priority.
4. The multi-master switched high-speed interconnect backplane bus of claim 1,
the programmable bus protocol controller is provided with a storage unit which comprises an internal storage unit and/or an external storage unit;
the programmable device receives tasks and data sent by any processor and stores the tasks and data to the storage unit;
and the processor reads the task and the data at idle time and processes the task and the data.
5. The multi-master switched high-speed interconnect backplane bus of claim 4,
and other processors can read and process the tasks and data stored in the storage unit.
6. A method for controlling a multi-master switching high-speed interconnect backplane bus according to any one of claims 1 to 5, comprising the steps of:
receiving control instructions of a plurality of processors of a processing system;
when the control instructions of the plurality of processors correspond to the same peripheral module, performing virtual address conversion on the peripheral module;
and judging whether the data of the peripheral module is valid data or not according to the use condition of the peripheral module, if so, mapping the peripheral access initiated by the processors to the virtual address of the peripheral module so as to realize the concurrent access of the processors to the peripheral module.
7. A method for controlling a multi-master switching high-speed interconnect backplane bus according to any one of claims 1 to 5, comprising the steps of:
receiving control instructions of a plurality of processors of a processing system;
when the control instructions of the plurality of processors correspond to the plurality of peripheral modules, the programmable bus protocol controller respectively performs virtual address conversion on the plurality of peripheral modules according to the control instructions of the plurality of processors;
the processors and the peripheral modules form a virtual one-to-one link so as to realize the concurrent access of the processors to the corresponding peripheral modules respectively.
8. A method for controlling a multi-master switching high-speed interconnect backplane bus according to any one of claims 1 to 5, comprising the steps of:
receiving a control instruction of a processing system processor;
when a control instruction of the processor corresponds to a plurality of peripheral modules, carrying out virtual address conversion on the plurality of peripheral modules;
and simultaneously accessing the peripheral modules according to the control instruction of the processor in an interrupt mode, integrating the return data of the peripheral modules into a data packet with complete synchronism by a programmable bus protocol controller, and sending the data packet to the processor.
9. A processing system, comprising: a plurality of treater and a plurality of peripheral hardware module still include: the multi-master switched high-speed interconnect backplane of any of claims 1-5;
and the plurality of processors and the plurality of peripheral modules perform data interaction through the multi-master switching type high-speed interconnection backboard.
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| CN202110710015.7A CN115525596A (en) | 2021-06-25 | 2021-06-25 | Multi-master switching type high-speed interconnection backplane bus, control method thereof and processing system thereof |
| PCT/CN2021/131726 WO2022267318A1 (en) | 2021-06-25 | 2021-11-19 | Multi-master-switch-type high-speed interconnection backplane bus, control method therefor, and processing system thereof |
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| CN202110710015.7A CN115525596A (en) | 2021-06-25 | 2021-06-25 | Multi-master switching type high-speed interconnection backplane bus, control method thereof and processing system thereof |
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| CN104539632B (en) * | 2015-01-20 | 2017-12-12 | 中国人民解放军国防科学技术大学 | A kind of PN device management control method based on virtual address space |
| US9626300B2 (en) * | 2015-07-27 | 2017-04-18 | Google Inc. | Address caching in switches |
| US10402218B2 (en) * | 2016-08-30 | 2019-09-03 | Intel Corporation | Detecting bus locking conditions and avoiding bus locks |
| CN107995081A (en) * | 2017-12-29 | 2018-05-04 | 徐州中矿大传动与自动化有限公司 | The system and method for a variety of communication bus conversions is supported at the same time |
| CN109634673A (en) * | 2018-12-06 | 2019-04-16 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Satellite borne electronic system management and control equipment |
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