CN115509468B - Method for improving life cycle of SSD - Google Patents
Method for improving life cycle of SSD Download PDFInfo
- Publication number
- CN115509468B CN115509468B CN202211473522.4A CN202211473522A CN115509468B CN 115509468 B CN115509468 B CN 115509468B CN 202211473522 A CN202211473522 A CN 202211473522A CN 115509468 B CN115509468 B CN 115509468B
- Authority
- CN
- China
- Prior art keywords
- ssd
- groups
- qlc
- group
- flash memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention provides a method for improving the life cycle of an SSD, which comprises the following steps: s1, coding N bit sequence of flash memory unit of SSD into 2 N A code group corresponding to 2 N A reference voltage, N>1 is a positive integer; s2, mapping the coding groups to data of k bits to obtain M rewriting groups, 0<k<N, k and M are positive integers; and S3, writing data into the flash memory unit based on the M rewriting groups, wherein only k bits can be written at a time. The invention can rewrite each flash memory unit for a plurality of times before being erased by recoding the bit of each flash memory unit, thereby reducing the erasing times of the flash memory units and improving the life cycle of the whole SSD.
Description
Technical Field
The invention relates to the technical field of data storage, in particular to a method for improving the life cycle of an SSD.
Background
As is well known, flash-based Solid State Disks (SSDs) provide faster read and write rates and lower read and write latencies compared to conventional mechanical hard disks (HDDs), but they have one major limitation: unlike a mechanical hard disk that can overwrite an already written data area, a flash memory cell requires an erase operation prior to overwriting, each erase operation causing wear and tear, thereby shortening the life of the cell. Older generation flash SLC (single-level cell) store only one bit in one cell, which can typically tolerate over ten thousand P/E (Program/Erase) cycles before wear out. However, to meet the increasing demand for storage capacity, more bits need to be stored in one cell. But every additional bit stored in 1 SSD cell, the number of erase cycles that the SSD can withstand is reduced by an order of magnitude. With high density SSDs such as QLC (Quad-Level Cell,4 bits/Cell) and PLC (Penta-Level Cell,5 bits/Cell), it can be seen that the P/E period falls to tens or hundreds. In order to make high density SSD drives (e.g., QLC and PLC) available in more applications, it is important to reduce the number of times the storage medium is erased.
To improve the lifetime of SSDs, many techniques are provided to reduce the number of flash memory die P/E times. The current main technology for reducing the P/E times of the solid state disk comprises the following steps: 1) The address space virtualization technology avoids that hot spot data are frequently erased and written into the same physical area; 2) Capacity redundancy, in order to avoid failure of a whole SSD caused by damage of a part of flash memories, the capacity redundancy can be realized during design of the SSD, for example, a nominal 100GB SSD, the actual physical capacity of the internal flash memories is generally more than 110GB, generally speaking, the larger the redundancy ratio is, the better the reliability, the service life and the performance of the SSD are, and the redundancy ratio of enterprise-level storage products generally reaches more than 28%; 3) And wear leveling, namely recording the P/E times of each block, and selecting the blocks with relatively low P/E times as much as possible when data needs to be erased or written, wherein the service life of the SSD subjected to wear leveling can be maximized.
In the prior art, the erasing balance of the SSD is emphasized, the erasing period of the SSD is close to the theoretical erasing period of the flash memory particles as much as possible, and the current situation that each flash memory unit can only be written once before being erased is not changed.
Disclosure of Invention
In order to solve the technical problem that each flash memory unit can only be written once before being erased in the prior art, the method for improving the life cycle of the SSD is characterized by comprising the following steps of:
s1, coding N bit sequence of flash memory unit of SSD into 2 N A code group corresponding to 2 N A reference voltage, N>1 is a positive integer;
s2, mapping the coding groups to data of k bits to obtain M rewriting groups, wherein 0 & ltk & ltn & gt and n & ltk & gt are positive integers;
and S3, writing the data into the flash memory unit based on the M rewriting groups, wherein only k bits can be written at a time.
Preferably, in S1, taking the QLC SSD drive as an example, the flash memory unit 4-bit sequence of the QLC drive is encoded into 16 encoding groups, which correspond to 16 reference voltages of the QLC drive, 0000 is the lowest reference voltage, and 1111 is the maximum reference voltage.
Preferably, in S2, when k =1, M =2 N -1，1<k<When N, M = [2 ] N /(2 k -1)],“[]"denotes a rounding operation, extracting the integer part of the computation result.
Preferably, in S2, the encoding process includes the following steps:
s21, mixing 2 N First 2 of the coding groups k Mapping each coding group into a rewriting group 1, and initializing a parameter i to 1;
s22, the last code group in the rewriting group i is used as a shared code group to become a new starting point, and 2 is acquired again k The coding groups are mapped into a rewriting group (i + 1), and the parameter i is updated after being increased by 1;
s23, judgment (2) N -（2 k -1）*i)< 2 k If yes, entering S24, otherwise, returning to S22;
and S24, ending the coding.
Preferably, in S2, taking a QLC SSD drive as an example, when k =1, the QLC SSD drive is divided into 15 rewrite groups, which are (0000, 0001), (0001, 0010), (0010, 0011), (0011, 0100), (0100, 0101), (0101, 0110), (0110, 0111), (0111, 1000), (1000, 1001), (1001, 1010), (1010, 1011), (1011, 1100), (1100, 1101), (1101, 1110), (1110, 1111), respectively.
Preferably, in S2, taking the QLC SSD drive as an example, when k =2, the rewrite groups are divided into 5 rewrite groups, which are (0000, 0001,0010, 0011), (0011, 0100,0101, 0110), (0110, 0111,1000, 1001), (1001, 1010,1011, 1100), (1100, 1101,1110, 1111), respectively.
Preferably, in S2, taking the QLC SSD drive as an example, when k =3, the rewrite groups are divided into 2 rewrite groups, which are (0000, 0001,0010, 0011,0100, 0101,0110, 0111), (0111, 1000,1001, 1010,1011, 1100,1101, 1110).
Preferably, in S3, two writing methods are adopted: 1) Jumping among the M rewriting groups to realize data writing; 2) Data conversion is performed within the same overwrite group.
Preferably, in S3, when data is written by jumping among the M rewrite groups, taking the QLC SSD drive as an example, the number of rewrites is 15 when k =1, 5 when k =2, and 2 when k = 3.
The computer storage medium provided by the invention stores a computer program, and the processor can realize the method for improving the life cycle of the SSD by running the computer program.
Compared with the prior art, the invention has the following beneficial effects:
by recoding the bits of each flash memory unit, each flash memory unit can be rewritten for a plurality of times before being erased, thereby reducing the erasing times of the flash memory units and improving the life cycle of the whole SSD.
Drawings
FIG. 1 is a flow chart of a method of the present invention for improving the lifecycle of an SSD.
Detailed Description
In order to more clearly understand the technical features, objects, and effects of the present invention, embodiments of the present invention will now be described with reference to the accompanying drawings.
In order to describe the method for protecting the cache data under the abnormal restart of the system more clearly, the storage structure of the cache part in the present invention is now explained:
for a better description of the present invention, the storage principle of an N-Level Cell SSD drive will now be explained. A flash memory Cell of an N-Level Cell SSD drive may store N bits corresponding to 16 different levels of reference voltages for transistors in the SSD, where each reference voltage represents an N-bit binary code, and, for example, a QLC SSD drive may store 4 bits corresponding to 16 different levels of reference voltages for transistors in the SSD, where each reference voltage represents a 4-bit binary code. Any transition between different states of a flash memory cell is controlled by the current reference voltage level, and the following rules must be followed: the reference voltage level may be increased in a single direction, but only decreased if erased first, which is independent of the value of a single bit of the 4-bit value stored in the flash memory cell.
As shown in fig. 1, the method for improving the life cycle of the SSD specifically includes the following steps:
s1, coding N bit sequence of flash memory unit of SSD into 2 N A code group corresponding to 2 N A reference voltage, N>1, which is a positive integer, taking QLC SSD drive as an example, the flash memory unit 4-bit sequence of QLC drive is encoded into 16 encoding groups, which correspond to 16 reference voltages of QLC drive, 0000 is the lowest reference voltage and 1111 is the maximum reference voltage.
S2, mapping the coding groups to data of k bits to obtain M rewriting groups, 0<k<N, k and M are positive integers, and when k =1, M =2 N -1，1<k<When N, M = [2 ] N /(2 k -1)],“[]"denotes a rounding operation, extracting the integer part of the computation result, and specifically, k bits may express 2 k One data, for example, 2 bits may express 4 data: 0001, 10,11, the encoding process comprises the following steps:
s21, mixing 2 N First 2 in one coding group k Mapping each coding group into a rewriting group 1, and initializing a parameter i to 1;
s22, the last code group in the rewriting group i is used as a shared code group to become a new starting point, and 2 is acquired again k The coding groups are mapped into a rewriting group (i + 1), and the parameter i is updated after being increased by 1;
s23, judgment (2) N -（2 k -1）*i)< 2 k If yes, entering S24, otherwise, returning to S22;
and S24, ending the coding.
The shared code group is set only for increasing the number of rewrite groups, and for increasing the number of rewrites, taking a QLC SSD drive as an example, in the case of k =1, 15 rewrite groups are divided into (0000, 0001), (0001, 0010), (0010, 0011), (0011, 0100), (0100, 0101), (0101, 0110), (0110, 0111), (0111, 1000), (1000, 1001, 1010), (1010, 1011), (1011, 1100, 1101), (1101, 1110), (1110, 1111), in the case of k =2, 5 rewrite groups are divided, respectively, (0000, 0001,0010, 0011), (0011, 0100,0101, 0110), (0110, 0111,1000, 1001), (1001, 1010,1011, 1100), (1100, 1101,1110, 1111), and in the case of k =3, 2 rewrite groups are divided, respectively, (0000, 0001,0010, 0011,0100, 0101,0110, 0111), (0111, 1000,1001, 1010,1011, 1100,1101, 1110).
S3, writing data into the flash memory unit based on M rewriting groups, wherein only k bits can be written at each time, and specifically, the writing method is divided into two writing modes:
1) Taking a QLC SSD drive as an example, when k =2, if the 5-time write sequence is 01,10, 11,01, 01, for a newly erased flash memory cell of the QLC drive, only the reference voltage needs to be sequentially increased to 0001, 0110,0111, 1001, 1101, and each time a higher rewrite group is written, only the voltage of the flash memory cell needs to be increased, and the flash memory cell does not need to be erased before increasing to the maximum reference voltage 1111, and at this time, the same flash memory cell can be rewritten 5 times without erasing, and similarly, when k =1, the number of times of rewriting is 15, and when k =3, the number of times of rewriting is 2.
2) More rewrite times can be provided by performing data conversion within the same rewrite group, taking a QLC SSD drive as an example, k =2, if the data sequences 01,10 and 11 are written in 3 consecutive write cycles, the write cycles 1 to 3 are encoded and the reference voltage levels are changed to 0001,0010 and 0011, respectively, the second write does not require a reference voltage transition to rewrite group 2, only the reference voltage needs to be increased from 0001 to 0010, both voltages are located within rewrite group 1, and the same holds for the third write.
Compared with the prior art, the invention has the following beneficial effects:
1) Taking a QLC SSD drive as an example, there are three coding schemes of k =1, k =2 and k =3, and although 4 times, 2 times and 1.33 times of physical space overhead is needed, 15 times, 5 times and 2 times of logical data can be written for the coding schemes, respectively, which has a huge gain compared to no coding scheme, and 375% of extra space is provided for each physical unit when k =1, 250% of extra space is provided for each physical unit when k =2, and 150% of extra logical space is provided for each physical unit when k = 3.
2) The flash memory has natural flash memory friendliness, in the invention, the reference voltage level is increased only within a shorter voltage level range, taking a QLC SSD driver as an example, in the case of k =2, the reference voltage can only jump within 5 rewrite groups, and unlike the non-coding scheme in which the reference voltage is arbitrarily increased within 16 reference voltages, the coding scheme has less voltage increase frequency, that is, a smaller amount of charge is injected into the flash memory cells, thereby reducing the program disturb error of the flash memory.
The above disclosure is only for the purpose of illustrating the preferred embodiments of the present invention, and it should not be understood that the scope of the present invention is limited thereby. It should be noted that those skilled in the art should recognize that they may make equivalent variations to the embodiments of the present invention without departing from the spirit and scope of the present invention.
Claims (10)
1. A method for improving the life cycle of an SSD, the method comprising the steps of:
s1, coding N bit sequence of flash memory unit of SSD into 2 N A code group corresponding to 2 N A reference voltage, N>1, is a positive integer;
s2, mapping the coding groups to data of k bits to obtain M rewriting groups, wherein 0-k-n, and k and M are positive integers;
and S3, writing the data into the flash memory unit based on the M rewriting groups, wherein only k bits can be written at a time.
2. The method of claim 1, wherein in S1, for example, a QLC SSD drive, a flash memory unit 4-bit sequence of the QLC drive is encoded into 16 encoding groups, which correspond to 16 reference voltages of the QLC drive, 0000 is the lowest reference voltage and 1111 is the maximum reference voltage.
3. The method of claim 1, wherein in S2, when k =1, M =2 N -1，1<k<When N, M = [2 ] N /(2 k -1)],“[]"denotes a rounding operation, extracting the integer part of the computation result.
4. The method of claim 1, wherein in the step S2, the encoding process comprises the following steps:
s21, mixing 2 N First 2 in one coding group k Mapping each coding group into a rewriting group 1, and initializing a parameter i to 1;
s22, the last code group in the rewriting group i is used as a shared code group to become a new starting point, and 2 is acquired again k The coding groups are mapped into a rewriting group (i + 1), and the parameter i is updated after being increased by 1;
s23, judgment (2) N -（2 k -1）*i)< 2 k If yes, entering S24, otherwise, returning to S22;
and S24, ending the coding.
5. The method of claim 4, wherein in S2, taking a QLC SSD driver as an example, in the case of k =1, the driver is divided into 15 rewrite groups of (0000, 0001), (0001, 0010), (0010, 0011), (0011, 0100), (0100, 0101), (0101, 0110), (0110, 0111), (0111, 1000), (1000, 1001), (0101010, 1011), (1011, 1100), (1100, 1101), (1101, 1110), (1110, 1111).
6. The method of claim 4, wherein in S2, taking a QLC SSD drive as an example, in the case of k =2, the SSD drive is divided into 5 rewrite groups, respectively (0000, 0001,0010, 0011), (0011, 0100,0101, 0110), (0110, 0111,1000, 1001), (1001, 1010,1011, 1100), (1100, 1101,1110, 1111).
7. The method of claim 4, wherein in S2, taking a QLC SSD drive as an example, in the case of k =3, the SSD drive is divided into 2 rewrite groups, which are (0000, 0001,0010, 0011,0100, 0101,0110, 0111), (0111, 1000,1001, 1010,1011, 1100,1101, 1110).
8. The method according to claim 1, wherein in S3, there are two writing methods: 1) Jumping among the M rewriting groups to realize data writing; 2) Data conversion is performed within the same overwrite group.
9. The method according to claim 8, wherein in S3, when data writing is implemented by jumping among M rewrite groups, taking a QLC SSD drive as an example, the number of rewrites is 15 in the case of k =1, 5 in the case of k =2, and 2 in the case of k = 3.
10. A computer storage medium, characterized in that the computer storage medium stores a computer program, and a processor can implement the method for improving the life cycle of SSD according to any one of claims 1-9 by running the computer program.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211473522.4A CN115509468B (en) | 2022-11-23 | 2022-11-23 | Method for improving life cycle of SSD |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211473522.4A CN115509468B (en) | 2022-11-23 | 2022-11-23 | Method for improving life cycle of SSD |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115509468A CN115509468A (en) | 2022-12-23 |
| CN115509468B true CN115509468B (en) | 2023-03-24 |
Family
ID=84513793
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211473522.4A Active CN115509468B (en) | 2022-11-23 | 2022-11-23 | Method for improving life cycle of SSD |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115509468B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104572334A (en) * | 2013-10-14 | 2015-04-29 | 群联电子股份有限公司 | Decoding method, memory storage device and memory control circuit unit |
| CN104575596A (en) * | 2013-10-10 | 2015-04-29 | 北京兆易创新科技股份有限公司 | Decline resistant flash memory and decline resistant method |
| CN105989883A (en) * | 2015-02-26 | 2016-10-05 | 群联电子股份有限公司 | Memory programming method, memory storage device and memory control circuit unit |
| CN108038026A (en) * | 2017-11-17 | 2018-05-15 | 中国科学院信息工程研究所 | A kind of data quick recovery method and system based on flash memory |
| US10665303B1 (en) * | 2019-05-10 | 2020-05-26 | Macronix International Co., Ltd. | Erasing blocks with few programmed pages |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11487455B2 (en) * | 2020-12-17 | 2022-11-01 | Pure Storage, Inc. | Dynamic block allocation to optimize storage system performance |
-
2022
- 2022-11-23 CN CN202211473522.4A patent/CN115509468B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104575596A (en) * | 2013-10-10 | 2015-04-29 | 北京兆易创新科技股份有限公司 | Decline resistant flash memory and decline resistant method |
| CN104572334A (en) * | 2013-10-14 | 2015-04-29 | 群联电子股份有限公司 | Decoding method, memory storage device and memory control circuit unit |
| CN105989883A (en) * | 2015-02-26 | 2016-10-05 | 群联电子股份有限公司 | Memory programming method, memory storage device and memory control circuit unit |
| CN108038026A (en) * | 2017-11-17 | 2018-05-15 | 中国科学院信息工程研究所 | A kind of data quick recovery method and system based on flash memory |
| US10665303B1 (en) * | 2019-05-10 | 2020-05-26 | Macronix International Co., Ltd. | Erasing blocks with few programmed pages |
Non-Patent Citations (2)
| Title |
|---|
| 《基于NAND FLASH的高性能存储器设计》;陈若娜;《中国优秀硕士学位论文全文数据库》;20200215;全文 * |
| 《基于SSD的多层次存储结构关键技术研究》;陈志广;《中国优秀硕士学位论文全文数据库》;20160315;全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115509468A (en) | 2022-12-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10372342B2 (en) | Multi-level cell solid state device and method for transferring data between a host and the multi-level cell solid state device | |
| US9547588B1 (en) | System and method of data storage in flash memory | |
| CN111326199B (en) | Multi-state programming for memory devices | |
| Jagmohan et al. | Write amplification reduction in NAND flash through multi-write coding | |
| CN102394101B (en) | Memory device with adaptive capacity | |
| US20110138104A1 (en) | Multi-write coding of non-volatile memories | |
| US8612667B2 (en) | Method for performing data pattern management regarding data accessed by a controller of a flash memory, and associated memory device and controller thereof | |
| US8719491B2 (en) | Encoding flash memory data with a randomizer using different seeds for different sectors | |
| JP2015064925A (en) | Method for reading data in multiple bits per cell (mbc) non-volatile memory, memory controller, and system | |
| JP5259138B2 (en) | Storage device | |
| US9171629B1 (en) | Storage device, memory controller and memory control method | |
| CN114175163A (en) | Performing refresh operations based on characteristics of a memory subsystem | |
| Jagmohan et al. | Adaptive endurance coding for NAND flash | |
| US20220129204A1 (en) | Extended cross-temperature handling in a memory sub-system | |
| CN110795270A (en) | Solid state storage device and read retry method thereof | |
| CN111352859A (en) | Bad block management for memory subsystems | |
| CN111813591B (en) | Data error correction method and device of Nand Flash, electronic equipment and storage medium | |
| WO2021011416A1 (en) | Read voltage management based on write-to-read time difference | |
| KR20160150036A (en) | Memory system for partial page compression | |
| CN112181710B (en) | Solid-state disk data storage method and device based on bit flipping | |
| CN115509468B (en) | Method for improving life cycle of SSD | |
| CN109522237B (en) | Data management method of memory and memory device | |
| JP2011134031A (en) | Semiconductor recording device and semiconductor recording system | |
| KR101661048B1 (en) | Error protection for memory devices | |
| CN106033681B (en) | Memory control circuit unit, memory storage device and data access method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |