CN1154931C - Pipe-lining and impulsing single command multiple data matrix treating structure and method therefor - Google Patents
Pipe-lining and impulsing single command multiple data matrix treating structure and method therefor Download PDFInfo
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- CN1154931C CN1154931C CNB951079190A CN95107919A CN1154931C CN 1154931 C CN1154931 C CN 1154931C CN B951079190 A CNB951079190 A CN B951079190A CN 95107919 A CN95107919 A CN 95107919A CN 1154931 C CN1154931 C CN 1154931C
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Abstract
The present invention relates to an array processing structure and a method for a pipelining and impulsing single-instruction multiple-data stream. The array processing structure is mainly composed of an array with pipelining elements connected in series, a delay temporary memory group, a multiplexer, etc., the input end and the output end of each pipelining element are added with a plurality of groups of delay temporary memory arrays and the multiplexer for data transfer, wherein the delay temporary memory arrays are composed of one or the a plurality of delay temporary memories; data is transmitted to and from each pipelining element in a broadcasting and impulsing mixed mode and is controlled by a single controller. Thus, the present invention has higher speed in processing the functions of calculation, shift, conversion, accessing, etc., and switching circuit elements can be added between the input/output ends of the pipelining elements and the temporary memory arrays, which enables data transmission faster and diversified.
Description
The present invention relates to a kind of pipeline system-pulsed-single instruction multiple data ARRAY PROCESSING structure and method thereof, be a kind of design that applies to computer parallel processing device, presentation manager and digital signal processing, so that the circuit structure of better efficient is arranged in its data transmission procedure.
In the design of computer parallel processing device, presentation manager and digital signal processing, the patent of invention that the applicant once declared a kind of " pipeline system-pulsed-single instruction multiple data ARRAY PROCESSING structure and method thereof ", number of patent application is: 94101719.2.It is made of pipeline system treatment element (PipelinedProcessing Element), working storage (register) and multiplexer circuit devcies such as (multiplexers), it is to add that at the input end of each treatment element and output terminal several working storages and multiplexer carry out data transmission, the mode of mixing broadcast type (Broadcasting) and pulsed (Systolic) is transmitted data and is passed in and out each treatment element, and uses single controller to control.This circuit structure is fast in aspect speed such as deal with data computing, displacement, conversions, and each treatment element only need use small amount of memory, saves operation time, can also save spent plenty of time and the connecting line of data input simultaneously.Through practice test after a while, the applicant has made some improvement again on the basis of foregoing invention application.
The purpose of this invention is to provide a kind ofly in processing procedures such as data I/O, displacement, conversion and access, faster, more high efficiency pipeline system (Pipelined)-pulsed (Systolic)-single instruction multiple data ARRAY PROCESSING structure and method can be arranged.
The present invention is achieved in that by a plurality of pipeline system elements and forms the array agent structure, to organize the delay buffer storage group pattern more more, be located at the input end and the output terminal of pipeline system element body structure respectively, in addition with one group of broadcast type transmission line, be connected the input end of pipeline system element body structure, with feedback output and the extraneous data of importing of accepting the pipeline system element body structure, and the main body array of pipeline system element, its input end is connected input with many group delay buffer storage group patterns, the output terminal of the main body array of this pipeline system element, also serial connection organizes the delay buffer storage group pattern, and the delay buffer storage in above-mentioned each delay buffer storage group pattern, multiplexer and pipeline system element are controlled by the connection of a controller all; It includes: a controller; The array agent structure that several pipeline system elements constitute; Be connected with the pulsed method by several buffers, and be located at the input buffer array of pipeline system access devices agent structure input end; Be connected in series mutually in the heartbeat mode by several buffers, and distinguish configure multiplexer, and be located at the output state array of pipeline system access devices agent structure output terminal in the transmission ends of each buffer; Buffer in above-mentioned each cache array, multiplexer and pipeline system element all are connected with above-mentioned controller and controlled by it.
It also can be to include: a controller; The array agent structure that several pipeline system elements constitute; Many group delay buffer storage arrays, its delay buffer storage group is made up of one or more delay buffer storage, and be connected in series each delay buffer storage group in the heartbeat mode, and transmission ends difference configure multiplexer in each delay buffer storage group, these delay buffer storage group patterns are separately positioned on the input end and the output terminal of pipeline system element body structure; One group of broadcast type transmission line is connected the input end of pipeline system element body structure, to accept the feedback output and the extraneous input data of pipeline system element body structure; Delay buffer storage group multiplexer in above-mentioned each delay buffer storage group pattern and pipeline system element all are connected with above-mentioned controller and controlled by it.
Wherein the pipeline system access devices includes a memory element, its input end is connected with buffer, Input Address generator, input writing controller, output terminal then is connected with OPADD generator, output Read Controller, and links to each other with extraneous pulsed structural transmission line by buffer and ternary whole controller; The I/O address generator, its input end links to each other with controller, and output terminal then joins with the I/O end of above-mentioned storer respectively; Read Controller is write and is exported in input, and its input end links to each other with controller, and output terminal then links to each other with the I/O end of above-mentioned storer respectively; Several buffers are separately positioned between storer and extraneous data line join, and ternary controller, place between the buffer and extraneous data line that the storer output terminal connected, and link to each other with the output Read Controller.
The wherein input end and the output terminal of the main body array of pipeline system access devices, and between input and the output state array are connected with and switch circuit elements, and this switches circuit elements with controller and is connected.
Wherein the main body array that is made of several pipeline system elements is the array that is become with the treatment element serial connection.
Wherein the main body array that is made of several pipeline system elements forms with pipeline system central processing unit serial connection.
The main body array structure of pipeline system element wherein, many groups delay buffer storage group pattern that its output terminal connects has the function of transmitted in both directions and ring shift, so also can be used as the input end of above-mentioned pipeline system element arrays.
The main body array structure of pipeline system element wherein, many groups delay buffer storage array that its output terminal connects is provided with feedback assembly, can be used as the input end of pipeline system element arrays.
The disposal route of array structure of the present invention includes the following step: this method includes the following step: send data to first input displacement delay buffer storage group pattern from data set with pulsed; Data are sent to second input displacement delay buffer storage group pattern from data set with pulsed; Data are sent to above-mentioned first displacement delay buffer storage group pattern and pipeline system element group abreast from above-mentioned second input displacement delay buffer storage group pattern; By an input broadcast type circuit, data are transferred to above-mentioned pipeline system element group from above-mentioned data set; By multiplexer and above-mentioned input broadcast type circuit, data are sent to the input end of pipeline system element group from the wired-OR gate output terminal; Data are imported parallel second input end that is sent to above-mentioned pipeline system element group of displacement delay buffer storage group pattern from above-mentioned first; Data are sent to first input end of above-mentioned pipeline system element group from above-mentioned input broadcast type circuit; Under programmable operator scheme, make the inner computing function of carrying out of above-mentioned pipeline system element group; By multiplexer, with the parallel output displacement delay buffer storage array that is sent to of the output terminal of result of calculation in above-mentioned pipeline system element group; Result of calculation is sent to pipeline system element group or data set from above-mentioned output with being shifted delay buffer storage array pulsed; Result of calculation is sent to said apparatus from the wired-OR gate output terminal; And under the control of controller, above-mentioned input displacement delay buffer storage group pattern, input broadcast type circuit, pipeline system element group, output displacement delay buffer storage group pattern, wired-OR gate circuit of output terminal and data set are operated concurrently, to carry out the transmission and the calculation process of data.Wherein one-piece construction is to adopt multidimensional structure.The control signal of its middle controller can be to mix broadcast type control method and pulsed control method.
Characteristics of the present invention are to improve the processing speed of data output/input, displacement, conversion and access, improve treatment effeciency, thereby can save the number of pins of its data line number and integrated circuit, avoid because of operation circuit quantity too many mixed and disorderly, improve the service efficiency of storer, so that can be made into a circuit of single-chip integrated.This circuit of single-chip integrated then can directly be installed on the computer or television, produces many image processings effect, and is both practical and convenient.The signal of output delay buffer group pattern of the present invention also can be used as the input of pipeline system component structure, makes the transmission computing of data more quick and convenient; Pipeline system element in its entire array can be access devices, to realize finishing high speed processing with low speed devices.In addition, in its input end delay buffer storage group pattern, can use many group delay buffer storage group patterns simultaneously side by side, cooperate broadcast type (Broadcasting) transmission line again, to gather way.Moreover the control signal of its controller can be broadcast type control method, and cooperates heart method control, to realize data processing function.Another characteristics of the present invention are can be at the main body array input end and the output terminal of pipeline system element, switch circuit elements with being connected between many groups delay buffer storage group pattern, make data transmission diversification and more rapid more.
Below in conjunction with accompanying drawing,, do specifically to introduce to detailed construction of the present invention, application principle, effect and effect.
Fig. 1 is the line assumption diagram that pipeline system element of the present invention is the pipeline system memory element.
Fig. 2 is a pipeline system element of the present invention when being the pipeline system memory element, memory element internal wiring structural drawing.
Fig. 3 is that pipeline system element of the present invention is pipeline system memory element and the line assumption diagram that cooperates switched circuit.
Fig. 4 is a switched circuit data-transmission mode synoptic diagram of the present invention.
Fig. 5 is that pipeline system element of the present invention is the embodiment circuit structure diagram that pipeline system treatment element and output offset buffer array have two-way function.
Fig. 6 is that pipeline system element of the present invention is the pipeline system treatment element and has feedback assembly and the embodiment circuit structure diagram of ring shift function output.
Fig. 7 is another embodiment circuit structure diagram that pipeline system element of the present invention is the pipeline system treatment element.
Fig. 8 is the embodiment circuit structure diagram that pipeline system element of the present invention is a pipelined processor.
Circuit structure diagram referring to pipeline system pulsed single instruction multiple data ARRAY PROCESSING structure of the present invention shown in Figure 1.Its input and output side at pipeline system access devices Mi-Mn is all installed some buffer R and multiplexer M, and this buffer R and multiplexer M are concatenated into cache array with the pulsed method, and be located at the output terminal of pipeline system element body structure, this buffer R also is concatenated into cache array and is located at the input end of pipeline system element body structure, and this pipeline system access devices Mi-Mi serial connection becomes agent structure, the buffer R in above-mentioned each cache array, the connection control of multiplexer R and all controlled device of pipeline system access devices Mi-Mn (Control Unit).
Referring to Fig. 2, this pipeline system access devices is made up of storer, Input Address generator, OPADD generator, input writing controller, output Read Controller and buffer, ternary controller.Wherein, the input end of Input Address generator is connected with above-mentioned controller, and output terminal then joins with the input end of storer; The input end of input writing controller connects above-mentioned controller, and output terminal then joins with the input end of storer.The input end of OPADD generator is connected with above-mentioned controller, and output terminal then is connected with the output terminal of storer; The input end of output Read Controller is connected to above-mentioned controller, and the output terminal of output terminal and storer joins.Buffer then is located between storer and the extraneous data line, and ternary controller places between the buffer and extraneous data line that the storer output terminal connected, and controlled by read-write controller.
Referring to Fig. 3, input end and output terminal at pipeline system access devices Mi-Mn main body array, and between many groups cache array, be connected with switched circuit (Switching Circuit) element, and this switches circuit elements is to connect control with controller (Control Unit), make data transmission that various modes (referring to Fig. 4) can be arranged, so that on data transmission shifts, variation more.
Referring to the array structure based on four pipeline system access devices shown in Figure 4 is example, and the multiple mode of operation of switched circuit can be:
mode0 UVWX＝abcd
mode1 UVWX＝bcda
mode2 UVWX＝cdab
mode3 UVWX＝dabc
Another circuit structure diagram referring to pipeline system pulsed single instruction multiple data ARRAY PROCESSING structure of the present invention shown in Figure 5.It is several delay buffer storage group (Registers-Delay) and multiplexer M of installing on the input end of pipeline system element Ui-Un and output terminal, this delay buffer storage group can be made of (referring to Fig. 9) one or several delay buffer storages, wherein the buffer number is looked and is determined time delay, and be controlled by the controller, and this delay buffer storage is formed multiplexer M and is concatenated into the delay buffer storage group pattern in the heartbeat mode, and be located at the input end and the output terminal of pipeline system element body structure respectively, and this pipeline system element Ui-Un serial connection is agent structure, and there is one group of broadcast type transmission line to be connected in the input end of pipeline system element Ui-Un agent structure, with the feedback output of accepting the pipeline system element body structure and external world's input data that data set (Data Derices) is transmitted, and the main body array of pipeline system element Ui-Un, its input end is connected input with many group delay buffer storage group patterns, the output terminal of the main body array of this pipeline system element Ui-Un, also serial connection is organized the delay buffer storage arrays more, and this delay buffer storage group pattern has the function of transmitted in both directions, and the delay buffer storage in above-mentioned each delay buffer storage group pattern, multiplexer M, and the connection of all controlled device of pipeline system element Ui-Un (Control Unit) control.
Referring to Fig. 6, delay buffer storage group pattern at pipeline system element Ui-Un array output end, can by control multiplexer delay buffer storage group pattern with data transmission to pipeline system element Ui-Un array, reach the effect of reverse input, and this delay buffer storage group pattern has the function of ring shift, makes data more rapid on transmission is passed on.
Referring to Fig. 7, between the agent structure of pipeline system element Ui-Un, respectively add a buffer, and be controlled by the controller with progressive mode.Control signal can be broadcast type control (BroadcastingControl), also can be pulsed control (Systolic Control).
Referring to Fig. 8, wherein the pipeline system element is to be main body unit body with the pipelined processor, this pipelined processor includes central processing unit (Central Processing Unit), storer (Memory), I/O data sequence (I/O Data Queues) and bus controller (BusController), for operation of data, access, transmission, I/O, more can be to carry out at a high speed and can be widely used in each side such as image processing, digital signal processing and computer parallel processing.
Referring to Fig. 9, be example with four delay buffer storages, the multiple mode of operation of delay buffer storage group is as can be known from this figure:
DELAY?CONTROL＝1；
REGISTERS-DELAY＝ONE-REGISTER?DELAY
DELAY?CONTROL＝2；
REGISTERS-DELAY＝TWO-REGISTER?DELAY
DELAY?CONTROL＝3；
REGISTERS-DELAY＝THREE-REGISTER?DELAY
DELAY?CONTROL＝4；
REGISTERS-DELAY＝FOUR-REGISTER?DELAY
In a word, pipeline system-pulsed of the present invention-single instruction multiple data ARRAY PROCESSING structure and method thereof, it is for data operation, access, transmission, I/O, can both carry out simultaneously with the control of each control signal, more saved its operation time, and also can save spent time and the connecting line of data input simultaneously, have good economic benefits.
Claims (12)
1, a kind of pipeline system-pulsed-single instruction multiple data ARRAY PROCESSING structure, it is characterized in that: it includes: a controller; The array agent structure that several pipeline system elements constitute; Be connected with the pulsed method by several buffers, and be located at the input buffer array of pipeline system access devices agent structure input end; Be connected in series mutually in the heartbeat mode by several buffers, and distinguish configure multiplexer, and be located at the output state array of pipeline system access devices agent structure output terminal in the transmission ends of each buffer; Buffer in above-mentioned each cache array, multiplexer and pipeline system element all are connected with above-mentioned controller and controlled by it.
2, a kind of pipeline system-pulsed-single instruction multiple data ARRAY PROCESSING structure, it is characterized in that: it includes: a controller; The array agent structure that several pipeline system elements constitute; Many group delay buffer storage arrays, its delay buffer storage group is made up of one or more delay buffer storage, and be connected in series each delay buffer storage group in the heartbeat mode, and transmission ends difference configure multiplexer in each delay buffer storage group, these delay buffer storage group patterns are separately positioned on the input end and the output terminal of pipeline system element body structure; One group of broadcast type transmission line is connected the input end of pipeline system element body structure, to accept the feedback output and the extraneous input data of pipeline system element body structure; Delay buffer storage group, multiplexer and pipeline system element in above-mentioned each delay buffer storage group pattern all is connected with above-mentioned controller and controlled by it.
3, pipeline system-pulsed as claimed in claim 1-single instruction multiple data ARRAY PROCESSING structure, it is characterized in that: wherein the pipeline system access devices includes a memory element, its input end is connected with buffer, Input Address generator, input writing controller, output terminal then is connected with OPADD generator, output Read Controller, and links to each other with extraneous pulsed structural transmission line by the ternary controller of buffer; The I/O address generator, its input end links to each other with controller, and output terminal then joins with the I/O end of above-mentioned storer respectively; Read Controller is write and is exported in input, and its input end links to each other with controller, and output terminal then links to each other with the I/O end of above-mentioned storer respectively; Several buffers are separately positioned between storer and extraneous data line join, and ternary controller, place between the buffer and extraneous data line that the storer output terminal connected, and link to each other with the output Read Controller.
4, pipeline system-pulsed as claimed in claim 1-single instruction multiple data ARRAY PROCESSING structure, it is characterized in that: the wherein input end and the output terminal of the main body array of pipeline system access devices, and between input and the output state array, be connected with and switch circuit elements, and this switches circuit elements with controller and is connected.
5, pipeline system-pulsed as claimed in claim 2-single instrction data array Processing Structure is characterized in that: the main body array that is made of several pipeline system elements wherein is the array that is become with the treatment element serial connection.
6, pipeline system-pulsed as claimed in claim 2-single instruction multiple data ARRAY PROCESSING structure is characterized in that: the main body array that is made of several pipeline system elements wherein forms with pipeline system central processing unit serial connection.
7, pipeline system-pulsed as claimed in claim 2-single instruction multiple data ARRAY PROCESSING structure, it is characterized in that: the main body array structure of pipeline system element wherein, many groups delay buffer storage group pattern that its output terminal connects, function with transmitted in both directions and ring shift is so also can be used as the input end of above-mentioned pipeline system element arrays.
8, pipeline system-pulsed as claimed in claim 2-single instruction multiple data processing array technique, it is characterized in that: the main body array structure of pipeline system element wherein, many groups delay buffer storage array that its output terminal connects is provided with feedback assembly, can be used as the input end of pipeline system element arrays.
9, a kind of pipeline system-pulsed-single instruction multiple data array processing method, it is characterized in that: this method includes the following step: send data to first input displacement delay buffer storage group pattern from data set with pulsed; Data are sent to second input displacement delay buffer storage group pattern from data set with pulsed; Data are sent to above-mentioned first displacement delay buffer storage group pattern and pipeline system element group abreast from above-mentioned second input displacement delay buffer storage group pattern; By an input broadcast type circuit, data are transferred to above-mentioned pipeline system element group from above-mentioned data set; By multiplexer and above-mentioned input broadcast type circuit, data are sent to the input end of pipeline system element group from the wired-OR gate output terminal; Data are imported parallel second input end that is sent to above-mentioned pipeline system element group of displacement delay buffer storage group pattern from above-mentioned first; Data are sent to first input end of above-mentioned pipeline system element group from above-mentioned input broadcast type circuit; Under programmable operator scheme, make the inner computing function of carrying out of above-mentioned pipeline system element group; By multiplexer, with the parallel output displacement delay buffer storage array that is sent to of the output terminal of result of calculation in above-mentioned pipeline system element group; Result of calculation is sent to pipeline system element group or data set from above-mentioned output with being shifted delay buffer storage array pulsed; Result of calculation is sent to said apparatus from the wired-OR gate output terminal; And under the control of controller, above-mentioned input displacement delay buffer storage group pattern, input broadcast type circuit, pipeline system element group, output displacement delay buffer storage group pattern, wired-OR gate circuit of output terminal and data set are operated concurrently, to carry out the transmission and the calculation process of data.
10, pipeline system-pulsed as claimed in claim 1-single instruction multiple data ARRAY PROCESSING structure is characterized in that: wherein one-piece construction is to adopt multidimensional structure.
11, pipeline system-pulsed as claimed in claim 2-single instruction multiple data ARRAY PROCESSING structure is characterized in that: wherein one-piece construction is to adopt multidimensional structure.
12, pipeline system-pulsed as claimed in claim 2-single instruction multiple data array processing method is characterized in that: the control signal of its middle controller can be to mix broadcast type control method and pulsed control method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB951079190A CN1154931C (en) | 1995-08-04 | 1995-08-04 | Pipe-lining and impulsing single command multiple data matrix treating structure and method therefor |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB951079190A CN1154931C (en) | 1995-08-04 | 1995-08-04 | Pipe-lining and impulsing single command multiple data matrix treating structure and method therefor |
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| CN1142636A CN1142636A (en) | 1997-02-12 |
| CN1154931C true CN1154931C (en) | 2004-06-23 |
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| DE102004038213A1 (en) * | 2004-08-05 | 2006-03-16 | Robert Bosch Gmbh | Method and device for accessing data of a message memory of a communication module |
| EP2030166A1 (en) * | 2006-05-24 | 2009-03-04 | Nxp B.V. | Integrated circuit arrangement for carrying out block and line based processing of image data |
| US20120297256A1 (en) * | 2011-05-20 | 2012-11-22 | Qualcomm Incorporated | Large Ram Cache |
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