CN115469816B - Method, device, equipment and storage medium for switching reading and writing of memory - Google Patents

Method, device, equipment and storage medium for switching reading and writing of memory Download PDF

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CN115469816B
CN115469816B CN202211359720.8A CN202211359720A CN115469816B CN 115469816 B CN115469816 B CN 115469816B CN 202211359720 A CN202211359720 A CN 202211359720A CN 115469816 B CN115469816 B CN 115469816B
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command
read
command buffer
write
message column
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CN115469816A (en
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请求不公布姓名
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Moore Threads Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0611—Improving I/O performance in relation to response time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Theoretical Computer Science (AREA)
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  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

The application provides a read-write switching method, a device, equipment and a storage medium of a memory, wherein the method comprises the following steps: and if at least one overtime maximum read delay sensitive command exists in the first command message column, executing each overtime maximum read delay sensitive command until the overtime maximum read delay sensitive command is empty. By adopting the technical scheme, the problem of long time consumption of a memory read-write conversion mode can be solved, so that the bandwidth occupancy rate is improved, and the command delay is reduced.

Description

Method, device, equipment and storage medium for switching reading and writing of memory
Technical Field
The present disclosure relates to the field of memory technologies, and in particular, to a method, an apparatus, a device, and a storage medium for switching between reading and writing of a memory.
Background
The DDR SDRAM (Double Data Rate SDRAM, double rate synchronous dynamic random access memory) needs to take extra conversion time from reading to writing or from writing to reading, and further occupies the DDR bandwidth, and meanwhile, the CPU or GPU and other systems have different demands on read-write delay.
However, the current DDR read-write conversion method consumes a long time, which results in a large bandwidth loss.
Therefore, there is a need for a read-write switching method of a memory, which can solve the above-mentioned problems.
Disclosure of Invention
The application provides a read-write switching method, device and equipment of a memory and a storage medium, which can solve the problem of long time consumption of a read-write conversion mode of the memory, and further improve the occupancy rate of bandwidth.
In a first aspect, the present application provides a method for switching between reading and writing of a memory, which is applied to a scheduler, and includes:
detecting a first command message column in a read command buffer;
and if at least one overtime maximum read delay sensitive command exists in the first command message column, executing each overtime maximum read delay sensitive command until the overtime maximum read delay sensitive command is empty.
In an alternative example, the method further comprises:
detecting a second command message column in the write command buffer;
determining whether to perform a switch from the read command buffer to the write command buffer based on a number of write command messages in the second command message column; wherein the second command message column characterizes a plurality of write command messages to be written.
In an alternative example, determining whether to perform the operation of switching from the read command buffer to the write command buffer according to the number of write command messages in the second command message column includes:
if the number of the write command messages in the second command message column exceeds a first threshold value and the first command message column does not include a timeout maximum read delay sensitive command, executing an operation of switching from the read command buffer to the write command buffer;
if the number of write command messages in the second command message column does not exceed the first threshold, then no switching operation to the read command buffer is required.
In an alternative example, if the number of the write command messages in the second command message column does not exceed the first threshold, after performing the switching operation on the read command buffer, the method further includes:
if the first command message column is empty, the second command message column is not empty, and the condition that the read command buffer is switched to the write command buffer is met, executing the operation of switching from the read command buffer to the write command buffer;
If the first command message column is not empty, the second command message column is empty, or the condition for switching the read command buffer to the write command buffer is not satisfied, the switching operation of the read command buffer is not required to be executed.
In an alternative example, the condition for the read command buffer to switch to the write command buffer includes: the dwell time in the read command buffer exceeds a first preset time.
In an alternative example, the method further comprises:
executing a switch from the read command buffer to the write command buffer if an alarm message sent by the write command buffer is received and the first command message queue does not include a timeout maximum read latency sensitive command; wherein the alarm message is used for indicating to execute the operation of switching from the read command buffer to the write command buffer.
In an alternative example, the method further comprises:
executing the write command messages in the write command buffer until the number of write command messages is below a second threshold; wherein the first threshold is greater than the second threshold.
In an alternative example, after performing the operation of switching from the read command buffer to the write command buffer, the method further includes:
And if the second command message column is empty and the condition that the write command buffer is switched to the read command buffer is met, executing the operation of switching from the write command buffer to the read command buffer.
In an alternative example, if the read command buffer is not empty, the scheduler stays in the write command buffer for more than a third preset time, and switches to the read command buffer.
In a second aspect, the present application provides a read-write switching device of a memory, applied to a scheduler, where the device includes:
a first detecting unit configured to detect a first command message column in the read command buffer;
and the first execution unit is used for executing each overtime maximum read delay sensitive command until the overtime maximum read delay sensitive command is empty if at least one overtime maximum read delay sensitive command exists in the first command message column.
In an alternative example, the apparatus further comprises:
a second detecting unit configured to detect a second command message column in the write command buffer;
a second execution unit configured to determine whether to execute an operation of switching from the read command buffer to the write command buffer according to the number of write command messages in the second command message column; wherein the second command message column characterizes a plurality of write command messages to be written.
In an alternative example, the second execution unit includes:
a first judging module, configured to execute an operation of switching from the read command buffer to the write command buffer if the number of the write command messages in the second command message column exceeds a first threshold and the first command message column does not include a timeout maximum read delay sensitive command;
and the second judging module is used for not executing switching operation on the read command buffer if the number of the write command messages in the second command message column does not exceed the first threshold value.
In an alternative example, after the second determining module, the method further includes:
a third judging module, configured to execute an operation of switching from the read command buffer to the write command buffer if the first command message column is empty, the second command message column is not empty, and a condition of switching from the read command buffer to the write command buffer is satisfied;
and a fourth judging module, configured to, if the first command message column is not empty, the second command message column is empty, or a condition that the read command buffer is switched to the write command buffer is not satisfied, not need to perform a switching operation on the read command buffer.
In an alternative example, the condition for the read command buffer to switch to the write command buffer includes: the dwell time in the read command buffer exceeds a first preset time.
In an alternative example, the apparatus further comprises:
the sending module is used for executing the operation of switching from the read command buffer to the write command buffer under the condition that the alarm message sent by the write command buffer is received and the first command message queue does not comprise a overtime maximum read delay sensitive command; wherein the alarm message is used for indicating to execute the operation of switching from the read command buffer to the write command buffer.
In an alternative example, the apparatus further comprises:
an execution module configured to execute the write command messages in the write command buffer until a number of the write command messages is below a second threshold; wherein the first threshold is greater than the second threshold.
In an alternative example, the apparatus further comprises:
and the third execution unit is used for executing the operation of switching from the write command buffer to the read command buffer if the second command message column is empty and the condition of switching from the write command buffer to the read command buffer is met.
In an alternative example, the apparatus further comprises:
and the fourth execution unit is used for switching to the read command buffer if the time that the scheduler stays in the write command buffer exceeds a third preset time if the read command buffer is not empty.
In a third aspect, the present application provides an electronic device, comprising: a processor, and a memory communicatively coupled to the processor;
the memory stores computer-executable instructions;
the processor executes computer-executable instructions stored in the memory to implement the method as described in the first aspect.
In a fourth aspect, the present application provides a computer-readable storage medium having stored therein computer-executable instructions for performing the method according to the first aspect when executed by a processor.
In a fifth aspect, the present application provides a computer program product comprising a computer program which, when executed by a processor, implements the method according to the first aspect.
According to the read-write switching method, device and equipment for the memory and the storage medium, if at least one overtime maximum read delay sensitive command exists in a first command message column in a read command buffer through detection, executing each overtime maximum read delay sensitive command until the overtime maximum read delay sensitive command is empty. By adopting the technical scheme, the problem of long time consumption of a memory read-write conversion mode can be solved, so that the bandwidth occupancy rate is improved, and the command delay is reduced.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
Fig. 1 is a schematic diagram of a frame of a read-write switching method of a memory according to a first embodiment of the present application;
fig. 2 is a flow chart of a read-write switching method of a memory according to a second embodiment of the present application;
fig. 3 is a flow chart of a read-write switching method of a memory according to a third embodiment of the present application;
FIG. 4 is a schematic diagram of a read command buffer and a write command buffer according to a third embodiment of the present application;
fig. 5 is a flow chart of a read-write switching method of a memory according to a fourth embodiment of the present application;
fig. 6 is a schematic diagram of a read-write switching device of a memory according to a fifth embodiment of the present application;
fig. 7 is a schematic diagram of a read-write switching device of a memory according to a sixth embodiment of the present application;
fig. 8 is a block diagram of an electronic device, according to an example embodiment.
Specific embodiments thereof have been shown by way of example in the drawings and will herein be described in more detail. These drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.
The read-write switching method of the memory aims at solving the technical problems in the prior art.
The following describes the technical solutions of the present application and how the technical solutions of the present application solve the above technical problems in detail with specific embodiments. The following embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a frame of a read-write switching method of a memory according to an embodiment of the present application, in which a plurality of host controllers issue a plurality of read command messages and a plurality of write command messages to a scheduler, and the scheduler issues the read command messages and the write command messages to a DDR SDRAM (Double Data Rate SDRAM, double rate synchronous dynamic random access memory). The scheduler includes two memory structures, RCB (Read command Buffer ) and WCB (Write command Buffer, write command buffer), respectively.
Fig. 2 is a flow chart of a method for switching between reading and writing of a memory according to a second embodiment of the present application, where the method is applied to a scheduler, and the second embodiment includes the following steps:
s201, detecting a first command message column in a read command buffer.
In one example, the first command message column includes a plurality of read command messages to be read and at least one timeout maximum read latency sensitive command, further, the read command messages include a maximum latency sensitive command and a general read command message.
The maximum read latency sensitive command is generated after the maximum latency sensitive command has reached the upper limit of the time that must be processed. Specifically, a timer is stored in each maximum delay sensitive command, the timer can time the maximum delay sensitive command, and when the maximum delay sensitive command exceeds a preset time, the maximum delay sensitive command is changed into a overtime maximum read delay sensitive command. The preset time can be set according to the requirement, and the preset time can be smaller than the delay time which can be accepted by the command actually.
The maximum read delay sensitive command is the highest priority, and when the maximum read delay sensitive command exists, the maximum read delay sensitive command is necessarily switched into the read command buffer, and the maximum read delay sensitive command in the read command buffer is processed, so that the maximum read delay sensitive command delay is ensured to be controllable.
S202, if at least one overtime maximum read delay sensitive command exists in the first command message column, executing each overtime maximum read delay sensitive command until the overtime maximum read delay sensitive command is empty.
If the first command message column is not empty, it is indicated that the first command message column includes a plurality of read command messages or further includes a timeout maximum read delay sensitive command.
In this embodiment, if at least one overtime maximum read delay sensitive command exists in the first command message column, each overtime maximum read delay sensitive command is preferentially executed until all overtime maximum read delay sensitive commands are empty.
According to the read-write switching method of the memory, through detecting the first command message column in the read command buffer, if the first command message column has the overtime maximum read delay sensitive command, the overtime maximum read delay sensitive command is preferentially processed, and all overtime maximum read delay sensitive commands are processed. By adopting the technical scheme, all the maximum read delay sensitive commands which need to be processed can be processed in priority, so that the first priority of the read command buffer is realized.
Fig. 3 is a flow chart of a method for switching between reading and writing of a memory according to a third embodiment of the present application, where the method is applied to a scheduler, and the third embodiment includes the following steps:
s301, detecting a first command message column in a read command buffer.
For example, this step may refer to step S201, and will not be described in detail.
And S302, if at least one overtime maximum read delay sensitive command exists in the first command message column, executing each overtime maximum read delay sensitive command until the overtime maximum read delay sensitive command is empty.
For example, this step may refer to step S202 described above, and will not be described in detail.
S303, detecting a second command message column in the write command buffer.
In one example, the write command buffer has a second command message column stored therein. In particular, the schematic structure of the read command buffer and the schematic structure of the write command buffer can be seen in fig. 4, and as can be seen from fig. 4, the read command buffer includes a plurality of read command messages and a timeout maximum read delay sensitive command. The write command buffer includes a plurality of write command messages.
S304, determining whether to execute the operation of switching from the read command buffer to the write command buffer according to the number of the write command messages in the second command message column; wherein the second command message column characterizes a plurality of write command messages to be written.
In this embodiment, the number of write command messages in the second command message column is obtained, and if the number meets the preset requirement, the read command buffer is switched to the write command buffer, and the read command message is processed to the write command message.
According to the read-write switching method of the memory, through detecting the first command message column in the read command buffer, if the first command message column has the overtime maximum read delay sensitive command, the overtime maximum read delay sensitive command is preferentially processed, after all the overtime maximum read delay sensitive commands are processed, the second command message column in the write command buffer is detected, according to the number of write command messages in the second command message column, the read command buffer is switched to the write command buffer, and the write command messages in the write command buffer are executed. By adopting the technical scheme, the read delay can be reduced as much as possible on the premise that the write command message is not blocked, and the read command message which is very sensitive to the delay can be ensured to be delayed and controlled to the greatest extent.
Fig. 5 is a flow chart of a method for switching between reading and writing of a memory according to a fourth embodiment of the present application, where the method is applied to a scheduler, and the fourth embodiment includes the following steps:
S501, detecting a first command message column in a read command buffer.
For example, this step may refer to step S201, and will not be described in detail.
S502, if at least one overtime maximum read delay sensitive command exists in the first command message column, executing each overtime maximum read delay sensitive command until the overtime maximum read delay sensitive command is empty.
For example, this step may refer to step S202 described above, and will not be described in detail.
S503, detecting a second command message column in the write command buffer.
For example, this step may refer to step S303, and will not be described in detail.
S504, if the number of the write command messages in the second command message column exceeds the first threshold value and the first command message column does not include the overtime maximum read delay sensitive command, executing the operation of switching from the read command buffer to the write command buffer.
In this embodiment, the first threshold is an upper limit value of the write command message set in the write command buffer, and when the upper limit value exceeds the first threshold, it indicates that the number of write command messages in the second command message column is too large, and the scheduler is required to process the write command message in the write command buffer, so that the write command buffer needs to be switched from the read command buffer to the write command buffer. In this embodiment, the exceeding means greater than or equal to.
In an alternative example, the method further comprises:
executing a switch from the read command buffer to the write command buffer if an alarm message sent by the write command buffer is received and the first command message queue does not include a timeout maximum read latency sensitive command; wherein the alarm message is used for indicating to execute the operation of switching from the read command buffer to the write command buffer.
In this embodiment, when the number of write command messages in the write command buffer exceeds the first threshold, an alarm message is sent to prompt the scheduler to process the write command messages in the write command buffer.
In an alternative example, the method further comprises:
executing the write command messages in the write command buffer until the number of write command messages is below a second threshold; wherein the first threshold is greater than the second threshold.
In this embodiment, the second threshold is a lower limit value of the write command message in the second command message column, if the second threshold is lower than the lower limit value, it indicates that there is a certain redundancy in the second command message column for the newly issued write command message, and after the number of the write command messages is lower than the second threshold, the alarm message is released.
S505, if the number of write command messages in the second command message column does not exceed the first threshold, no switching operation on the read command buffer is required.
In this embodiment, if the second command message column is empty, it indicates that no write command message needs to be processed in the write command buffer, and if the number of write command messages in the second command message column does not exceed the first threshold, it indicates that the write command buffer also has a storage space available for write command messages to be issued.
S506, if the first command message column is empty, the second command message column is not empty, and the condition that the read command buffer is switched to the write command buffer is satisfied, the operation of switching from the read command buffer to the write command buffer is executed.
In this embodiment, the first command message column is empty, which indicates that no read command message needs to be processed in the read command buffer, and the second command message column is not empty, which indicates that a write command message needs to be processed in the write command buffer.
S507, if the first command message column is not empty, the second command message column is empty or the condition that the read command buffer is switched to the write command buffer is not satisfied, the switching operation of the read command buffer is not required to be executed.
In this embodiment, there may be several cases where the switching operation to the read command buffer is not required to be performed:
the first case is that the first command message column is not empty;
the second case is that the second command message column is empty;
the third case is that the condition for switching the read command buffer to the write command buffer is not satisfied;
the fourth case is that the first command message column is not empty and the second command message column is empty;
the fifth case is that the first command message column is not empty and does not satisfy the operation of switching the read command buffer to the write command buffer;
the sixth case is that the second command message column is empty and does not satisfy the operation of switching the read command buffer to the write command buffer;
the seventh case is that the first command message column is not empty, the second command message column is empty, and the condition for switching the read command buffer to the write command buffer is not satisfied.
In an alternative example, the condition for the read command buffer to switch to the write command buffer includes: the dwell time in the read command buffer exceeds a first preset time.
In this embodiment, the first preset time is a time when the read command buffer preset by the user is switched to the write command buffer, and the specific first preset time may be represented by the identifier t_r2w_delay. Wherein the value of the first preset time is a non-0 value.
In an alternative example, if the read command buffer is not empty, the scheduler stays in the write command buffer for more than a third preset time, and switches to the read command buffer.
In this embodiment, when the read command buffer is not empty, the controller does not switch to the read command buffer, i.e., the time that the scheduler stays in the write command buffer exceeds the third preset time, and then the controller is forced to switch to the read command buffer.
In this embodiment, a timer is configured in the read command buffer, so that the unprocessed time of the scheduler in the read command buffer can be calculated, and if the residence time of the scheduler in the write command buffer exceeds a third preset time, the scheduler is forced to switch to the read command buffer. Wherein the value of the unprocessed time in the read command buffer is equal to the value of the third preset time.
In an alternative example, after performing the operation of switching from the read command buffer to the write command buffer, further comprising:
If the second command message column is empty and the condition for switching the write command buffer to the read command buffer is satisfied, an operation for switching from the write command buffer to the read command buffer is performed.
In one example, if the second command message column is empty and the condition for switching the write command buffer to the read command buffer is satisfied, it is indicated that the write command message in the write command buffer has not been processed, and therefore, the write command buffer may be switched to the read command buffer at this time. The condition for switching the write command buffer to the read command buffer is that the dwell time of the write command buffer exceeds a second preset time. The second preset time may be represented by the identifier t_w2r_delay. The specific value of the second preset time may be 0.
According to the read-write switching method of the memory, through setting the switching conditions between the read command buffer and the write command buffer, the read command buffer and the write command buffer can be free from the influence of the sequence of input read-write command messages, the read command messages and the write command messages can be adaptively selected and executed, the read-write conversion times are greatly reduced, and the bandwidth utilization rate is improved.
Fig. 6 is a schematic diagram of a read-write switching device of a memory according to a fifth embodiment of the present application, where a device 60 in the fifth embodiment includes:
a first detection unit 601 is configured to detect a first command message column in the read command buffer.
The first execution unit 602 executes each timeout maximum read latency sensitive command if there is at least one timeout maximum read latency sensitive command in the first command message column until the timeout maximum read latency sensitive command is null.
It will be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process of the above-described apparatus may refer to the corresponding process in the foregoing method embodiment, which is not repeated herein.
Fig. 7 is a schematic diagram of a read-write switching device of a memory according to a sixth embodiment of the present application, where the device 70 in the sixth embodiment includes:
a first detecting unit 701 for detecting a first command message column in the read command buffer;
a first execution unit 702, configured to execute each timeout maximum read delay sensitive command if there is at least one timeout maximum read delay sensitive command in the first command message column, until the timeout maximum read delay sensitive command is null.
In an alternative example, the apparatus further comprises:
a second detecting unit 703 for detecting a second command message column in the write command buffer;
a second execution unit 704, configured to determine whether to execute an operation of switching from the read command buffer to the write command buffer according to the number of write command messages in the second command message column; wherein the second command message column characterizes a plurality of write command messages to be written.
In an alternative example, the second execution unit 704 includes:
a first determining module 7041, configured to execute an operation of switching from the read command buffer to the write command buffer if the number of the write command messages in the second command message column exceeds a first threshold and the first command message column does not include a timeout maximum read delay sensitive command;
the second determining module 7042 is configured to, if the number of the write command messages in the second command message column does not exceed the first threshold, not need to perform a switching operation on the read command buffer.
In an alternative example, after the second determining module 7042, further includes:
a third determining module 7043, configured to execute an operation of switching from the read command buffer to the write command buffer if the first command message column is empty, the second command message column is not empty, and a condition of switching from the read command buffer to the write command buffer is satisfied;
The fourth determining module 7044 is configured to, if the first command message column is not empty, the second command message column is empty, or the condition for switching the read command buffer to the write command buffer is not satisfied, not need to perform a switching operation for the read command buffer.
In an alternative example, the condition for the read command buffer to switch to the write command buffer includes: the dwell time in the read command buffer exceeds a first preset time.
In an alternative example, the apparatus further comprises:
an issue module 7045, configured to perform an operation of switching from the read command buffer to the write command buffer when an alarm message issued by the write command buffer is received and the first command message queue does not include a timeout maximum read delay sensitive command; wherein the alarm message is used for indicating to execute the operation of switching from the read command buffer to the write command buffer.
In an alternative example, the apparatus further comprises:
an execution module 7046 for executing the write command messages in the write command buffer until the number of write command messages is below a second threshold; wherein the first threshold is greater than the second threshold.
In an alternative example, the apparatus further comprises:
and a third execution unit 705, configured to execute an operation of switching from the write command buffer to the read command buffer if the second command message column is empty and the condition of switching from the write command buffer to the read command buffer is satisfied.
In an alternative example, the apparatus further comprises:
the fourth execution unit 706 is configured to switch to the read command buffer if the read command buffer is not empty and the time that the scheduler stays in the write command buffer exceeds a third preset time.
It will be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process of the above-described apparatus may refer to the corresponding process in the foregoing method embodiment, which is not repeated herein.
Fig. 8 is a block diagram of an electronic device, which may be a mobile phone, computer, digital broadcast terminal, messaging device, game console, tablet device, medical device, exercise device, personal digital assistant, or the like, in accordance with an exemplary embodiment.
The apparatus 800 may include one or more of the following components: a processing component 802, a memory 804, a power component 806, a multimedia component 808, an audio component 810, an input/output (I/O) interface 812, a sensor component 814, and a communication component 816.
The processing component 802 generally controls overall operation of the apparatus 800, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing component 802 may include one or more processors 820 to execute instructions to perform all or part of the steps of the methods described above. Further, the processing component 802 can include one or more modules that facilitate interactions between the processing component 802 and other components. For example, the processing component 802 can include a multimedia module to facilitate interaction between the multimedia component 808 and the processing component 802.
The memory 804 is configured to store various types of data to support operations at the apparatus 800. Examples of such data include instructions for any application or method operating on the device 800, contact data, phonebook data, messages, pictures, videos, and the like. The memory 804 may be implemented by any type or combination of volatile or nonvolatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disk.
The power supply component 806 provides power to the various components of the device 800. The power components 806 may include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power for the device 800.
The multimedia component 808 includes a screen between the device 800 and the user that provides an output interface. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensor may sense not only the boundary of a touch or sliding action, but also the duration and pressure associated with the touch or sliding operation. In some embodiments, the multimedia component 808 includes a front camera and/or a rear camera. The front camera and/or the rear camera may receive external multimedia data when the apparatus 800 is in an operational mode, such as a photographing mode or a video mode. Each front camera and rear camera may be a fixed optical lens system or have focal length and optical zoom capabilities.
The audio component 810 is configured to output and/or input audio signals. For example, the audio component 810 includes a Microphone (MIC) configured to receive external audio signals when the device 800 is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may be further stored in the memory 804 or transmitted via the communication component 816. In some embodiments, audio component 810 further includes a speaker for outputting audio signals.
The I/O interface 812 provides an interface between the processing component 802 and peripheral interface modules, which may be a keyboard, click wheel, buttons, etc. These buttons may include, but are not limited to: homepage button, volume button, start button, and lock button.
The sensor assembly 814 includes one or more sensors for providing status assessment of various aspects of the apparatus 800. For example, the sensor assembly 814 may detect an on/off state of the device 800, a relative positioning of the components, such as a display and keypad of the device 800, the sensor assembly 814 may also detect a change in position of the device 800 or a component of the device 800, the presence or absence of user contact with the device 800, an orientation or acceleration/deceleration of the device 800, and a change in temperature of the device 800. The sensor assembly 814 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 814 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 may also include an acceleration sensor, a gyroscopic sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.
The communication component 816 is configured to facilitate communication between the apparatus 800 and other devices, either in a wired or wireless manner. The device 800 may access a wireless network based on a communication standard, such as WiFi,2G or 3G, or a combination thereof. In one exemplary embodiment, the communication component 816 receives broadcast signals or broadcast related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, the communication component 816 further includes a Near Field Communication (NFC) module to facilitate short range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, ultra Wideband (UWB) technology, bluetooth (BT) technology, and other technologies.
In an exemplary embodiment, the apparatus 800 may be implemented by one or more Application Specific Integrated Circuits (ASICs), digital Signal Processors (DSPs), digital Signal Processing Devices (DSPDs), programmable Logic Devices (PLDs), field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic elements for executing the methods described above.
In an exemplary embodiment, a non-transitory computer readable storage medium is also provided, such as memory 804 including instructions executable by processor 820 of apparatus 800 to perform the above-described method. For example, the non-transitory computer readable storage medium may be ROM, random Access Memory (RAM), CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.
A non-transitory computer readable storage medium, which when executed by a processor of an electronic device, causes the electronic device to perform a read-write switching method of a memory of the electronic device.
The application also discloses a computer program product comprising a computer program which, when executed by a processor, implements a method as described in the present embodiment.
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.
Program code for carrying out methods of the present application may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or electronic device.
In the context of this application, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data electronic device), or that includes a middleware component (e.g., an application electronic device), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), and the internet.
The computer system may include a client and an electronic device. The client and the electronic device are generally remote from each other and typically interact through a communication network. The relationship of client and electronic devices arises by virtue of computer programs running on the respective computers and having a client-electronic device relationship to each other. The electronic equipment can be cloud electronic equipment, also called cloud computing electronic equipment or cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service (Virtual Private Server or VPS for short) are overcome. The electronic device may also be an electronic device of a distributed system or an electronic device that incorporates a blockchain. It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present application may be performed in parallel, sequentially, or in a different order, provided that the desired results of the technical solutions disclosed in the present application can be achieved, and are not limited herein.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It is to be understood that the present application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (9)

1. A method for switching between reading and writing of a memory, the method being applied to a scheduler, the method comprising:
detecting a first command message column in a read command buffer;
if at least one overtime maximum read delay sensitive command exists in the first command message column, executing each overtime maximum read delay sensitive command until the overtime maximum read delay sensitive command is empty;
detecting a second command message column in the write command buffer;
if the number of the write command messages in the second command message column does not exceed the first threshold, the switching operation of the read command buffer is not required to be executed; wherein the second command message column characterizes a plurality of write command messages to be written;
if the first command message column is not empty, the second command message column is empty or the residence time of the read command buffer exceeds a first preset time, the switching operation of the read command buffer is not required to be executed;
If the read command buffer is not empty, the scheduler stays in the write command buffer for more than a third preset time, and then switches to the read command buffer.
2. The method according to claim 1, wherein the method further comprises:
and if the number of the write command messages in the second command message column exceeds a first threshold value and the first command message column does not comprise a overtime maximum read delay sensitive command, executing the operation of switching from the read command buffer to the write command buffer.
3. The method of claim 1, wherein if the number of write command messages in the second command message column does not exceed the first threshold, then no switching operation to the read command buffer is required, the method further comprising:
and if the first command message column is empty, the second command message column is not empty and the residence time of the read command buffer exceeds a first preset time, executing the operation of switching from the read command buffer to the write command buffer.
4. The method according to claim 1, wherein the method further comprises:
Executing a switch from the read command buffer to the write command buffer if an alarm message sent by the write command buffer is received and the first command message column does not include a timeout maximum read latency sensitive command; wherein the alarm message is used for indicating to execute the operation of switching from the read command buffer to the write command buffer.
5. The method according to claim 2, wherein the method further comprises:
executing the write command messages in the write command buffer until the number of write command messages is below a second threshold; wherein the first threshold is greater than the second threshold.
6. A method according to any of claims 1-3, further comprising, after performing the operation of switching from the read command buffer to the write command buffer:
and if the second command message column is empty and the condition that the write command buffer is switched to the read command buffer is met, executing the operation of switching from the write command buffer to the read command buffer.
7. A read-write switching apparatus for a memory, the apparatus being applied to a scheduler, the apparatus comprising:
A first detecting unit configured to detect a first command message column in the read command buffer;
the first execution unit is used for executing each overtime maximum read delay sensitive command until the overtime maximum read delay sensitive command is empty if at least one overtime maximum read delay sensitive command exists in the first command message column;
a second detecting unit configured to detect a second command message column in the write command buffer;
a second execution unit configured to determine whether to execute an operation of switching from the read command buffer to the write command buffer according to the number of write command messages in the second command message column; wherein the second command message column characterizes a plurality of write command messages to be written;
the second execution unit includes:
a second judging module, configured to, if the number of the write command messages in the second command message column does not exceed a first threshold, not need to perform a switching operation on the read command buffer;
a fourth judging module, configured to, if the first command message column is not empty, the second command message column is empty, or the residence time of the read command buffer is not longer than a first preset time, not need to perform a switching operation on the read command buffer;
And the fourth execution unit is used for switching to the read command buffer if the time that the scheduler stays in the write command buffer exceeds a third preset time if the read command buffer is not empty.
8. An electronic device, comprising: a processor, and a memory communicatively coupled to the processor;
the memory stores computer-executable instructions;
the processor executes computer-executable instructions stored in the memory to implement the method of any one of claims 1-6.
9. A computer readable storage medium having stored therein computer executable instructions which when executed by a processor are adapted to carry out the method of any one of claims 1-6.
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