CN115459896A - Control method, control system, medium and chip for multi-channel data transmission - Google Patents
Control method, control system, medium and chip for multi-channel data transmission Download PDFInfo
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- CN115459896A CN115459896A CN202211410596.3A CN202211410596A CN115459896A CN 115459896 A CN115459896 A CN 115459896A CN 202211410596 A CN202211410596 A CN 202211410596A CN 115459896 A CN115459896 A CN 115459896A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/003—Arrangements for allocating sub-channels of the transmission path
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/003—Arrangements for allocating sub-channels of the transmission path
- H04L5/0058—Allocation criteria
Abstract
The disclosure provides a control method of multichannel data transmission, a control system of multichannel data transmission, a chip and a computer readable storage medium, and relates to the technical field of integrated circuits. The method is applied to a chip serving as a data sending end and comprises the following steps: in the s-th channel selection process, the first circuit module determines the pre-selection effective weight set W of the N channels sA Wherein, s is positive integer, N is integer greater than or equal to 2; the pre-selection effective weight set W is processed by a second circuit module sA Carrying out grading parallel computation to obtain the maximum effective weight w smax (ii) a Control channel C smax Transmitting corresponding cache data, wherein the channel C smax With the above maximum effective weight w smax And (7) correspondingly. The technical scheme can meet the requirement of high-frequency time sequence in the D2D process, and can balance loads, thereby reducing the buffer pressure of a chip as a transmitting end.
Description
Technical Field
The present disclosure relates to the field of integrated circuit technologies, and in particular, to a control method for multi-channel data transmission, a control system for multi-channel data transmission, a chip, and a computer-readable storage medium.
Background
The core grain Chiplet framework adopts a novel packaging technology To package small chips manufactured by different functions and different processes together, and the small chips are connected through a D2D (Die To Die, bare chip To bare chip) high-speed serial interface To form a heterogeneous integrated chip. Divide into the chiplet with system level chip according to the function needs, not only can reduce cost, promote the yield, make the design of the complicated big chip of multicore become possible, simultaneously, the modularized design thinking also can improve chip research and development speed, reduces the research and development cost.
The high-speed data transmission of D2D is the key of Chiplet technology landing. To achieve low-latency data transmission between cores, a chipset typically transmits and receives data in the Flit format. When high-speed Flit data streams in the D2D process are transmitted on the same physical channel, a control scheme of multi-channel data transmission is usually required to reduce the buffer pressure of a chip serving as a transmitting end.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to a method for controlling multi-channel data transmission, a system for controlling multi-channel data transmission, a chip and a computer readable storage medium, which can meet the requirement of high frequency timing sequence in a D2D process.
Additional features and advantages of the disclosure will be set forth in the detailed description which follows, or in part will be obvious from the description, or may be learned by practice of the disclosure.
According to an aspect of the present disclosure, there is provided a control method for multi-channel data transmission, applied to a chip as a data transmitting end, the method including: in the s-th channel selection process, the first circuit module determines the pre-selection effective weight set W of the N channels sA Wherein, s is positive integer, N is integer greater than or equal to 2; the pre-selection effective weight set W is processed by a second circuit module sA Carrying out hierarchical parallel computation to obtain the maximum effective weight w smax (ii) a And, control channel C smax Transmitting corresponding cache data, wherein the channel C smax With the above maximum effective weight w smax And (7) correspondingly.
In an exemplary embodiment, based on the above scheme, the determining, by the first circuit module, the pre-selection valid weight set W of the N channels sA The method comprises the following steps: calculating the pre-selection effective weight w of the ith channel through the ith processing unit of the first circuit module sAi Obtaining the pre-selection effective weight set W in a parallel processing mode sA And i is a positive integer not greater than N.
In an exemplary embodiment, based on the foregoing solution, the method further includes: determining a configuration weight set W' of the N channels according to a preset total weight value;
the pre-selection effective weight w of the ith channel is calculated by the ith processing unit of the first circuit module sAi The method comprises the following steps: under the condition that the value of s is greater than 1, the ith processing unit of the first circuit module selects the effective weight w after the selection in the s-1 channel selection process according to the ith channel （s-1）Bi And configuration weight w' i Determining the pre-selection valid weight w sAi 。
In an exemplary embodiment, based on the foregoing scheme, the method further includes: determining a configuration weight set W' of the N channels according to a preset total weight value; the pre-selection effective weight w of the ith channel is calculated by the ith processing unit of the first circuit module sAi The method comprises the following steps: when s is 1, the ith processing unit of the first circuit module assigns w 'to the configuration weight of the ith channel' i Is determined as the pre-selection effective weight w sAi 。
In an exemplary embodiment, the above-mentioned pair of the pre-selection valid weight sets W is based on the above-mentioned scheme sA Carrying out hierarchical parallel computation to obtain the maximum effective weight w smax Afterwards, the method further comprises: calculating the selected effective weight w of the ith channel through the ith processing unit of the third circuit module sBi Obtaining the selected effective weight set W of the N channels in a parallel processing mode sA And i is a positive integer not greater than N.
In an exemplary embodiment, based on the foregoingIn another embodiment, the i-th processing unit of the third circuit module calculates the selected effective weight w of the i-th channel sBi The method comprises the following steps: in the ith channel, the channel C smax In the case of (1), the ith processing unit of the third circuit block is based on the pre-selection valid weight w of the ith channel sAi And determining the selected effective weight w sBi 。
In an exemplary embodiment, based on the foregoing scheme, the selected effective weight w of the ith channel is calculated by the ith processing unit of the third circuit module sBi The method comprises the following steps: in the ith channel except for the channel C smax In the case of other channels, the ith processing unit of the third circuit block applies the pre-selection valid weight w of the ith channel sAi Determined as the above-mentioned selected effective weight w sBi 。
According to another aspect of the present disclosure, there is provided a control system for multi-channel data transmission, configured on a chip as a data transmitting end, the system including: the circuit comprises a first circuit module, a second circuit module and a data selector;
wherein, the first circuit module is configured to determine the pre-selection valid weight set W of the N channels in the s-th channel selection process sA Wherein, s is positive integer, N is integer greater than or equal to 2; the second circuit module is used for selecting the pre-selection valid weight set W sA Carrying out grading parallel computation to obtain the maximum effective weight w smax (ii) a The data selector is used for controlling the maximum effective weight w smax Corresponding channel C smax And transmitting the corresponding cache data.
According to still another aspect of the present disclosure, there is provided a chip including a memory, a processor, and a computer program stored in the memory and executable on the processor, the processor implementing the control method of multi-channel data transmission as provided in the above aspect when executing the computer program.
According to yet another aspect of the present disclosure, there is provided a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements a control method of multi-channel data transmission as in the above embodiments.
The control method for multi-channel data transmission, the control system for multi-channel data transmission, the chip and the computer readable storage medium provided by the embodiment of the disclosure have the following technical effects:
in the solution provided in the embodiment of the present specification, in a channel selection process, a first circuit module determines a pre-selection effective weight corresponding to each channel in the channel selection process, and then a second circuit module determines a maximum effective weight, where a channel corresponding to the maximum effective weight is a channel of data to be transmitted determined in the channel selection process. More specifically, the maximum effective weight is determined by performing hierarchical parallel computation using the second circuit block. It can be seen that the scheme provided by the embodiments of the present specification is implemented based on a circuit, and can meet the requirement of high frequency and time sequence in the D2D process. If the algorithm is adopted for realization, the required algorithm is complex, and the time sequence convergence requirement in the D2D process cannot be ensured.
Meanwhile, by executing the channel selection process for multiple times, the load can be balanced, so that the cache pressure of a chip serving as a sending end is reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure. It should be apparent that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived by those of ordinary skill in the art without inventive effort.
Fig. 1 shows a schematic structural diagram of a chip as a data transmitting end in an exemplary embodiment of the present disclosure.
Fig. 2 is a flowchart illustrating a control method for multi-channel data transmission according to an exemplary embodiment of the disclosure.
Fig. 3 shows a circuit schematic diagram of a data transmission method implementing control of multi-channel data transmission in an exemplary embodiment of the present disclosure.
Fig. 4 is a flowchart illustrating a control method for multi-channel data transmission according to another exemplary embodiment of the disclosure.
Fig. 5 shows a flow chart of a selected effective weight method in an exemplary embodiment of the disclosure.
Fig. 6 shows a schematic structural diagram of a control system for multi-channel data transmission in an exemplary embodiment of the present disclosure.
Fig. 7 shows a schematic structural diagram of a chip in an embodiment of the disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the present disclosure more clear, embodiments of the present disclosure will be described in further detail below with reference to the accompanying drawings.
When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below do not represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and the like. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.
The ucle1.0 version defines a set of physical interfaces (called modules) between Die-to-Die. When high-speed Flit data streams in the D2D process are transmitted on the same physical channel, a control scheme of multi-channel data transmission is usually required to reduce the buffer pressure of a chip serving as a transmitting end.
Embodiments provided in this specification provide a control method for multichannel data transmission, a control system for multichannel data transmission, a chip, and a computer-readable storage medium, which can guarantee timing convergence requirements in a D2D process, and can balance loads, thereby reducing a cache pressure of a chip serving as a sending end.
The following detailed description of the embodiments of the control method for multi-channel data transmission provided by the present disclosure in conjunction with fig. 1 to 5:
in an exemplary embodiment, a FIFO (First Input First Output) buffer is added for the data Input terminal of each logical channel in the chip as the data transmission terminal. Fig. 1 illustrates a schematic structural diagram of a chip serving as a data transmitting end in an exemplary embodiment of the present disclosure. Referring to fig. 1, 8 logical channels (port 0-port 7) are exemplarily shown, and FIFO buffers are respectively set, and then the FIFO of each channel is controlled by the control system for multi-channel data transmission provided in the embodiment of the present specification, specifically, a selected channel is determined by a channel selection process as described below, and the buffer data corresponding to the selected port is controlled to be transmitted.
In an exemplary embodiment, fig. 2 shows a flowchart of a control method for multi-channel data transmission in an exemplary embodiment of the disclosure, which is applied to a chip shown in fig. 1, and is particularly applied to a control system for multi-channel data transmission of a chip shown in fig. 1. Referring to fig. 2, the embodiment shown in this figure comprises: S210-S230.
In S210, in the S-th channel selection process, the pre-selection valid weight set W of the N channels is determined by the first circuit module sA . Wherein N is an integer greater than or equal to 2.
Where s has an initial value of 1 to indicate the order of the channel selection process. In each channel selection process, one channel port is selected, and the data cached by the selected channel port is sent to another DIE through the corresponding physical channel. For example, in the 1 st channel selection process, port5 is selected, and the data cached by port5 is sent to another DIE through the corresponding physical channel. It is understood that two types of effective weights are included in each channel selection process, in the embodiment of the present specification, the subscript "a" represents a pre-selection effective weight, and the subscript "B" represents a post-selection effective weight.
In an embodiment provided in this specification, the control system for multi-channel data transmission implements control of multi-channel data transmission through a circuit. Fig. 3 is a circuit diagram illustrating a data transmission method for implementing control of multi-channel data transmission according to an exemplary embodiment of the present disclosure. It is to be understood that the lane selection process provided in this specification is implemented based on the clock signal "clk" and the lane cache data ready flag.
Illustratively, during the s-th channel selection process, the pre-selection valid weight sets W for the N channels are determined by the first circuit block 310 of the system described above sA . In the case of logical channels as shown in FIG. 1, the set of pre-selection valid weights W sA The effective weights before selection corresponding to the 8 logical channels in the list are respectively expressed as: w is a sA0 、w sA1 、w sA2 、w sA3 、w sA4 、w sA5 、w sA6 And w sA7 。
Referring to the first circuit module 310 in fig. 3, it includes a plurality of processing units. According to the number of the logic channels, a corresponding number of processing units in the first circuit module 310 may be occupied. For example, if 8 logic channels are currently included, 8 processing units in the first circuit module 310 are occupied. Referring to FIG. 3, exemplary, "w sAi_cal "means: in the s-th channel selection process, the ith processing unit in the first circuit module 310 is used to calculate the pre-selection effective weight w of the ith logic channel sAi 。
In the solution provided in the embodiment of the present specification, the first circuit module selects the pre-significant weight set W by a parallel processing method sA And the requirement of high frequency and time sequence in the D2D process can be met.
With continued reference to FIG. 2, at S220, the set of pre-selection valid weights W is matched by the second circuit block sA Carrying out grading parallel computation to obtain the maximum effective weight w smax 。
In an exemplary embodiment, referring to fig. 3, the pre-selection valid weight set W corresponding to N logical channels in the s-th channel selection process is determined by the first circuit module 310 sA The maximum effective weight w is then determined by the second circuit module 320 smax . It should be noted that, in order to reduce the delay, the second circuit module 320 in the embodiment of the present disclosure determines the maximum effective weight w by means of hierarchical parallel computation smax 。
Specifically, if there are 8 logical channels as shown in fig. 1, there are four groups in the first level: [ Port0, port1 ]]、[port2，port3]、[port4，port5]And [ port6, port7 ]]The two logic channels of each group compare the magnitude of the pre-selection effective weight, and may be implemented by using a comparator, for example. Thus, four sets of comparisons are performed in parallel in the first level, e.g., four sets of results output separately: port0, port3, port4, port7. Then in the second level, two groups are divided, which may be, for example: [ Port0, port3 ]]、[port4，port7]Thus, in the second level, two sets of parallel comparisons are performed, for example, two sets of results respectively output: port0 and port7. Then in the third levelComparing the sizes of port0 and port7, and finally determining the maximum effective weight w in the selection process of the s-th channel smax 。
The weight comparison process provided by the embodiment of the present description adopts a hierarchical parallel comparison manner, which can reduce the delay of the combined path and is beneficial to ensuring the timing convergence requirement in the D2D process.
With continued reference to FIG. 2, in S230, control channel C smax Corresponding buffer data is transmitted, wherein, the channel C smax And the maximum effective weight w smax And (7) correspondingly.
For example, the embodiment corresponding to S220 may determine the maximum effective weight w in the S-th channel selection process smax If w is smax =w sA7 That is, the pre-selection effective weight of the 8 th logical channel in the secondary channel selection process is the largest, that is, the 8 th logical channel port7 is the channel C smax . Further, referring to fig. 3, the second circuit block 320 outputs channel C smax 。
Further, a channel C is selected among the buffered data corresponding to all channels by a data selector (multiplexer) 330 smax (port 7) corresponding cache data is output. Wherein, referring to fig. 3, the "chs _ data [8 × 320-1]", indicating all the buffered data for 8 channels, each exemplary channel containing 320 bits.
As can be seen from the embodiment shown in fig. 2, in a channel selection process, a first circuit module determines a pre-selection effective weight corresponding to each channel in the channel selection process, and then a second circuit module determines a maximum effective weight, where the channel corresponding to the maximum effective weight is a channel of data to be transmitted determined in the channel selection process. More specifically, the maximum effective weight is determined by performing hierarchical parallel computation using the second circuit block. It can be seen that the scheme provided by the embodiment of the present specification is implemented based on a circuit, and can meet the high-frequency timing requirement in the D2D process, for example, the timing requirement of 1.6GHz can be met based on the circuit implementation. If the algorithm is adopted for realization, the required algorithm is complex, and the time sequence convergence requirement in the D2D process cannot be ensured. Meanwhile, by executing the channel selection process for multiple times, the load can be balanced, so that the cache pressure of a chip serving as a sending end is reduced.
In an exemplary embodiment, fig. 4 is a schematic flow chart illustrating a control method for multi-channel data transmission in another exemplary embodiment of the present disclosure, which is realized on the basis of the embodiment shown in fig. 2.
Referring to fig. 4, in the embodiment shown in the figure, before performing S210, S200 is also performed: and determining a configuration weight set W' of the N channels according to the preset total weight value.
In the solution provided in the embodiment of the present specification, the total preset weight value of the priority is fixed, and on this premise, the weight of each logical channel may be freely allocated. That is, the sum of the configuration weights in the configuration weight set W' of the N channels is fixed, but the configuration weight corresponding to each logical channel can be flexibly set. In the case that N takes a value of 8, the configuration weight set W' of 8 logical channels may be represented as: [ w' 0 、w’ 1 、w’ 2 、w’ 3 、w’ 4 、w’ 5 、w’ 6 、w’ 7 ]。
In an exemplary embodiment, the configuration weight w' of each channel (e.g., the configuration weight of the ith channel is denoted as "w i ' ") can be set within a specified range. In an implementable embodiment, w i The value range of' is 0 to 15, and the scheme in the range is close to the QoS (Quality of service) design scheme of the AXI4 protocol, so that the universality of the scheme provided by the specification is favorably improved.
It can be understood that, on the premise that the preset total weight value of the priority is fixed, the configuration weights corresponding to the channels may be set according to actual requirements, and the specific value obtaining range of the configuration weights corresponding to the channels is not limited in the embodiments of the present specification. Exemplary, w i The range of' can be set to 0 to 31, and can also be set to 0 to 63, and so on.
Further executing S210: at the s time of the circulationIn the channel selection process, a first circuit module determines pre-selection effective weight set W of N channels sA 。
For example, when s is 1, the configuration weight w 'of the ith channel is determined by the ith processing unit of the first circuit module 310 as shown in fig. 3' i Determining the pre-selection effective weight w of the logic channel sAi . For example, the 3 rd processing unit of the first circuit module 310 directly sets the configuration weight w 'of the ith logic channel during the 1 st (s-valued) secondary channel selection process' 3 Determining the pre-selection effective weight w of the logic channel sA3 。
For example, when the value of s is greater than 1, the ith processing unit of the first circuit module 310 shown in fig. 3 is used to select the selected effective weight w in the s-1 th channel selection process according to the ith channel （s-1）Bi And configuration weight w' i Determining the pre-selection valid weight w sAi . It can be seen that, in the case that the value of s is greater than 1, the current pre-selection configuration weight is related to the last post-selection configuration weight, where details about the post-selection configuration weight will be described in the embodiment shown in fig. 5. In particular, w sAi = w （s-1）Bi + w’ i . For example, the 3 rd processing unit of the first circuit module 310 determines the pre-selection valid weight w in the 5 th (s-valued) channel selection process （s=5）A3 Then, the selected w in the 4 th channel selection process is obtained （s-1=4）B3 Configuration weight w 'is also obtained' 3 And further determine w （s=5）A3 = w （s-1=4）B3 + w’ 3 。
With continuing reference to fig. 4, the specific implementation of S220 and S230 is the same as the corresponding portion in the embodiment of fig. 2, and is not repeated here.
After performing S220, in addition to performing S230, performing S240: calculating the selected effective weight w of the ith channel through the ith processing unit of the third circuit module sBi Obtaining the selected effective weight set W of N channels in a parallel processing mode sB 。
In an exemplary embodiment, referring to FIG. 3, a third circuit modeBlock 340 includes a plurality of processing units. According to the number of the logic channels, a corresponding number of processing units in the third circuit module 340 may be occupied. For example, if 8 logic channels are currently included, 8 processing units in the third circuit module 340 are occupied. Exemplary, "w sBi_cal "means: in the s-th channel selection process, the ith processing unit in the third circuit module 340 is used to calculate the selected effective weight w of the ith logic channel sBi 。
In the solution provided in the embodiment of this specification, the third circuit module selects the effective weight set W by parallel processing sB And the requirement of high-frequency time sequence in the D2D process is also favorably met.
In an exemplary embodiment, fig. 5 shows a flowchart of a selected effective weight method in an exemplary embodiment of the disclosure, which may be used as a specific implementation manner of S240. Referring to fig. 5, the embodiment shown in this figure comprises: S2401-S2403.
In S2401, it is determined whether the ith channel is channel C smax . Wherein, the ith channel is a channel C smax In the case of (3), S2402 is executed; in the ith passage other than passage C smax In the case of (3), S2403 is executed.
In S2402, the ith processing unit of the third circuit block selects the valid weight w according to the ith channel sAi Determining the selected effective weight w of the ith channel according to the total value of the preset weights sBi . And, in S2403, the ith processing unit of the third circuit block assigns the pre-selection effective weight w of the ith channel sAi Determining the selected effective weight w of the ith channel sBi 。
Illustratively, in the ith channel is channel C smax In case of (2), the ith processing unit of the third circuit module 340 selects the valid weight w according to the ith channel sAi Subtracting the total value of the preset weight to obtain the selected effective weight w of the ith channel sBi . For example, at 8 th channel port7 is channel C smax The 8 th processing unit of the third circuit block 340 according to the 8 th channel's pre-selection valid weight w sA8 Subtracting the total value of the preset weight to obtain the ith fluxPost-selection effective weight w of a track sB8。
For channels other than C smax The other channels except for the 8 th channel, for example, the 5 th processing unit of the third circuit module 340 selects the pre-selection valid weight w of the 5 th channel sA5 Determining the selected effective weight w of the 5 th channel sB5 。
In an exemplary embodiment, the selected effective weight set W of the s-th channel selection process is calculated by the third circuit module 340 sB It may then be buffered by buffer 350. Further, the selected effective weight set W in the cache sB W may be calculated by the first circuit block 310 （s+1）A 。
On one hand, the weight calculation and updating method provided by the embodiment of the specification has higher smoothness and meets the requirement of complex load balance. On the other hand, the scheme provided by the embodiment of the specification is realized based on a circuit, and can meet the requirement of high frequency and time sequence in the D2D process. Meanwhile, by executing the channel selection process for multiple times, the load can be balanced, so that the cache pressure of a chip serving as a sending end is reduced.
It is to be noted that the above-mentioned figures are only schematic illustrations of the processes involved in the method according to an exemplary embodiment of the invention, and are not intended to be limiting. It will be readily understood that the processes shown in the above figures are not intended to indicate or limit the chronological order of the processes. In addition, it is also readily understood that these processes may be performed, for example, synchronously or asynchronously in multiple modules.
The following is a system embodiment of the present invention that may be used to implement method embodiments of the present invention. For details that are not disclosed in the embodiments of the apparatus of the present invention, reference is made to method embodiments of the present invention.
Fig. 6 is a schematic structural diagram of a control system for multi-channel data transmission according to an exemplary embodiment of the present invention. Referring to fig. 6, the control system for multi-channel data transmission shown in the figure may be implemented by software, hardware or a combination of both as all or a part of a chip, and may also be integrated in the chip or on a server as a separate module.
The control system 600 for multi-channel data transmission in the exemplary embodiment of the present invention includes: a first circuit block 310, a second circuit block 320, and a data selector 330.
The first circuit module 310 is configured to determine the pre-selection valid weight set W of the N channels in the s-th channel selection process sA Wherein, s is positive integer, N is integer greater than or equal to 2; the second circuit block 320 is configured to apply the pre-selection valid weight set W sA Carrying out hierarchical parallel computation to obtain the maximum effective weight w smax (ii) a The data selector 330 is used for controlling the channel C smax Transmitting corresponding cache data, wherein the channel C smax With the above maximum effective weight w smax And (7) corresponding.
In an exemplary embodiment, based on the foregoing solution, the first circuit module 310 includes: and N processing units. The ith processing unit of the first circuit module is configured to calculate the pre-selection effective weight w of the ith channel sAi Obtaining the pre-selection effective weight set W in a parallel processing mode sA And i is a positive integer not greater than N.
In an exemplary embodiment, based on the foregoing solution, the control system 600 for multi-channel data transmission further includes: the weight determination module 610 is configured. The configuration weight determining module 610 is configured to determine a configuration weight set W' of the N channels according to a preset total weight value;
the ith processing unit of the first circuit module is specifically configured to: when the value of s is greater than 1, the ith processing unit of the first circuit module selects the post-selection effective weight w in the s-1 th channel selection process according to the ith channel （s-1）Bi And configuration weight w' i Determining the pre-selection valid weight w sAi 。
In an exemplary embodiment, based on the foregoing scheme, the control system 600 for multi-channel data transmission further includes: the weight determination module 610 is configured. Wherein the configuration weight determining module 610 is configured to: determining a configuration weight set W' of the N channels according to a preset total weight value;
the ith processing unit of the first circuit module is specifically configured to: when s is equal to 1, the ith processing unit of the first circuit module assigns an arrangement weight w 'to the ith channel' i Is determined as the pre-selection effective weight w sAi 。
In an exemplary embodiment, based on the foregoing scheme, the control system 600 for multi-channel data transmission further includes: a third circuit module 340. Wherein the third circuit module 340 selects the set of pre-selection valid weights W at the second circuit module 320 sA Carrying out grading parallel computation to obtain the maximum effective weight w smax Thereafter, for: calculating the selected effective weight w of the ith channel through the ith processing unit of the third circuit module sBi Obtaining the selected effective weight set W of the N channels in a parallel processing mode sA And i is a positive integer not greater than N.
In an exemplary embodiment, based on the foregoing scheme, the ith processing unit of the third circuit module 340 is configured to: in the ith channel is the above-mentioned channel C smax According to the pre-selection effective weight w of the ith channel sAi And determining the selected effective weight w sBi 。
In an exemplary embodiment, based on the foregoing solution, the ith processing unit of the third circuit module 340 is configured to: in the ith channel except for the channel C smax In the case of other channels than the ith channel, the pre-selection effective weight w of the ith channel is set sAi Determined as the above-mentioned selected effective weight w sBi 。
In an exemplary embodiment, based on the foregoing scheme, the control system 600 for multi-channel data transmission further includes: a buffer 350. Wherein, the buffer 350 obtains the selected effective weight set W of the s-th channel selection process through calculation by the third circuit module 340 sB Then, the selected effective weight set W used for caching the s-th channel selection process sB 。
It should be noted that, when the control system for multi-channel data transmission provided in the foregoing embodiment executes the control method for multi-channel data transmission, only the division of the above functional modules (e.g., the first circuit module, the second circuit module, etc.) is taken as an example, in practical applications, the above function distribution may be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules, so as to complete all or part of the above described functions. In addition, the control system for multi-channel data transmission provided by the above embodiment and the control method for multi-channel data transmission belong to the same concept.
The above-mentioned serial numbers of the embodiments of the present disclosure are merely for description, and do not represent the advantages or disadvantages of the embodiments.
The embodiments of the present disclosure also provide a computer-readable storage medium, on which a computer program is stored, which when executed by a processor implements the steps of the method of any of the preceding embodiments. The computer-readable storage medium may include, but is not limited to, any type of disk including floppy disks, optical disks, DVDs, CD-ROMs, microdrive, and magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, DRAMs, VRAMs, flash memory devices, magnetic or optical cards, nanosystems (including molecular memory ICs), or any type of media or device suitable for storing instructions and/or data.
The embodiment of the present disclosure further provides a chip, which includes a memory, a processor, and a computer program stored in the memory and capable of running on the processor, and when the processor executes the computer program, the steps of any of the above-mentioned embodiments of the method are implemented.
Fig. 7 shows a schematic structural diagram of a chip in an embodiment of the disclosure. Referring to fig. 7, a chip 700 includes: a processor 701 and a memory 702.
In the embodiment of the present disclosure, the processor 701 is a control center of a computer system, and may be a processor of an entity machine or a processor of a virtual machine. The processor 701 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and so on. The processor 701 may be implemented in at least one hardware form of a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), and a PLA (Programmable Logic Array). The processor 701 may also include a main processor and a coprocessor, where the main processor is a processor for Processing data in an awake state, and is also called a Central Processing Unit (CPU); a coprocessor is a low power processor for processing data in a standby state.
In this embodiment of the present disclosure, the processor 701 is specifically configured to:
in the s-th channel selection process, the first circuit module determines the pre-selection effective weight set W of the N channels sA Wherein, s is positive integer, N is integer greater than or equal to 2; the pre-selection effective weight set W is processed by a second circuit module sA Carrying out grading parallel computation to obtain the maximum effective weight w smax (ii) a And, control channel C smax Corresponding buffer data is transmitted, wherein, the channel C is smax With the above maximum effective weight w smax And (7) corresponding.
Further, the determining the pre-selection valid weight set W of the N channels by the first circuit module sA The method comprises the following steps: calculating the pre-selection effective weight w of the ith channel through the ith processing unit of the first circuit module sAi Obtaining the pre-selection effective weight set W in a parallel processing mode sA And i is a positive integer not greater than N.
Further, the processor 701 is further specifically configured to: determining a configuration weight set W' of the N channels according to a preset total weight value;
calculating the pre-selection effective weight w of the ith channel by the ith processing unit of the first circuit module sAi The method comprises the following steps: when the value of s is greater than 1, the ith processing unit of the first circuit module selects the post-selection effective weight w in the s-1 th channel selection process according to the ith channel （s-1）Bi And configuration weight w' i Determining the pre-selection valid weight w sAi
Further, the processor 701 is further specifically configured to: determining a configuration weight set W' of the N channels according to a preset total weight value;
the pre-selection effective weight w of the ith channel is calculated by the ith processing unit of the first circuit module sAi The method comprises the following steps: when s is equal to 1, the ith processing unit of the first circuit module assigns an arrangement weight w 'to the ith channel' i Is determined as the pre-selection effective weight w sAi 。
Further, the processor 701 is further specifically configured to:
for the above-mentioned before-selection valid weight set W sA Carrying out grading parallel computation to obtain the maximum effective weight w smax And then: calculating the selected effective weight w of the ith channel through the ith processing unit of the third circuit module sBi Obtaining the selected effective weight set W of the N channels in a parallel processing mode sA And i is a positive integer not greater than N.
Further, the above-mentioned i processing unit through the third circuit module calculates the selected effective weight w of the i channel sBi The method comprises the following steps: in the ith channel is the above-mentioned channel C smax In the case of (1), the ith processing unit of the third circuit block selects an effective weight w according to the ith channel sAi And determining the selected effective weight w sBi 。
Further, the above-mentioned ith processing unit through the third circuit module calculates the selected effective weight w of the ith channel sBi The method comprises the following steps: in the ith channel except for the channel C smax In the case of other channels, the ith processing unit of the third circuit block applies the pre-selection valid weight w of the ith channel sAi Determined as the above-mentioned selected effective weight w sBi 。
In some embodiments, chip 700 further comprises: a peripheral interface 703 and at least one peripheral. The processor 701, memory 702, and peripheral interface 703 may be connected by buses or signal lines. Various peripheral devices may be connected to peripheral interface 703 via a bus, signal line, or circuit board. Specifically, the peripheral device includes: at least one of a display screen 704, a camera 705, and an audio circuit 706.
The peripheral interface 703 may be used to connect at least one peripheral related to I/O (Input/Output) to the processor 701 and the memory 702. In some embodiments of the present disclosure, the processor 701, the memory 702, and the peripheral interface 703 are integrated on the same chip or circuit board; in some other embodiments of the present disclosure, any one or both of processor 701, memory 702, and peripherals interface 703 may be implemented on separate chips or circuit boards. The embodiments of the present disclosure are not particularly limited in this regard.
The display screen 704 is used to display a UI (User Interface). The UI may include graphics, text, icons, video, and any combination thereof. When the display screen 704 is a touch display screen, the display screen 704 also has the ability to capture touch signals on or over the surface of the display screen 704. The touch signal may be input to the processor 701 as a control signal for processing. At this point, the display screen 704 may also be used to provide virtual buttons and/or a virtual keyboard, also referred to as soft buttons and/or a soft keyboard. In some embodiments of the present disclosure, the display screen 704 may be one, providing the front panel of the chip 700; in other embodiments of the present disclosure, the number of the display screens 704 may be at least two, and the display screens are respectively disposed on different surfaces of the chip 700 or in a folded design; in some embodiments of the present disclosure, the display 704 may be a flexible display, disposed on a curved surface or on a folded surface of the chip 700. Even more, the display screen 704 may be arranged in a non-rectangular irregular pattern, i.e., a shaped screen. The Display screen 704 may be made of LCD (Liquid Crystal Display), OLED (Organic Light-Emitting Diode), and other materials.
The camera 705 is used to capture images or video. Optionally, the camera 705 comprises a front camera and a rear camera. Generally, the front camera is disposed on the front panel of the chip, and the rear camera is disposed on the back of the chip. In some embodiments, the number of the rear cameras is at least two, and each rear camera is any one of a main camera, a depth-of-field camera, a wide-angle camera and a telephoto camera, so that the main camera and the depth-of-field camera are fused to realize a background blurring function, the main camera and the wide-angle camera are fused to realize panoramic shooting and a VR (Virtual Reality) shooting function or other fusion shooting functions. In some embodiments of the present disclosure, the camera 705 may also include a flash. The flash lamp can be a monochrome temperature flash lamp or a bicolor temperature flash lamp. The double-color-temperature flash lamp is a combination of a warm-light flash lamp and a cold-light flash lamp, and can be used for light compensation at different color temperatures.
The audio circuitry 706 may include a microphone and a speaker. The microphone is used for collecting sound waves of a user and the environment, converting the sound waves into electric signals, and inputting the electric signals to the processor 701 for processing. For the purpose of stereo sound collection or noise reduction, a plurality of microphones may be provided at different portions of the chip 700. The microphone may also be an array microphone or an omni-directional pick-up microphone.
The block diagram of the chip architecture shown in the embodiments of the present disclosure does not constitute a limitation on the chip 700, and the chip 700 may include more or less components than those shown, or combine some components, or adopt a different arrangement of components.
In the description of the present disclosure, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The specific meaning of the above terms in the present disclosure can be understood in specific instances by those of ordinary skill in the art. Further, in the description of the present disclosure, "a plurality" means two or more unless otherwise specified. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.
The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Accordingly, equivalents may be resorted to as falling within the scope of the disclosure as claimed.
Claims (10)
1. A control method for multi-channel data transmission is applied to a chip as a data transmitting end, and comprises the following steps:
determining, by a first circuit module, a pre-selection valid weight set W for the N channels in an s-th channel selection process sA Wherein, s is an integer, and N is an integer greater than or equal to 2;
by a second circuit module, the pre-selection valid weight set W sA Carrying out grading parallel computation to obtain the maximum effective weight w smax ；
Control channel C smax Transmitting corresponding cache data, wherein the channel C smax And the maximum effective weight w smax And (7) correspondingly.
2. The method of claim 1, wherein determining, by the first circuit block, the pre-selection valid weight set W for the N channels sA The method comprises the following steps:
calculating the pre-selection effective weight w of the ith channel through the ith processing unit of the first circuit module sAi Obtaining the pre-selection effective weight set W in a parallel processing mode sA And i is a positive integer not greater than N.
3. The method of claim 2, further comprising:
determining a configuration weight set W' of the N channels according to a preset total weight value;
calculating the pre-selection effective weight w of the ith channel through the ith processing unit of the first circuit module sAi The method comprises the following steps:
under the condition that the value of s is greater than 1, the ith processing unit of the first circuit module selects the effective weight w after selection in the s-1 channel selection process according to the ith channel （s-1）Bi And configuration weight w' i Determining the pre-selection valid weight w sAi 。
4. The method of claim 2, further comprising:
determining a configuration weight set W' of the N channels according to a preset total weight value;
calculating the pre-selection effective weight w of the ith channel through the ith processing unit of the first circuit module sAi The method comprises the following steps:
when s is equal to 1, the ith processing unit of the first circuit module assigns an i-th channel configuration weight w' i Is determined as the pre-selection effective weight w sAi 。
5. The method according to any of claims 1 to 4, wherein the pair of pre-selection valid weight sets W sA Carrying out grading parallel computation to obtain the maximum effective weight w smax Thereafter, the method further comprises:
calculating the selected effective weight w of the ith channel through the ith processing unit of the third circuit module sBi Obtaining the selected effective weight set W of the N channels in a parallel processing mode sB And i is a positive integer not greater than N.
6. The method of claim 5, wherein the selected effective weight w of the ith channel is calculated by the ith processing unit of the third circuit block sBi The method comprises the following steps:
in the ith channel is the channel C smax In the case of (1), the ith processing unit of the third circuit block is according to the pre-selection valid weight w of the ith channel sAi And determining the selected effective weight w according to the total value of the preset weights sBi 。
7. The method of claim 5, wherein the computing the selected effective weight w of the ith channel by the ith processing unit of the third circuit block sBi The method comprises the following steps:
in the ith channel being said channel C smax In the case of other channels, the ith processing unit of the third circuit block applies the pre-selection effective weight w of the ith channel sAi Is determined as the selected effective weight w sBi 。
8. A control system for multi-channel data transmission, configured in a chip as a data transmitting end, the system comprising: the circuit comprises a first circuit module, a second circuit module and a data selector;
the first circuit module is used for determining the pre-selection effective weight set W of the N channels in the s-th channel selection process sA Wherein, s is positive integer, N is integer greater than or equal to 2;
the second circuit module is used for selecting the pre-selection effective weight set W sA Carrying out grading parallel computation to obtain the maximum effective weight w smax ；
The data selector is used for controlling the channel C smax Transmitting corresponding cache data, wherein the channel C smax And the maximum effective weight w smax And (7) corresponding.
9. A chip comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the method of controlling a multi-channel data transmission according to any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out a method of controlling a multichannel data transmission according to any one of claims 1 to 7.
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