CN115459618A

CN115459618A - Bridge circuit with serially connected switches and no-load control method of DC/AC conversion circuit

Info

Publication number: CN115459618A
Application number: CN202211146486.0A
Authority: CN
Inventors: 邵帅; 高枝; 崔文韬; 王金帅; 张军明; 吴新科
Original assignee: Zhejiang University ZJU
Current assignee: Zhejiang University ZJU
Priority date: 2022-09-20
Filing date: 2022-09-20
Publication date: 2022-12-09

Abstract

The invention belongs to the technical field of power electronics, and aims to provide a bridge circuit with serially connected switches and a no-load control method of a DC/AC conversion circuit. In the circuit, two ends of each main switch tube are connected with an active clamping circuit in parallel, and the active clamping circuit comprises a clamping capacitor and an auxiliary switch tube. The no-load control method is characterized in that at least half of the auxiliary switching tubes are selectively controlled to be conducted in dead time, and when the sum of voltages of clamping capacitors corresponding to the selected auxiliary switching tubes exceeds an input voltage, the clamping capacitors discharge and feed energy back to an input side. The auxiliary switch tubes are respectively sequenced by adopting upper and lower bridge arms, and the auxiliary switch tube corresponding to a half clamping capacitor with higher clamping capacitor voltage in each bridge arm is selected; or the upper bridge arm and the lower bridge arm are sequenced together, and the auxiliary switch tube corresponding to the higher half of the clamping capacitor in all the voltages is selected to realize the balance of the voltage of the clamping capacitor. The control method of the invention does not affect the normal operation of the main switching tube, and reduces the no-load loss of the system by feeding energy back to the input side.

Description

Bridge circuit with serially connected switches and no-load control method of DC/AC conversion circuit

Technical Field

The invention belongs to the technical field of power electronics, and particularly relates to a bridge circuit with switches connected in series and a no-load control method of a DC/AC conversion circuit.

Background

Due to the limited voltage withstanding capability of a single power switch tube, a plurality of power switch tubes are generally required to be connected in series for use in medium-high voltage applications. To achieve reliable operation of the series devices, it is necessary to ensure voltage equalization between the series-connected power devices. The main causes of voltage imbalance in the series devices include device dynamic, static parameter differences, and external circuit condition differences. To address this problem, existing solutions are mainly classified into three categories: passive snubber circuit, gate drive compensation circuit and active voltage clamp circuit. The active voltage clamping circuit absorbs voltage spikes generated when the switches of the power devices are not synchronous through a circuit formed by connecting a capacitor, a resistor, a semiconductor diode, a semiconductor switch tube or a combination of the capacitor, the resistor, the semiconductor diode and the semiconductor switch tube in parallel at the two ends of each power device, so that the voltage at the two ends of each power device is clamped to the voltage of the capacitor, and the voltage of each power device is balanced through the balance control of the voltage of the capacitor. Compared with a gate driving compensation circuit and an active voltage clamping circuit, the active voltage clamping circuit has the advantages of simple structure, high reliability, small loss and the like.

An auxiliary switch tube is added in the clamping circuit, the auxiliary switch tube is selectively controlled to be conducted for a preset time length in the dead time according to the sequencing result of the voltage of the clamping capacitor, the negative bridge arm current is used for discharging the clamping capacitor, and the balance of the voltage of the clamping capacitor can be realized. The method can realize energy feedback and further reduce the overall loss of the system. However, under the no-load condition, the bridge arm current is zero, and there is no negative bridge arm current to discharge the clamping capacitor all the time, so that the original control method cannot be used for realizing the voltage balance of the clamping capacitor and the voltage balance between the series power devices.

Disclosure of Invention

In order to overcome the defects in the prior art, the invention provides a bridge circuit with switches connected in series and a no-load control method of a DC/AC conversion circuit.

According to an embodiment of the present invention, a no-load control method for a bridge circuit with serially connected switches is provided, the bridge circuit including a first bridge leg and a second bridge leg coupled to a common terminal, the first bridge leg including a plurality of first main switches coupled in series, wherein each of the first main switches is connected in parallel to a first auxiliary module, each of the first auxiliary modules includes a first clamping capacitor and a first auxiliary switch, the second bridge leg includes a plurality of second main switches, wherein each of the second main switches is connected in parallel to a second auxiliary module, each of the second auxiliary modules includes a second clamping capacitor and a second auxiliary switch, the first bridge leg receives a first main switch signal for controlling the plurality of first main switches, the second bridge leg receives a second main switch signal for controlling the plurality of second main switches, wherein in each switch cycle, a first dead time and a second dead time are included between the first main switch signal and the second main switch signal, the bridge circuit includes a first dead time and a second dead time, the bridge circuit includes a first auxiliary switch m and a second auxiliary switch, and the number of m is a natural number: and controlling p first auxiliary switching tubes and q second auxiliary switching tubes to be respectively conducted for a first preset time length and a second preset time length in a first dead time in a switching period, wherein p and q are natural numbers, and p + q is more than or equal to (m + n)/2.

Furthermore, the control method further includes controlling the p first auxiliary switching tubes and the q second auxiliary switching tubes to be respectively conducted for a third preset time and a fourth preset time within a second dead time in the switching period.

Further, the control method further comprises controlling the p first auxiliary switching tubes and the q second auxiliary switching tubes to be turned off in a second dead time in the one switching period.

Furthermore, the control method further includes controlling p first auxiliary switching tubes and q second auxiliary switching tubes to be respectively conducted for a fifth preset time length and a sixth preset time length in a second dead time in another switching period.

Further, the control method further includes controlling the p first auxiliary switching tubes and the q second auxiliary switching tubes to be respectively conducted for a seventh preset time period and an eighth preset time period within a first dead time in the other switching cycle.

Further, the control method further includes sampling voltages across all the first clamping capacitors and voltages across all the second clamping capacitors in one switching period and outputting corresponding voltage sampling signals; uniformly sequencing all the voltage sampling signals according to the voltage from large to small to obtain an integral sequencing result; and selecting the first p first auxiliary switch tubes and the q second auxiliary switch tubes according to the whole sequencing result, wherein the voltage sampling signals corresponding to the p first auxiliary switch tubes and the q second auxiliary switch tubes are all larger than the voltage sampling signals of the rest first auxiliary switch tubes and the rest second auxiliary switch tubes.

Furthermore, the control method further includes sampling voltages across all the first clamping capacitors and outputting corresponding first voltage sampling signals, and sampling voltages across all the second clamping capacitors and outputting corresponding second voltage sampling signals in a switching period; sequencing all the first voltage sampling signals according to the voltage from large to small to obtain a first sequencing result, and sequencing all the second voltage sampling signals according to the voltage from large to small to obtain a second sequencing result; and selecting the first p first auxiliary switch tubes according to the first sequencing result, and selecting the first q second auxiliary switch tubes according to the second sequencing result, wherein the first voltage sampling signals of the p first auxiliary switch tubes are greater than the first voltage sampling signals of the rest first auxiliary switch tubes, and the second voltage sampling signals of the q second auxiliary switch tubes are greater than the second voltage sampling signals of the rest second auxiliary switch tubes.

Further, the control method further includes controlling the remaining first auxiliary switching tubes and the remaining second auxiliary switching tubes to be turned off in the first dead time and the second dead time.

Further, the bridge circuit outputs an output current and an output voltage at the common terminal, when the output current is zero current or less than a certain threshold, the bridge circuit is in a no-load working state, and the no-load control method is adopted when the bridge circuit is in the no-load working state.

Further, the no-load control method is performed in each switching period, or in X consecutive switching periods, Y switching periods are selected and controlled by the no-load control method, where Y is a positive integer less than or equal to X.

According to another embodiment of the present invention, a no-load control method for a DC/AC conversion circuit with switches connected in series is provided, the DC/AC conversion circuit including: a bridge circuit, a filter device and an output load connected in series by switches, where the bridge circuit includes a first bridge arm and a second bridge arm coupled to a common terminal, the first bridge arm includes a plurality of first main switches coupled in series, each of the first main switches is connected in parallel to a first auxiliary module, each of the first auxiliary modules includes a first clamping capacitor and a second auxiliary switch tube, the second bridge arm includes a plurality of second main switches, each of the second main switches is connected in parallel to a second auxiliary module, each of the second auxiliary modules includes a second clamping capacitor and a second auxiliary switch tube, the bridge circuit includes m first auxiliary switch tubes and n second auxiliary switch tubes, m and n are natural numbers, a switching cycle of the DC/AC conversion circuit includes a first time period, a second time period, a first dead time and a second dead time, and the control method includes: in a first time period, the plurality of first main switches are controlled to be turned off, the plurality of second main switches are controlled to be turned on, and all the first auxiliary switch tubes and the second auxiliary switch tubes are turned off; in a first dead time, controlling the plurality of first main switches and the plurality of second main switches to be turned off, controlling p first auxiliary switch tubes to be conducted for a first preset time period, and controlling q second auxiliary switch tubes to be conducted for a second preset time period, wherein p and q are natural numbers, and p + q is greater than or equal to (m + n)/2, controlling the rest of first auxiliary switch tubes and the rest of second auxiliary switch tubes to be turned off, and discharging first clamping capacitors corresponding to the p first auxiliary switch tubes and second clamping capacitors corresponding to the q second auxiliary switch tubes; in a second time period, the plurality of first main switches are controlled to be switched on, the plurality of second main switches are switched off, and the first auxiliary switch tube and the second auxiliary switch tube are both switched off to control the bridge circuit to enter an inversion state; and in a second dead time, controlling the plurality of first main switches and the plurality of second main switches to be turned off, controlling p first auxiliary switch tubes to be conducted for a third preset time, controlling q second auxiliary switch tubes to be conducted for a fourth preset time, controlling the other first auxiliary switch tubes and the other second auxiliary switch tubes to be turned off, and discharging first clamping capacitors corresponding to the p first auxiliary switch tubes and second clamping capacitors corresponding to the q second auxiliary switch tubes.

Further, the control method further includes the steps of utilizing a control circuit to sequence voltages at two ends of all first clamping capacitors and all second clamping capacitors of the first bridge arm and the second bridge arm together to obtain an overall sequencing result, and selecting the first p first auxiliary switch tubes and the q second auxiliary switch tubes according to the overall sequencing result and the voltages from large to small, wherein the voltages at two ends of the first clamping capacitors and the second clamping capacitors corresponding to the p first auxiliary switch tubes and the q second auxiliary switch tubes are larger than the voltages at two ends of the first clamping capacitors and the second clamping capacitors corresponding to the rest first auxiliary switch tubes and the rest second auxiliary switch tubes.

The control method further includes the steps of utilizing a control circuit to sequence voltages at two ends of all first clamping capacitors of a first bridge arm from high to low to obtain a first sequencing result, sequencing voltages at two ends of all second clamping capacitors of a second bridge arm from high to low to obtain a second sequencing result, selecting the first p first auxiliary switch tubes according to the first sequencing result, and selecting the first q second auxiliary switch tubes according to the second sequencing result, wherein voltages at two ends of the first clamping capacitors corresponding to the p first auxiliary switch tubes are larger than voltages at two ends of the first clamping capacitors corresponding to the rest first auxiliary switch tubes, and voltages at two ends of the second clamping capacitors corresponding to the q second auxiliary switch tubes are larger than voltages at two ends of the second clamping capacitors corresponding to the rest second auxiliary switch tubes.

Further, the DC/AC conversion circuit further includes a third bridge arm and a fourth bridge arm, main switch signals of the third bridge arm and the fourth bridge arm and main switch signals of the first bridge arm and the second bridge arm have a phase difference of 180 degrees, and the ordering of the clamping capacitors of the third bridge arm and the fourth bridge arm and the control of the auxiliary switch tubes are independent of the first bridge arm and the second bridge arm.

The DC/AC conversion circuit further comprises a third bridge arm, a fourth bridge arm, a fifth bridge arm and a sixth bridge arm, main switch signals of the third bridge arm, the fourth bridge arm, the fifth bridge arm, the sixth bridge arm and the first bridge arm and main switch signals of the second bridge arm have a phase difference of 120 degrees, and the sequence of clamping capacitors of the third bridge arm, the fourth bridge arm, the fifth bridge arm and the sixth bridge arm and the control of auxiliary switch tubes are independent of the first bridge arm and the second bridge arm.

Compared with the prior art, the invention has the beneficial effects that: the no-load control method can realize voltage balance between the series power devices through the common action of the two bridge arms under the special no-load condition that no output current exists or the output current is smaller than a certain threshold value and no follow current exists or the follow current is smaller than a certain threshold value in dead time; in the control method, the clamping capacitor is inserted into the circuit only in dead time, and the switching speed and the normal operation of the power switch tube are not influenced; in the no-load control method, the voltage balance of the clamping capacitors in the bridge arms is realized by a bridge arm individual control method, or the voltage balance of the clamping capacitors in the bridge arms and between the bridge arms is realized by a bridge arm cooperative control method; the control method can feed the energy in the clamping capacitor back to the direct current input side, and reduces the energy loss of the whole system.

Drawings

Fig. 1 is a block diagram of a half-bridge circuit 1000 with switches in series according to an embodiment of the present invention;

fig. 2 is a circuit schematic of first leg 10 and second leg 20 shown in fig. 1 according to an embodiment of the present invention;

FIG. 3 is a flowchart 2000 of a no-load control method for a bridge circuit with switches connected in series according to an embodiment of the present invention;

FIG. 4 is a flowchart 3000 of an idle control method for separately sequencing the legs of a bridge circuit having serially connected switches according to an embodiment of the present invention;

FIG. 5 is a flow chart 4000 of a method for controlling the no-load operation of the common sequencing of the legs of a bridge circuit having series-connected switches according to an embodiment of the present invention;

FIG. 6 is a waveform diagram of idle control with only one dead band in accordance with an embodiment of the present invention;

FIG. 7 is a schematic diagram of idle control performed on Y selected X cycles according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of half-bridge, full-bridge, and three-phase DC/AC conversion circuits implementing multiple switches in series, according to an embodiment of the present invention;

FIG. 9 is a waveform diagram illustrating an idle control method of the half-bridge DC/AC converting circuit shown in FIG. 8 according to an embodiment of the present invention;

fig. 10 is a circuit mode diagram of the discharge of the clamping capacitors of the first leg 10 and the second leg 20 during the second dead time in the waveform diagram shown in fig. 9 according to the embodiment of the present invention;

fig. 11 is a flowchart 5000 of an idle control method of a DC/AC converting circuit with switches connected in series according to an embodiment of the present invention.

Detailed Description

In order to describe the present invention more specifically, the following detailed description of the embodiments of the present invention is provided with reference to the accompanying drawings.

Fig. 1 is a block diagram of a half-bridge circuit 1000 with series-connected switches according to an embodiment of the present invention. The half-bridge circuit 1000 comprises a first bridge arm 10, a second bridge arm 20, a voltage sampling circuit 50 and a control circuit 60, wherein the first bridge arm 10The half-bridge circuit comprises a first end 101, a second end 102 and a control end 103, the control end 103 is configured to receive a first main switch signal g, the second bridge arm 20 comprises a first end 201, a second end 202 and a control end 203, the first end 201 of the second bridge arm 20 and the second end 102 of the first bridge arm 10 are coupled to a common end M1, the control end 203 of the second bridge arm 20 is configured to receive a second main switch signal g', and the half-bridge circuit 1000 outputs an output current i at the common end M1 _a And an output voltage v _r . In one embodiment, the output current i _a =0 or i _a And when the voltage is less than a certain threshold value, the bridge circuit is in a no-load working state, and the no-load control method is adopted when the bridge circuit is in the no-load working state. .

In one embodiment, a first dead time and a second dead time are included between the first main switching signal g and the second main switching signal g 'in each switching cycle, the first dead time being a dead time before a rising edge of the first main switching signal g, and the second dead time being a dead time before a rising edge of the second main switching signal g'. In one embodiment, the first main switching signal g is complementary to the second main switching signal g', and the first dead time or the second dead time is not limited to a duration of the dead time, but includes a timing of the dead time, and the like.

In one embodiment, the first bridge arm 10 can be configured as shown in fig. 2, and the first bridge arm 10 includes N main switches S coupled in series ₁₁ ～S _1N N is a natural number greater than or equal to 2, and the first main switch signal g is used for controlling the N main switches S ₁₁ ～S _1N Wherein each main switch S _1N Are all connected in parallel with an auxiliary module ARM1N, and each auxiliary module ARM1N comprises a clamping capacitor C _1N And an auxiliary switch tube S _a1N In one embodiment, each auxiliary switch tube S _a1N Comprising a reverse diode, each clamping capacitor C _1N Voltage across v _c1N (e.g. clamp capacitor C) ₁ Voltage across v _c11 ) Each auxiliary switching tube S _a1N Receive oneAn auxiliary switching signal g _aN (e.g. auxiliary switching signal g) _a1 For controlling the auxiliary switching tube S _a11 On and off). As shown in FIG. 1 in combination with the embodiment of FIG. 2 (a), the voltage sampling circuit 50 is used for sampling the clamping capacitor C ₁₁ ～C _1N Voltage v across _c11 ～v _c1N And outputs a corresponding voltage sampling signal v _c11 ’～v _c1N ', the control circuit 60 receives the voltage sampling signal v _c11 ’～v _c1N ', and sampling a signal v from said voltage _c11 ’～v _c1N ' and generating said auxiliary switching signal g _a1 ～g _aN To respectively control the auxiliary switch tube S _a11 ～S _a1N . In one embodiment, when a certain voltage is sampled, signal Vv _ci ' (i may refer to any of 1 to N, the same applies hereinafter) sampling the signal v at said voltage _c11 ’～v _c1N When the "middle row" is the front row p, the control circuit 60 controls the voltage sampling signal v _c1i ' auxiliary switch tube S in corresponding auxiliary module ARM1i _a1i Turning on a first preset time within the first dead time, wherein the first preset time is less than or equal to the first dead time, or the control circuit 60 controls the auxiliary switch tube S _a1i Turning on a second preset time within the second dead time, wherein the second preset time is less than or equal to the second dead time, and the second preset time may be equal to or different from the first preset time, or the control circuit 60 controls the auxiliary switch tube S _a1i Turning on a second preset time within the second dead time and turning on a first preset time within the first dead time, wherein p is a natural number greater than or equal to N/2, and in one embodiment, the auxiliary switch tube S _a1i The voltage difference between the voltage sum of the clamping capacitor in the first dead time or the second dead time and the input voltage is utilized to realize the clamping capacitor C _1i And feeds its energy back to the input side. In one embodiment, the preset duration may be set to a fixed value in advance, and in other embodiments, the preset duration may also be set to the fixed value at all timesThe adjustment is performed in real time or periodically as required, for example, the preset time period can be calculated in real time by a digital controller, or the preset time period can be adjusted according to a required feedback signal.

In one embodiment, the second bridge arm 20 can be configured as shown in fig. 2 (b), and the second bridge arm 20 includes N main switches S coupled in series ₂₁ ～S _2N The second main switch signal g' is used to control the N main switches S ₂₁ ～S _2N Wherein each main switch S _2N Are all connected with an auxiliary module ARM2N (such as a main switch S) ₂₁ Parallel auxiliary module ARM21, main switch S ₂₂ Parallel auxiliary modules ARM 22), each auxiliary module ARM2N comprising a clamping capacitor C _2N And an auxiliary switch tube S _a2N Each auxiliary switching tube S _a2N Comprising a reverse diode, and in one embodiment, each clamp capacitor C _2N Voltage across v _c2N Each auxiliary switching tube S _a2N Receiving an auxiliary switching signal g' _aN . The voltage sampling circuit 50 samples the clamp capacitor C ₂₁ ～C _2N Voltage v across _c21 ～v _c2N And outputs a corresponding voltage sampling signal v _c21 ’～v _c2N ', the control circuit 60 receives the voltage sampling signal v _c21 ’～v _c2N ', and sampling a signal v from said voltage _c21 ’～v _c2N 'generating the auxiliary switching signal g' _a1 ～g’ _aN To respectively control the auxiliary switch tubes S _a21 ～S _a2N . In one embodiment, the signal v is sampled at a certain voltage _c2i ' sampling a signal v at said voltage _c21 ’～v _c2N When the middle is the first q, the control circuit 60 controls the voltage sampling signal v _c2i ' auxiliary switch tube S in corresponding auxiliary module ARM2i _a2i A third preset time is opened within the first dead time, the third preset time is less than or equal to the first dead time, or the control circuit 60 controls the auxiliary switch tube S _a2i Turning on a fourth preset time within the second dead time, wherein the fourth preset time isThe length of the third preset time period is less than or equal to the second dead time, the third preset time period may be equal to or different from the first preset time period, the second preset time period and the fourth preset time period, or the control circuit 60 controls the auxiliary switch tube S _a2i And opening a fourth preset time length in the second dead time and opening a third preset time length in the first dead time, wherein q is a natural number which is greater than or equal to N/2, and the natural number q is equal to or different from the natural number p. In one embodiment, the auxiliary switch tube S _a2i The voltage difference between the voltage sum of the clamping capacitor in the first dead time or the second dead time and the input voltage is utilized to realize the clamping capacitor C _2i And feeds its energy back to the input side.

In other embodiments, the voltage sampling circuit 50 may also sample the clamp capacitor C ₁₁ ～C _1N And C ₂₁ ～C _2N Voltage v across _c11 ～v _c1N And v _c21 ～v _c2N And outputs a corresponding voltage sampling signal v _c11 ’～v _c1N ' and v _c21 ’～v _c2N ', the control circuit 60 receives the voltage sampling signal v _c11 ’～v _c1N ' and v _c21 ’～v _c2N ', and sampling a signal v from said voltage _c11 ’～v _c1N ' and v _c21 ’～v _c2N ' generating the auxiliary switching signal g _a1 ～g _aN And g' _a1 ～g’ _aN To respectively control the auxiliary switch tubes S _a11 ～S _a1N And S _a21 ～S _a2N . In one embodiment, the signal v is sampled at a certain voltage _c2i ' or v _c1i ' sampling a signal v at said voltage _c11 ’～v _c1N ' and v _c21 ’～v _c2N When the middle is the front Q, the control circuit 60 controls the voltage sampling signal v _c1i ' auxiliary switch tube S in corresponding auxiliary module ARM1i _a1i Turning on a first preset time within the first dead time, wherein the first preset time is less than or equal to the first dead time, or controlling by the control circuit 60Auxiliary switch tube S _a1i Turning on a second preset time within the second dead time, wherein the second preset time is less than or equal to the second dead time, and the second preset time may be equal to or different from the first preset time, or the control circuit 60 controls the auxiliary switch tube S _a1i And opening a second preset time length in the second dead time and opening a first preset time length in the first dead time. The control circuit 60 controls the voltage sampling signal v _c2i ' auxiliary switch tube S in corresponding auxiliary module ARM2i _a2i A third preset time is opened within the first dead time, the third preset time is less than or equal to the first dead time, or the control circuit 60 controls the auxiliary switch tube S _a2i A fourth preset time is switched on in the second dead time, the fourth preset time is less than or equal to the second dead time, the third preset time can be equal to or different from the first preset time, the second preset time and the fourth preset time, or the control circuit 60 controls the auxiliary switch tube S _a2i And opening a fourth preset time length in the second dead time and opening a third preset time length in the first dead time, wherein Q is a natural number greater than or equal to N. In one embodiment, the auxiliary switch tube S _a2i And S _a1i The voltage difference between the voltage sum of the clamping capacitor in the first dead time or the second dead time and the input voltage is utilized to realize the clamping voltage C _1i And C _2i And feeds its energy back to the input side. In one embodiment, taking the example that each of the first leg 10 and the second leg 20 includes 10 sub-modules (i.e. N = 10), the voltage sampling circuit 50 samples the clamp capacitor C ₁₁ ～C _{1_10} And C ₂₁ ～C _{2_10} Voltage v across _c11 ～v _{c1_10} And v _c21 ～v _{c2_10} The control circuit 60 receives the voltage sampling signal v _c11 ’～v _{c1_10} ' and v _c21 ’～v _{c2_10} ' parallel sorting, take Q =10, assume v in the sorting result _c11 ’～v _c13 ' and v _c21 ～v _c27 The first 10 bits are arranged in the row,the control circuit 60 controls the voltage sampling signal v _c11 ’～v _c13 ' auxiliary switch tube S in corresponding auxiliary modules ARM 11-ARM 11 _a11 ～S _a13 Turning on the preset duration within the dead time, the control circuit 60 controls the voltage sampling signal v _c21 ’～v _c27 ' auxiliary switch tube S in corresponding auxiliary modules ARM 21-ARM 27 _a21 ～S _a27 And opening the preset duration within the dead time.

Fig. 3 is a flowchart 2000 of a no-load control method for a bridge circuit with series-connected switches according to an embodiment of the present invention. A no-load control method for a bridge circuit having a series of switches, the bridge circuit comprising a first leg and a second leg coupled to a common terminal, the first leg comprising a plurality of first main switches coupled in series, wherein each of the first main switches is connected in parallel with a first auxiliary module, each of the first auxiliary modules comprises a first clamping capacitor and a first auxiliary switch, the second leg comprises a plurality of second main switches, wherein each of the second main switches is connected in parallel with a second auxiliary module, each of the second auxiliary modules comprises a second clamping capacitor and a second auxiliary switch, the first leg receives a first main switch signal for controlling the plurality of first main switches, the second leg receives a second main switch signal for controlling the plurality of second main switches, wherein in each switch cycle, a first dead time and a second dead time are included between the first main switch signal and the second main switch signal, the bridge leg comprises m first auxiliary switches and n second auxiliary switches, and the no-load control method comprises the steps S2:

and S2, controlling p first auxiliary switching tubes and q second auxiliary switching tubes to be respectively conducted with a first preset time and a second preset time within a first dead time in a switching period, wherein p and q are natural numbers, p + q is greater than or equal to (m + n)/2, the first preset time and the second preset time are equal to or less than the first dead time, and the first preset time and the second preset time can be equal to or different from each other.

Furthermore, the control method further includes controlling the p first auxiliary switching tubes and the q second auxiliary switching tubes to be respectively conducted for a third preset time and a fourth preset time within a second dead time in the switching cycle, where the first dead time and the second dead time are equal to or unequal, the third preset time and the fourth preset time are equal to or less than the second dead time, and the first, second, third, and fourth preset times are equal to or unequal.

Furthermore, the control method further includes controlling p first auxiliary switching tubes and q second auxiliary switching tubes to be respectively conducted for a fifth preset time length and a sixth preset time length in a second dead time in another switching cycle, where the second dead time in the another switching cycle is equal to or not equal to the second dead time in the first switching cycle, the fifth preset time length and the sixth preset time length are equal to or less than the second dead time in the another switching cycle, and the first, second, third, fourth, fifth and sixth preset time lengths are equal to or not equal to each other.

Further, the control method further includes controlling the p first auxiliary switching tubes and the q second auxiliary switching tubes to be respectively conducted for a seventh preset time length and an eighth preset time length in a first dead time of the other switching cycle, where the first dead time of the other switching cycle is equal to or not equal to the first dead time of the first switching cycle, the seventh preset time length and the eighth preset time length are equal to or less than the first dead time of the other switching cycle, and the first, second, third, fourth, fifth, sixth, seventh and eighth preset time lengths are equal to or not equal to each other.

Fig. 4 is a flowchart 3000 of an idle control method for jointly sequencing bridge arms of a bridge circuit with serially connected switches according to an embodiment of the present invention. The bridge circuit comprises a first bridge arm and a second bridge arm, the first bridge arm comprises a plurality of first main switches coupled in series, each first main switch is connected with an auxiliary module in parallel, each auxiliary module comprises a clamping capacitor and an auxiliary switch tube, the second bridge arm comprises a plurality of second main switches, the first bridge arm receives a first main switch signal to control the plurality of first main switches, the second bridge arm receives a second main switch signal to control the plurality of second main switches, a first dead time and a second dead time are included between the first main switch signal and the second main switch signal in each switching period, the bridge circuit comprises m first auxiliary switch tubes and n second auxiliary switch tubes, m and n are natural numbers, and the control method comprises steps S31-S33.

Step S31, in a switching period, sampling voltages at both ends of all the first clamping capacitors and voltages at both ends of all the second clamping capacitors and outputting corresponding voltage sampling signals.

And S32, uniformly sequencing all the voltage sampling signals according to the voltage from large to small to obtain an integral sequencing result.

And S33, selecting the first p first auxiliary switch tubes and the q second auxiliary switch tubes according to the integral sorting result, wherein the voltage sampling signals corresponding to the p first auxiliary switch tubes and the q second auxiliary switch tubes are all larger than the voltage sampling signals of the rest first auxiliary switch tubes and the rest second auxiliary switch tubes. And controlling the other first auxiliary switch tubes and the other second auxiliary switch tubes to be switched off in the first dead time and the second dead time. In one embodiment, the clamping capacitor corresponding to the auxiliary switch tube is discharged in the first dead time and the second dead time and energy is fed back to the direct current side. The no-load condition control method for the common sequencing of the bridge arms can simultaneously realize the voltage balance of the clamping capacitors in the bridge arms and between the bridge arms.

Fig. 5 is a flowchart 4000 of a method for controlling idle conditions by separately sequencing bridge arms of a bridge circuit having serially connected switches according to an embodiment of the present invention. The bridge circuit comprises a first bridge arm and a second bridge arm which are coupled to a common terminal, the first bridge arm comprises a plurality of first main switches which are coupled in series, each first main switch is connected with an auxiliary module in parallel, each auxiliary module comprises a clamping capacitor and an auxiliary switch tube, the second bridge arm comprises a plurality of second main switches, the first bridge arm receives a first main switch signal for controlling the plurality of first main switches, the second bridge arm receives a second main switch signal for controlling the plurality of second main switches, a first dead time and a second dead time are included between the first main switch signal and the second main switch signal in each switching period, the bridge circuit comprises m first auxiliary switch tubes and n second auxiliary switch tubes, m and n are natural numbers, and the control method comprises steps S41-S43.

Step S41, in a switching period, sampling voltages at two ends of the first clamping capacitor and outputting a corresponding first voltage sampling signal, and sampling voltages at two ends of the second clamping capacitor and outputting a corresponding second voltage sampling signal.

And S42, sequencing all the first voltage sampling signals according to the voltage from large to small to obtain a first sequencing result, and sequencing all the second voltage sampling signals according to the voltage from large to small to obtain a second sequencing result.

And S43, selecting the first p first auxiliary switch tubes according to the first sequencing result, and selecting the first q second auxiliary switch tubes according to the second sequencing result, wherein the first voltage sampling signals of the p first auxiliary switch tubes are greater than the first voltage sampling signals of the rest first auxiliary switch tubes, and the second voltage sampling signals of the q second auxiliary switch tubes are greater than the second voltage sampling signals of the rest second auxiliary switch tubes. And controlling the other first auxiliary switch tubes and the other second auxiliary switch tubes to be switched off in the first dead time and the second dead time. In one embodiment, the clamping capacitor corresponding to the auxiliary switch tube is discharged in the first dead time and the second dead time and energy is fed back to the direct current side. The no-load condition control method for respectively sequencing the bridge arms can realize voltage balance of the clamping capacitors in the bridge arms.

Fig. 6 is a waveform diagram for idle control with only one dead time in accordance with an embodiment of the present invention. In practice, in order to reduce the loss of the auxiliary switch tube, the auxiliary switch tube does not need to be closed in each dead time, and the voltage of the clamping capacitor is discharged to realize voltage equalization. In the embodiment as shown in fig. 6, the first dead time is a dead time before the first main switching signal g changes from a low level to a high level, t _d1 The first dead time is a time length of the first main switch signal, the second dead time is a dead time before the second main switch signal g' changes from low level to high level, t _d2 For a second dead time duration, t _d1 And t _d2 May be equal or different. g _a And g' _a, Respectively turning on the pulse of the auxiliary switch tube in the first bridge arm 10 and the pulse of the auxiliary switch tube in the second bridge arm 20 _a0 Is the turn-off signal of the auxiliary switching tube in the first bridge arm 10 and the second bridge arm 20. Pulse-on drive signal g _a And g' _a Maintaining a high level, g, for a period of time during a first dead time and a second dead time _a Opening for a short time in advance of the first dead zone, g' _a And the switch-on is carried out for a short time in advance of the second dead zone, and in order to ensure that the zero voltage of the corresponding auxiliary switch tube is switched on, the rest time is low level. Pulse-on drive signal g _a The duration of maintaining the high level in the first dead time and the second dead time is t _a1 And t _a3 Pulse-on drive signal g' _a The duration of maintaining the high level in the first dead time and the second dead time is t _a2 And t _a4 Said t is _a1 ,t _a2 ,t _a3 And t _a4 May be equal or unequal. In the embodiment illustrated in FIG. 9, t _a1 ＝t _a4 ，t _a2 ＝t _a3 And t is _a1 <t _d1 ，t _a2 <t _d2 ，t _a1 And t _a2 Can be adjusted according to circuit parameters, the dead zone time length t _d1 And t _d2 The switching frequency of the circuit is set according to actual requirements. FIG. 6 (a) is a diagram illustrating idle load control during a first dead time and a second dead time according to an embodiment of the present inventionMaking a waveform diagram of the driving signal, the clamping capacitance of the selected submodule is at t of the first dead time ₈ ～t ₉ T of phase and second dead time ₃ ～t ₄ Discharge in the phase and feed back energy to the input side. FIG. 6 (b) is a waveform diagram of a driving signal with no-load control during a first dead time and no-load control during a second dead time, wherein the clamp capacitance of a selected sub-module is at t of the first dead time ₅ ～t ₆ Discharge in the phase and feed back energy to the input side. FIG. 6 (c) is a waveform diagram of a driving signal with no-load control during only the second dead time and no control during the first dead time, wherein the clamp capacitance of the selected sub-module is at t of the second dead time ₃ ～t ₄ Discharge in the phase and feed back energy to the input side.

Fig. 7 is a waveform diagram of selecting Y of X cycles for idle control according to an embodiment of the present invention. In fact, no-load control is necessary in every switching cycle in order to further reduce the losses of the auxiliary switching tube. As shown in fig. 7, in X consecutive switching cycles, Y switching cycles are selected to be controlled by the no-load control method, where Y is a positive integer less than or equal to X. Meanwhile, Y first dead time and Y second dead time exist in Y switching cycles, the first dead time can be selected according to actual needs to carry out no-load control, or the second dead time can be selected to carry out no-load control, or the first dead time and the second dead time can both carry out no-load control. For example, in X consecutive switching periods (X ≧ 3) in fig. 7, Y =3 switching periods are selected for the idle control, that is, the 1 st, 3 rd and xth switching periods, the 1 st switching period may select a first dead time for the idle control, the 3 rd switching period may select a second dead time for the idle control, and the xth switching period may perform the idle control with both the first dead time and the second dead time. In the 1 st switching period, p first auxiliary switching tubes and q second auxiliary switching tubes are controlled to be respectively conducted for a first preset time and a second preset time in a first dead time, all the first auxiliary switching tubes and all the second auxiliary switching tubes are controlled to be turned off in the second dead time, the first preset time and the second preset time are less than or equal to the first dead time, p and q are natural numbers, and p + q is greater than or equal to (m + n)/2. In the 3 rd switching period, p first auxiliary switching tubes and q second auxiliary switching tubes are controlled to be respectively conducted for a third preset time and a fourth preset time in a second dead time, all the first auxiliary switching tubes and all the second auxiliary switching tubes are controlled to be turned off in the first dead time, and the third preset time and the fourth preset time are less than or equal to the second dead time. In the Xth switching period, p first auxiliary switching tubes and q second auxiliary switching tubes are controlled to be respectively conducted for a fifth preset time and a sixth preset time in a first dead time, and p first auxiliary switching tubes and q second auxiliary switching tubes are controlled to be respectively conducted for a seventh preset time and an eighth preset time in a second dead time, wherein the fifth preset time and the sixth preset time are less than or equal to the first dead time, the seventh preset time and the eighth preset time are less than or equal to the second dead time, and the first to eighth preset times are equal or unequal.

Fig. 8 is a schematic diagram of half-bridge, full-bridge and three-phase DC/AC conversion circuits implementing multiple switches in series according to an embodiment of the present invention. The half-bridge DC/AC conversion circuit (as shown in fig. 8 (a)) includes a half-bridge circuit 110 and a filter device 120, where the half-bridge circuit 110 includes two bridge-arm capacitors C _i And a half-bridge circuit comprising a first leg 10 and a second leg 20 connected in series with switches as shown in fig. 1, the two leg midpoints M1 and M2 of the half-bridge circuit 100 being connected to a load via a filter arrangement 120. The full-bridge DC/AC conversion circuit (as shown in fig. 8 (b)) includes a full-bridge circuit 130 and a filter device 140, where the full-bridge circuit 130 includes a first bridge arm 10, a second bridge arm 20, a third bridge arm 30 and a fourth bridge arm 40, and two bridge arm midpoints M1 and M2 of the full-bridge circuit 130 are connected to a load through the filter device 140. The third leg 30 and the fourth leg 40 are similar in structure to the first leg 10 and the second leg 20 in the control method. The three-phase DC/AC conversion circuit (as shown in FIG. 8 (c)) includes a three-phase bridge circuit 150 and a filter device 160The full-bridge circuit 150 includes a first bridge arm 10, a second bridge arm 20, a third bridge arm 30, a fourth bridge arm 40, a fifth bridge arm 50, and a sixth bridge arm 60, and three bridge arm midpoints M1, M2, and M3 of the three-phase bridge circuit 150 are connected to a load through a filter device 160. Fifth leg 50 and sixth leg 60 are similar in construction to first leg 10 and second leg 20 in terms of control methods. The load can be an alternating current source such as a power grid, a motor or heating equipment, and the like, and the research is carried out on a control method under the no-load condition, namely the output current i _a ，i _b And i _c Are all zero current. The filter means 120, 140 and 160 comprise a filter inductance L _f And a filter capacitor C _f Damping resistors may also be included; v _dc And V _ac The DC side voltage and the AC side voltage of the DC/AC conversion circuit, respectively. In the embodiment shown in fig. 8 (a), for convenience of description, each main switch and the auxiliary module connected in parallel therewith are defined as a sub-module, that is, the first bridge leg 10 includes sub-modules SM11 to SM1N coupled in series, the second bridge leg 20 includes sub-modules SM21 to SM2N coupled in series, where each sub-module SM1i and SM2i includes a main switch S and an auxiliary diode D _a An auxiliary switch tube S _a And a clamping capacitor C, the auxiliary switch tube S _a The clamping capacitor C is connected in series and then connected to two ends of the main switch S, two output ports of each submodule are positioned at two ends of the main switch S, and the auxiliary diode D _a And an auxiliary switch tube S _a Inverse parallel connection, i _arm The direction shown in fig. 8 (a) is a positive direction for the bridge arm current. For convenience of description, elements in each sub-module are not differently numbered, but in an actual embodiment, the first leg 10 shown in fig. 8 (a) has the same structure and respective element numbers as those of the first leg 10 shown in fig. 2 (a), and the second leg 20 shown in fig. 8 (a) has the same structure and respective element numbers as those of the second leg 20 shown in fig. 2 (b). Similarly, the third leg 30 and fourth leg 40 shown in fig. 8 (b) are similar in structure to the first leg 10 and second leg 20 except that the drive signals of the main switch S are 180 degrees out of phase. Sequencing of clamping capacitors of the third bridge arm and the fourth bridge arm and control of auxiliary switching tubesThe first leg and the second leg are independent of each other. The fifth leg 50 and sixth leg 60 shown in fig. 8 (c) are also similar in structure to first leg 10 and second leg 20, except that the drive signals for main switches S of first leg 10 and second leg 20, third leg 30 and fourth leg 40, and fifth leg 50 and sixth leg 60 differ in phase by 120 degrees. The sequencing of the clamping capacitors of the third bridge arm and the fourth bridge arm, and the sequencing of the clamping capacitors of the fifth bridge arm and the sixth bridge arm, and the control of the auxiliary switching tubes are independent of the first bridge arm and the second bridge arm. It should be noted that fig. 8 is a topology of a two-level DC/AC conversion circuit, which is the most common topology, in practical applications, a midpoint clamp (NPC), a cascade H-bridge (CHB), and a Modular Multilevel (MMC) DC/AC conversion circuit replace a single power device with a bridge arm (a first bridge arm or a second bridge arm) with a series-connected switch, and may also discharge a clamping capacitor in the bridge arm by using the same control method.

Fig. 9 is a waveform diagram of an idle control method of the half-bridge DC/AC converting circuit shown in fig. 8 according to an embodiment of the invention. V _dc Is an input voltage of the DC/AC conversion circuit, v ₁₀ Bridge arm voltage, v, of first bridge arm 10 ₂₀ Bridge arm voltage i of second bridge arm 20 ₁ For bridge arm current, i _a To output a current, i _a =0 or i _a When the amplitude of the voltage is smaller than a certain threshold value, the circuit is in a no-load working state, and the no-load control method is adopted when the bridge circuit is in the no-load working state. T is _s For the switching period of each main switch, in the embodiment as shown in fig. 9, the first dead time is a dead time before the first main switch signal g changes from the low level to the high level, t _d1 The first dead time is a time length of the first main switch signal, the second dead time is a dead time before the second main switch signal g' changes from low level to high level, t _d2 For a second dead time duration, t _d1 And t _d2 May be equal or different. g _a And g' _a, Respectively turning on the pulse of the auxiliary switch tube in the first bridge arm 10 and the pulse of the auxiliary switch tube in the second bridge arm 20 _a0 A pulse-on driving signal g for the turn-off signals of the auxiliary switching tubes in the first bridge arm 10 and the second bridge arm 20 _a And g' _a In the first placeThe dead time and the second dead time are maintained at a high level, g, for a period of time _a Opening for a short time in advance of the first dead zone, g' _a And the auxiliary switch tube is switched on for a short time in advance of the second dead zone, and the rest time is low level in order to ensure the zero voltage switching on of the corresponding auxiliary switch tube. In one embodiment as illustrated in FIG. 9, the pulsed ON drive signal g _a (g’ _a ) At least half of the auxiliary switching tubes in the first (second) bridge arm are respectively distributed, and the driving signals of the other auxiliary switching tubes are all turn-off signals g _a0 I.e. always remains low. Pulse-on drive signal g _a The duration of maintaining the high level in the first dead time and the second dead time is t _a1 And t _a2 Pulse-on drive signal g' _a The duration of maintaining the high level in the first dead time and the second dead time is t _a3 And t _a4 Said t is _a1 ,t _a2 ,t _a3 And t _a4 May be equal or unequal. In the embodiment illustrated in FIG. 9, t _a1 ＝t _a3 ，t _a2 ＝t _a4 And t is _a1 <t _d1 ，t _a2 <t _d2 ，t _a1 And t _a2 Can be adjusted according to circuit parameters, the dead time duration t _d1 And t _d2 The switching frequency of the circuit is set according to actual requirements.

In the embodiment shown in fig. 9, 0 represents the start time of one switching cycle at which the first main switching signal g changes from low level to high level; t is t ₃ Representing the moment when the first main switching signal g changes from high to low, and, at the same time, t ₃ The moment is also the starting moment of the second dead time in the switching period, and the driving signal g 'is switched on in a pulse mode' _a, Is also at t ₂ The time is changed from low level to high level and is slightly ahead of the second dead time; t is t ₄ Representing the pulse-on drive signal g _a, The time when the low level is changed into the high level; t is t ₅ Representing a pulse-on drive signal g' _a, And g _a The time when the high level is changed into the low level; t is t ₆ Represents the moment when the second main switching signal g' changes from low level to high level, and so onOne switching period T _s An end time of the inner second dead time; t is t ₉ Represents the time when the second main switching signal g' changes from high level to low level, and is also the switching period T _s At the start of the first dead time, the drive signal g is pulsed on _a, Is also at t ₈ The time is changed from low level to high level and is slightly ahead of the first dead time; t is t ₁₀ Representing a pulse-on drive signal g' _a, The time when the low level is changed into the high level; t is t ₁₁ Representing a pulse-on drive signal g' _a, And g _a The time when the high level is changed into the low level; t is t ₁₂ Representing this switching period T _s The first main switching signal g changes from low level to high level at this point in time. At 0 to t ₁₂ In this switching period, the second dead time t ₃ ～t ₆ In the first bridge arm 10, a pulse-on drive signal g is obtained _a The submodules of (1) are SM 11-SM 1k, and the pulse-on driving signal g 'is obtained from the second bridge arm 20' _a The sub-modules of the system are SM 21-SM 2j, and the other sub-modules obtain a turn-off signal g _a0 ，v _c1k ，v _c2j The voltage waveforms of the clamping capacitors in the submodules SM1k and SM2j are shown, wherein j and k can represent any natural number from 1 to N, and k + j is more than or equal to N. In the waveform diagram shown in fig. 9, the voltage waveform of the clamping capacitor is amplified to show the operation characteristics of the circuit in the embodiment, and in the actual circuit operation, the magnitude of the change of the voltage of the clamping capacitor is influenced by the capacitance value of the clamping capacitor C.

Fig. 10 is a circuit mode diagram illustrating discharge of the clamp capacitors of the first leg 10 and the second leg 20 during the second dead time in the waveform diagram shown in fig. 9 according to the embodiment of the present invention. FIG. 9 shows the pulse driving signal g in the second dead time _a, And g' _a The circuit mode diagrams of the first bridge arm 10 and the second bridge arm 20 in the high level period are maintained, and correspond to the second dead time (t) shown in fig. 9 ₃ ～t ₆ ) Inner t ₄ ～t ₅ Stage (2): wherein, t ₄ <t<t ₅ In the meantime, the main switches S in the first arm 10 and the second arm 20 are both turned off, because the submodules SM11 to SM1k in the first arm 10 and the submodules SM2 in the second arm 20Auxiliary switch tube S in 1-SM 2j _a The sub-modules are switched on, so that the clamping capacitors C in the sub-modules are connected with the parasitic capacitors of the corresponding main switches S in parallel, and when the sum of the voltages of the clamping capacitors is greater than the input voltage V, because k + j is more than or equal to N _dc When the temperature of the water is higher than the set temperature,

v _c11 +…+v _c1k +v _c21 +…+v _c2j ≥V _dc

the clamp capacitor will naturally discharge to the input side with the bridge arm discharge current i ₁ And recovering energy to the input side until t ₅ Auxiliary switch tube S in time submodules SM 11-SM 1k and SM 21-SM 2j _a And (6) turning off. The capacitance value of the clamping capacitor C is far larger than that of the parasitic capacitor of the main switch S, so that the bridge arm discharge current is i ₁ Mainly flows through a clamping capacitor C, parasitic capacitors in the other sub-modules in the first bridge arm and the second bridge arm are quickly discharged to 0, and the bridge arm discharge current is i ₁ The anti-parallel diode of the main switch S.

In the embodiment shown in FIG. 9, the values are from 0 to t ₁₂ In this switching period, t ₂ Auxiliary switching tube S in submodules SM 21-SM 2j in second bridge arm 20 at any moment _a At this moment, the main switch tube of the submodule in the first bridge arm 10 is still conducting, so the auxiliary switch tube S in the second bridge arm 20 _a The voltage at the two ends is approximately equal to zero, and the auxiliary switch tube can realize the quasi-zero voltage switching-on. t is t ₄ Auxiliary switching tube S in submodules SM 11-SM 1k in first bridge arm 10 at any moment _a Turn on slightly later than the start time t of the second dead time ₃ In order to prevent the main switch tube and the auxiliary switch tube in the first bridge arm from penetrating. t is t ₅ ～t ₆ Stage, auxiliary switch tube S _a After the switch-off, oscillation exists between the parasitic capacitance of the main switch tube and the parasitic inductance of the loop.

Under the method of the bridge arm individual sequencing control as shown in fig. 5, as shown in fig. 9, the second dead time t ₄ ～t ₅ In the stage, the voltage of the clamping capacitors in SM 11-SM 1k (k is more than or equal to N/2) and SM 21-SM 2j (j is more than or equal to N/2) is higher, and the auxiliary switch tube S in the submodule is connected with the auxiliary switch tube S _a Voltage v of turn-on and clamping capacitor _c11 ～v _c1k And v _c21 ～v _c2j Decreases while the remaining sub-module capacitor voltages do not change (only v is drawn in fig. 9) _c1k ，v _c2j ，v _c2N And v _c1N Waveform schematic), then the stage ends and the clamp capacitor voltage becomes higher in SM1 (k + 1) -SM 1N and SM2 (j + 1) -SM 2N. t is t ₆ At the moment, the main switch tube of the submodule in the second bridge arm 20 is conducted, and the instantaneous forward bridge arm current i ₁ Will give a clamping capacitance C in first leg 10 ₁₁ ～C _1N Charging, similarly, the process also exists that at the time 0, the main switch tube of the submodule in the first bridge arm 10 is conducted, i ₁ To the clamp capacitance C in the second leg 20 ₂₁ ～C _2N And charging, wherein the charging quantity of all sub-module clamping capacitors in the bridge arm is the same. Then at the next dead time, the first dead time t ₉ ～t ₁₂ In the stage, the voltage of the clamping capacitor in SM1 (k + 1) -SM 1N and SM2 (j + 1) -SM 2N is higher, and the auxiliary switch tube S in the sub-module is _a Voltage v of turn-on and clamping capacitor _c1(k+1) ～v _c1N And v _c2(j+1) ～v _c2N And the voltage of the capacitor of the rest sub-modules is reduced and unchanged, then the stage is ended, and the voltage of the clamping capacitor in SM 11-SM 1k and SM 21-SM 2j becomes higher, thereby realizing the compensation of the unbalanced voltage. Under the no-load control method shown in fig. 5, the voltage-equalizing process is continuously performed in each switching period, and finally the voltage of the clamping capacitor in each bridge arm is at V _dc Dynamic equilibrium at/N.

Under the no-load control method of the common bridge arm sequencing as shown in FIG. 4, auxiliary switch tubes S in Q (Q is larger than or equal to N) sub-modules SM 1-SMQ are selected according to the sequencing result of the clamp capacitor voltages in 2N sub-modules SM 1-SM (2N) in total of the first bridge arm 10 and the second bridge arm 20 _a And (3) switching on to reduce the voltage of the clamping capacitor of the voltage compensation circuit, and keeping the voltage of the capacitors of the other sub-modules unchanged, so that the stage is ended, and the voltage of the clamping capacitors in SM (Q + 1) -SM 2N is changed to be higher, thereby realizing the compensation of the unbalanced voltage. Because the method of sequencing the bridge arms together is adopted, the balance of the capacitance voltage in the bridge arms can be realized, and the balance of the capacitance voltage between the bridge arms can also be realized.

Fig. 11 is a flowchart 5000 of an idle-load control method for a DC/AC conversion circuit with serially connected switches according to an embodiment of the present invention. The DC/AC conversion circuit includes: the bridge circuit comprises a first bridge arm and a second bridge arm which are coupled to a common terminal, the first bridge arm comprises a plurality of first main switches which are coupled in series, each first main switch is connected with a first auxiliary module in parallel, each first auxiliary module comprises a first clamping capacitor and a second auxiliary switch tube, the second bridge arm comprises a plurality of second main switches, each second main switch is connected with a second auxiliary module in parallel, each second auxiliary module comprises a second clamping capacitor and a second auxiliary switch tube, the bridge circuit comprises m first auxiliary switch tubes and n second auxiliary switch tubes, m and n are natural numbers, one switching cycle of the DC/AC conversion circuit comprises a first time period, a second time period, a first dead time and a second dead time, and the dead time control method comprises steps S51-S54.

And S51, controlling the plurality of first main switches to be switched off, controlling the plurality of second main switches to be switched on, and switching off all the first auxiliary switch tubes and the second auxiliary switch tubes in a first time period.

Step S52, in a first dead time, controlling the plurality of first main switches and the plurality of second main switches to be turned off, controlling p first auxiliary switch tubes to be conducted for a first preset time period, and controlling q second auxiliary switch tubes to be conducted for a second preset time period, wherein p and q are natural numbers, p + q is more than or equal to (m + n)/2, controlling the rest of first auxiliary switch tubes and the rest of second auxiliary switch tubes to be turned off, and discharging first clamping capacitors corresponding to the p first auxiliary switch tubes and second clamping capacitors corresponding to the q second auxiliary switch tubes;

and S53, in a second time period, controlling the plurality of first main switches to be connected, the plurality of second main switches to be disconnected, and the first auxiliary switch tube and the second auxiliary switch tube to be disconnected, so as to control the bridge circuit to enter an inversion state.

And S54, in a second dead time, controlling the plurality of first main switches and the plurality of second main switches to be turned off, controlling the p first auxiliary switch tubes to be conducted for a third preset time period, controlling the q second auxiliary switch tubes to be conducted for a fourth preset time period, controlling the other first auxiliary switch tubes and the other second auxiliary switch tubes to be turned off, and discharging first clamping capacitors corresponding to the p first auxiliary switch tubes and second clamping capacitors corresponding to the q second auxiliary switch tubes.

A no-load control method of a DC/AC conversion circuit as shown in fig. 11, the control method comprising:

the method comprises the steps that a control circuit is utilized to sequence voltages at two ends of all first clamping capacitors and all second clamping capacitors of a first bridge arm and a second bridge arm together to obtain an integral sequencing result, and according to the integral sequencing result, the first p first auxiliary switch tubes and the q second auxiliary switch tubes are selected from the large voltage to the small voltage, wherein the voltages at two ends of the first clamping capacitors and the second clamping capacitors corresponding to the p first auxiliary switch tubes and the q second auxiliary switch tubes are larger than the voltages at two ends of the first clamping capacitors and the second clamping capacitors corresponding to the rest first auxiliary switch tubes and the rest second auxiliary switch tubes.

The no-load control method of the DC/AC conversion circuit shown in fig. 11 further includes:

and utilizing a control circuit to sequence voltages at two ends of all first clamping capacitors of a first bridge arm from large to small according to the voltage to obtain a first sequencing result, sequence voltages at two ends of all second clamping capacitors of a second bridge arm from large to small according to the voltage to obtain a second sequencing result, selecting the first p first auxiliary switch tubes according to the first sequencing result, and selecting the first q second auxiliary switch tubes according to the second sequencing result, wherein the voltages at two ends of the first clamping capacitors corresponding to the p first auxiliary switch tubes are greater than the voltages at two ends of the first clamping capacitors corresponding to the other first auxiliary switch tubes, and the voltages at two ends of the second clamping capacitors corresponding to the q second auxiliary switch tubes are greater than the voltages at two ends of the second clamping capacitors corresponding to the other second auxiliary switch tubes.

In one embodiment, the first period of time is first main switch signal holdThe period of low level and the second main switch signal is maintained at high level corresponds to t in the waveform diagram of the DC/AC converting circuit embodiment shown in FIG. 9 ₆ ～t ₉ The first dead time is the time period after the first main switch signal maintains low level and the second main switch signal changes from high level to low level, which corresponds to t in the waveform diagram of the embodiment of the DC/AC conversion circuit shown in FIG. 9 ₉ ～t ₁₂ The second time period, which is the time period when the first main switch signal changes from low level to high level and the second main switch signal maintains low level, corresponds to 0-t in the waveform diagram of the embodiment of the DC/AC converting circuit shown in fig. 9 ₃ The second dead time is a time period when the first main switch signal changes from high level to low level and the second main switch signal maintains low level, which corresponds to t in the waveform diagram of the embodiment of the DC/AC converting circuit shown in fig. 9 ₃ ～t ₆ A time period.

The above embodiments are only for illustrating the technical conception and the application features of the present invention, and the purpose of the present invention is to enable the engineer skilled in the art to understand the meaning and the application of the present invention, but not to limit the protection scope of the present invention. The details of the above-described circuit configuration and its control method may vary considerably in its implementation, while still being encompassed by the invention disclosed herein. All equivalent changes and modifications made according to the spirit of the present invention should be covered in the protection scope of the present invention.

Claims

1. A method for controlling a bridge circuit having a series of switches, said bridge circuit comprising a first leg and a second leg coupled to a common terminal, said first leg comprising a plurality of first main switches coupled in series, wherein each of said first main switches is connected in parallel to a first auxiliary module, each of said first auxiliary modules comprises a first clamping capacitor and a first auxiliary switch, said second leg comprises a plurality of second main switches, wherein each of said second main switches is connected in parallel to a second auxiliary module, each of said second auxiliary modules comprises a second clamping capacitor and a second auxiliary switch, said first leg receives a first main switch signal for controlling said plurality of first main switches, said second leg receives a second main switch signal for controlling said plurality of second main switches, wherein during each switching cycle, there is a first dead time and a second dead time between said first main switch signal and said second main switch signal, said bridge circuit comprises m first auxiliary switches and n second auxiliary switches, and said method comprises a natural number of controlling said first leg and second leg, said method comprising:

and controlling p first auxiliary switching tubes and q second auxiliary switching tubes to be respectively conducted for a first preset time length and a second preset time length in a first dead time in a switching period, wherein p and q are natural numbers, and p + q is more than or equal to (m + n)/2.

2. The no-load control method of claim 1, further comprising: and controlling the p first auxiliary switching tubes and the q second auxiliary switching tubes to be respectively conducted for a third preset time and a fourth preset time in a second dead time in the switching period.

3. The no-load control method of claim 1, further comprising: and controlling the p first auxiliary switching tubes and the q second auxiliary switching tubes to be switched off in a second dead time in the switching period.

4. The no-load control method of claim 1, further comprising: and controlling the p first auxiliary switching tubes and the q second auxiliary switching tubes to be respectively conducted for a fifth preset time length and a sixth preset time length in a second dead time in another switching period.

5. The empty load control method of claim 4, further comprising: and controlling the p first auxiliary switching tubes and the q second auxiliary switching tubes to be respectively conducted for a seventh preset time length and an eighth preset time length in the first dead time in the other switching period.

6. The empty load control method of claim 1, said control method further comprising:

in a switching period, sampling voltages at two ends of all the first clamping capacitors and voltages at two ends of all the second clamping capacitors and outputting corresponding voltage sampling signals;

uniformly sequencing all the voltage sampling signals according to the voltage from large to small to obtain an integral sequencing result; and

and selecting the first p first auxiliary switch tubes and the q second auxiliary switch tubes according to the whole sequencing result, wherein the voltage sampling signals corresponding to the p first auxiliary switch tubes and the q second auxiliary switch tubes are all larger than the voltage sampling signals of the other first auxiliary switch tubes and the other second auxiliary switch tubes.

7. The empty load control method of claim 1, said control method further comprising:

in a switching period, sampling voltages at two ends of all the first clamping capacitors and outputting corresponding first voltage sampling signals, and sampling voltages at two ends of all the second clamping capacitors and outputting corresponding second voltage sampling signals;

sequencing all the first voltage sampling signals according to the voltage from large to small to obtain a first sequencing result, and sequencing all the second voltage sampling signals according to the voltage from large to small to obtain a second sequencing result; and

and selecting the first p first auxiliary switch tubes according to the first sequencing result, and selecting the first q second auxiliary switch tubes according to the second sequencing result, wherein the first voltage sampling signals of the p first auxiliary switch tubes are greater than the first voltage sampling signals of the rest first auxiliary switch tubes, and the second voltage sampling signals of the q second auxiliary switch tubes are greater than the second voltage sampling signals of the rest second auxiliary switch tubes.

8. The no-load control method according to claim 6 or 7, further comprising:

and controlling the other first auxiliary switch tubes and the other second auxiliary switch tubes to be switched off in the first dead time and the second dead time.

9. The no-load control method as claimed in any one of claims 1 to 8, wherein said bridge circuit outputs an output current and an output voltage at said common terminal, said bridge circuit is in the no-load operation state when the output current is zero current or less than a certain threshold, and said no-load control method is adopted when said bridge circuit is in the no-load operation state.

10. An empty load control method as claimed in any one of claims 1 to 8, carried out in each switching cycle, or carried out using the empty load control method by selecting Y switching cycles out of X consecutive switching cycles, where Y is a positive integer less than or equal to X.

11. A no-load control method of a DC/AC conversion circuit switching in series, the DC/AC conversion circuit comprising: a bridge circuit, a filter device and an output load connected in series by switches, wherein the bridge circuit includes a first bridge arm and a second bridge arm coupled in series, the first bridge arm includes a plurality of first main switches coupled in series, each of the first main switches is connected in parallel to a first auxiliary module, each of the first auxiliary modules includes a first clamping capacitor and a second auxiliary switch tube, the second bridge arm includes a plurality of second main switches, each of the second main switches is connected in parallel to a second auxiliary module, each of the second auxiliary modules includes a second clamping capacitor and a second auxiliary switch tube, the bridge circuit includes m first auxiliary switch tubes and n second auxiliary switch tubes, m and n are natural numbers, a switching cycle of the DC/AC conversion circuit includes a first time period, a second time period, a first dead time and a second dead time, and the dead time control method includes:

in a first time period, the plurality of first main switches are controlled to be turned off, the plurality of second main switches are controlled to be turned on, and all the first auxiliary switch tubes and the second auxiliary switch tubes are turned off;

in a first dead time, controlling the plurality of first main switches and the plurality of second main switches to be turned off, controlling p first auxiliary switch tubes to be conducted for a first preset time period, and controlling q second auxiliary switch tubes to be conducted for a second preset time period, wherein p and q are natural numbers, and p + q is more than or equal to (m + n)/2, controlling the rest of first auxiliary switch tubes and the rest of second auxiliary switch tubes to be turned off, and discharging first clamping capacitors corresponding to the p first auxiliary switch tubes and second clamping capacitors corresponding to the q second auxiliary switch tubes;

in a second time period, the plurality of first main switches are controlled to be switched on, the plurality of second main switches are switched off, and the first auxiliary switch tube and the second auxiliary switch tube are both switched off to control the bridge circuit to enter an inversion state; and

and in a second dead time, controlling the plurality of first main switches and the plurality of second main switches to be turned off, controlling p first auxiliary switch tubes to be conducted for a third preset time, controlling q second auxiliary switch tubes to be conducted for a fourth preset time, controlling the other first auxiliary switch tubes and the other second auxiliary switch tubes to be turned off, and discharging first clamping capacitors corresponding to the p first auxiliary switch tubes and second clamping capacitors corresponding to the q second auxiliary switch tubes.

12. The empty load control method of claim 11, further comprising:

13. The empty load control method of claim 11, further comprising:

14. The no-load control method of claim 11, wherein the DC/AC conversion circuit further comprises a third leg and a fourth leg, the main switch signals of the third leg and the fourth leg are 180 degrees out of phase with the main switch signals of the first leg and the second leg, and the order of the clamping capacitors of the third leg and the fourth leg and the control of the auxiliary switch tubes are independent of the first leg and the second leg.

15. The no-load control method of claim 11, wherein the DC/AC conversion circuit further comprises a third arm and a fourth arm, a fifth arm and a sixth arm, the main switch signals of the third arm and the fourth arm, the fifth arm and the sixth arm, and the main switch signals of the first arm and the second arm have a phase difference of 120 degrees, and the order of the clamp capacitors of the third arm and the fourth arm, and the fifth arm and the sixth arm, and the control of the auxiliary switch tubes are independent of the first arm and the second arm.