CN115390846A - Compiling construction method and device, electronic equipment and storage medium - Google Patents
Compiling construction method and device, electronic equipment and storage medium Download PDFInfo
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- CN115390846A CN115390846A CN202210964744.XA CN202210964744A CN115390846A CN 115390846 A CN115390846 A CN 115390846A CN 202210964744 A CN202210964744 A CN 202210964744A CN 115390846 A CN115390846 A CN 115390846A
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Abstract
The embodiment of the disclosure discloses a compiling construction method, a compiling construction device, an electronic device and a storage medium, wherein the method comprises the following steps: determining compiling task parameter information, wherein the compiling task parameter information comprises compiling task parameters corresponding to at least one processor core; generating a compiling task rule file corresponding to the processor core based on the compiling task parameter information; running a compiling task rule file based on the compiling class object corresponding to the processor core to generate an intermediate file corresponding to the processor core; and generating a target file corresponding to the processor core based on the intermediate file corresponding to the processor core. The compiling task rule file for controlling compiling corresponding to each processor core can be automatically generated aiming at the isomorphic multi-core or the heterogeneous multi-core, so that compiling work of the plurality of processor cores is realized, relevant personnel do not need to develop corresponding makefile scripts aiming at each processor core, relevant workload is greatly reduced, and compiling efficiency is effectively improved.
Description
Technical Field
The present disclosure relates to compiling technologies, and in particular, to a compiling construction method, apparatus, electronic device, and storage medium.
Background
With the rapid development of processor technology, a multi-core processor becomes a mainstream technology, and generally, a multi-core processor has a plurality of cores, and the types of the multi-core processor can include homogeneous multi-cores and heterogeneous multi-cores. In simulation verification of a multi-core system, particularly in simulation verification of a heterogeneous multi-core system, a related verification engineer is usually required to develop corresponding makefile scripts for cores of different architectures to process compilation work of heterogeneous multi-cores, and the makefile scripts are used for defining a series of rules to specify files needing to be compiled first, files needing to be compiled later, files needing to be compiled again and the like, so that the compilation efficiency is low, and further the verification work efficiency is low.
Disclosure of Invention
The method and the device for compiling the multi-core system solve the technical problems that the multi-core system is low in compiling efficiency and the like. The embodiment of the disclosure provides a compiling and constructing method and device, an electronic device and a storage medium.
According to an aspect of the embodiments of the present disclosure, there is provided a compilation building method including: determining compiling task parameter information, wherein the compiling task parameter information comprises compiling task parameters corresponding to at least one processor core; generating a compiling task rule file corresponding to the processor core based on the compiling task parameter information; running the compiling task rule file based on the compiling class object corresponding to the processor core to generate an intermediate file corresponding to the processor core; and generating a target file corresponding to the processor core based on the intermediate file corresponding to the processor core.
According to another aspect of the embodiments of the present disclosure, there is provided a compilation building apparatus including: the device comprises a first determining module, a second determining module and a third determining module, wherein the first determining module is used for determining compiling task parameter information, and the compiling task parameter information comprises compiling task parameters corresponding to at least one processor core; the first processing module is used for generating a compiling task rule file corresponding to the processor core based on the compiling task parameter information; the second processing module is used for running the compiling task rule file based on the compiling class object corresponding to the processor core and generating an intermediate file corresponding to the processor core; and the third processing module is used for generating a target file corresponding to the processor core based on the intermediate file corresponding to the processor core.
According to a further aspect of the embodiments of the present disclosure, there is provided a computer-readable storage medium storing a computer program for executing the compiling and constructing method according to any of the embodiments of the present disclosure.
According to still another aspect of an embodiment of the present disclosure, there is provided an electronic apparatus including: a processor; a memory for storing the processor-executable instructions; the processor is configured to read the executable instructions from the memory and execute the instructions to implement the compiling and building method according to any of the above embodiments of the disclosure.
Based on the compiling construction method, the compiling construction device, the electronic equipment and the storage medium provided by the embodiment of the disclosure, the compiling task rule file corresponding to each processor core and used for controlling compiling can be automatically generated aiming at the isomorphic multi-core or the isomerous multi-core, so that the compiling work of the plurality of processor cores is realized, relevant personnel do not need to develop corresponding makefile scripts aiming at each processor core, the relevant workload is greatly reduced, and the compiling efficiency is effectively improved.
The technical solution of the present disclosure is further described in detail by the accompanying drawings and examples.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent by describing in more detail embodiments of the present disclosure with reference to the attached drawings. The accompanying drawings are included to provide a further understanding of the embodiments of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure and not to limit the disclosure. In the drawings, like reference numbers generally represent like parts or steps.
FIG. 1 is an exemplary application scenario of a compilation build method provided by the present disclosure;
FIG. 2 is a flowchart illustrating a compilation build method according to an exemplary embodiment of the present disclosure;
FIG. 3 is a flowchart of step 202 provided by an exemplary embodiment of the present disclosure;
FIG. 4 is a schematic flow chart of step 2021 provided by an exemplary embodiment of the present disclosure;
FIG. 5 is a schematic flow chart of step 2021 provided by another exemplary embodiment of the present disclosure;
FIG. 6 is a flowchart of step 203 provided by an exemplary embodiment of the present disclosure;
FIG. 7 is a schematic flow chart of step 2022 provided by an exemplary embodiment of the present disclosure;
FIG. 8 is a flowchart of step 2024 provided by an exemplary embodiment of the present disclosure;
FIG. 9 is a flowchart illustration of a compilation build method provided by another exemplary embodiment of the present disclosure;
FIG. 10 is a flowchart illustration of a compilation build method provided by yet another exemplary embodiment of the present disclosure;
FIG. 11 is a block diagram of a compile build apparatus according to an exemplary embodiment of the present disclosure;
fig. 12 is a schematic structural diagram of a first processing module 502 provided in an exemplary embodiment of the present disclosure;
fig. 13 is a schematic structural diagram of a first determining unit 5021 provided in an exemplary embodiment of the present disclosure;
fig. 14 is a schematic structural diagram of a first determining unit 5021 provided in another exemplary embodiment of the present disclosure;
fig. 15 is a schematic structural diagram of a second processing module 503 according to an exemplary embodiment of the disclosure;
fig. 16 is a schematic structural diagram of the second determining unit 5022 provided in an exemplary embodiment of the present disclosure;
fig. 17 is a schematic structural diagram of a first generating unit 5024 provided in an exemplary embodiment of the present disclosure;
fig. 18 is a schematic structural diagram of a third processing module 504 provided in an exemplary embodiment of the present disclosure;
FIG. 19 is a block diagram of a compile building apparatus according to another exemplary embodiment of the present disclosure;
fig. 20 is a schematic structural diagram of the first determining module 501 provided in an exemplary embodiment of the present disclosure;
FIG. 21 is a block diagram illustrating a compile building apparatus according to still another exemplary embodiment;
fig. 22 is a schematic structural diagram of an application example of the electronic device of the present disclosure.
Detailed Description
Hereinafter, example embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. It is to be understood that the described embodiments are merely a subset of the embodiments of the present disclosure and not all embodiments of the present disclosure, with the understanding that the present disclosure is not limited to the example embodiments described herein.
It should be noted that: the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.
It will be understood by those of skill in the art that the terms "first," "second," and the like in the embodiments of the present disclosure are used merely to distinguish one element from another, and are not intended to imply any particular technical meaning, nor is the necessary logical order between them.
It is also understood that in embodiments of the present disclosure, "a plurality" may refer to two or more and "at least one" may refer to one, two or more.
It is also to be understood that any reference to any component, data, or structure in the embodiments of the present disclosure may be generally understood as one or more, unless explicitly defined otherwise or indicated to the contrary hereinafter.
In addition, the term "and/or" in the present disclosure is only one kind of association relationship describing an associated object, and means that three kinds of relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" in the present disclosure generally indicates that the former and latter associated objects are in an "or" relationship.
It should also be understood that the description of the various embodiments of the present disclosure emphasizes the differences between the various embodiments, and the same or similar parts may be referred to each other, so that the descriptions thereof are omitted for brevity.
Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
The disclosed embodiments may be applied to electronic devices such as terminal devices, computer systems, servers, etc., which are operational with numerous other general purpose or special purpose computing system environments or configurations. Examples of well known terminal devices, computing systems, environments, and/or configurations that may be suitable for use with electronic devices, such as terminal devices, computer systems, servers, and the like, include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, hand-held or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network personal computers, small computer systems, mainframe computer systems, and distributed cloud computing environments that include any of the above, and the like.
Electronic devices such as terminal devices, computer systems, servers, etc. may be described in the general context of computer system-executable instructions, such as program modules, being executed by a computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc. that perform particular tasks or implement particular abstract data types. The computer system/server may be practiced in distributed cloud computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media including memory storage devices.
Summary of the disclosure
In the process of implementing the present disclosure, the inventors found that, in the simulation verification of a multi-core system, especially in the simulation verification of a heterogeneous multi-core system, a relevant verification engineer is usually required to develop corresponding makefile scripts for cores of different architectures to process the compiling work of the heterogeneous multi-core system, the makefile scripts are used to define a series of rules to specify a file needing to be compiled first, a file needing to be compiled later, a file needing to be recompiled, and the like, and a plurality of sets of makefile call logics are very complicated, so that the compiling efficiency is low, and further the verification work efficiency is low.
Brief description of the drawings
FIG. 1 is an exemplary application scenario of the compilation build methodology provided by the present disclosure.
In a chip verification scenario, for a multi-core system of a chip, with the compiling and building method provided by the present disclosure, a user may input a compiling task command list to a compiling and building device executing the method through a terminal or any other manner, where the compiling task command list includes a compiling task parameter corresponding to at least one processor core, the device may determine compiling task parameter information based on the compiling task command list, and further generate a compiling task rule file corresponding to the processor core based on the compiling task parameter information, where the compiling task rule file is similar to a makefile and is a script that defines a series of rules to specify a file that needs to be compiled first, a file that needs to be compiled later, a file that needs to be recompiled, and the like, and the compiling task rule file may be any implementable script file, for example, a compiling task rule script file generated by any organizing compiling tool library and a template tool library may be used to control a compiling process. For example, for some automated build tools, the present disclosure may be used to implement complex class makefiles instead of make, thereby generating a compilation task rule file. After the compiling task rule file corresponding to the processor core is generated, the compiling task rule file is operated based on the compiling class object corresponding to the processor core, an intermediate file corresponding to the processor core is generated, and then a target file corresponding to the processor core is generated based on the intermediate file, wherein the target file is at least one of an executable file (.so), a disassembler file (.as), a binary code file (.bin) and a hexadecimal code file (.hex) obtained by performing linking operation, decompiling operation, file analysis operation and the like on the intermediate file. The target file may be used for chip verification, which is illustrated as an example of verification of a multi-core system, where each processor core cluster corresponds to a core architecture, and each processor core cluster may include a plurality of processor cores of the architecture. Aiming at a multi-core system, the compiling task of each processor core is mutually independently processed and resource isolation is realized based on an object-oriented mode, and the compiling task rule file, the intermediate file and the target file which are respectively corresponding to each processor core can be generated aiming at each processor core according to the process, so that the automatic construction and compiling of the compiling task of the multi-core system are realized, the compiling efficiency is effectively improved, and the verification work efficiency is further improved. In practical applications, the multi-core system may further include other subsystems, such as a vision subsystem, a message network, and the like, which are not limited in this disclosure.
The compiling and constructing method provided by the disclosure is not only suitable for any chip verification scene, but also can realize automatic construction of a compiling task and further compile in any other scene needing compiling based on the compiling and constructing method provided by the disclosure, and the specific application scene can be set according to actual requirements, and the disclosure is not limited.
Exemplary method
Fig. 2 is a flowchart illustrating a compiling and building method according to an exemplary embodiment of the disclosure. The embodiment can be applied to electronic devices, such as a server and a terminal, as shown in fig. 2, and includes the following steps:
The compiling task parameter information may include project file information (such as a project file identifier and a position), a position of the compiling task (that is, under which directory, a work directory is located), a compiling main function position, compiled processor core information (such as a processor core architecture, a number, a type, and the like), and other related description information, and may further include simulation code use case information (such as a simulation code use case name), which may be specifically set according to actual requirements. The engineering file is a file describing engineering information of a target architecture platform of a multi-core system or a sub-system to be constructed, and may be, for example, a file based on another Markup Language (YAML Ain't Markup Language, which is abbreviated as YAML), and includes macro information, static library information, header file information, start assembly function information, and the like, and the engineering file needs to be prepared by a user according to an actual requirement of the user, and is not particularly limited. The compiling task parameter information may include compiling task parameters corresponding to one or more processor cores, and for the case that the compiling task parameters corresponding to multiple processor cores are included, the multiple processor cores may be homogeneous or heterogeneous, and are not limited specifically.
The compiling task parameter information can be prepared in advance by a user according to actual requirements, and is submitted to the compiling and constructing device in a certain mode when compiling and constructing are needed, and the compiling and constructing device can determine the compiling task parameter information according to the content submitted by the user. The specific submission mode of the user is not limited, and for example, the user may input the compilation task command list to the compilation building device.
The compiling task rule file is similar to makefile, and is a script that defines a series of rules to specify which files need to be compiled first, which files need to be compiled later, which files need to be compiled again, and the like, and the compiling task rule file can be any implementable script file, for example, a compiling task rule script file generated by organizing a compiling tool library and a template tool library based on any language can be used to control a compiling process. For example, for some automated build tools, the present disclosure is used to implement complex class makefiles instead of make, thereby automatically generating a compilation task rule file.
For example, classes for generating compilation task rule files corresponding to various processor cores can be created in advance based on an object-oriented factory model, when compilation construction is actually performed, objects corresponding to the processor cores are instantiated according to compilation task parameters corresponding to the processor cores, each processor core can instantiate a corresponding object, and the compilation task rule files corresponding to the processor cores are generated based on the objects corresponding to the processor cores independently, so that the compilation tasks of the processor cores are processed and isolated from resources independently.
The compiling object is also an object for instantiating the pre-created compiling class according to the compiling task parameter respectively corresponding to each processor core, and the compiling task of each processor core can correspond to an independent compiling object, so that the mutually independent processing and resource isolation of each processor core are realized. Running the compilation task rule file based on the compilation class object may be accessing member functions therein through the compilation class object, such as first executing an automation building tool function, running the compilation task rule file, and generating a corresponding intermediate file. The compiling task of a processor core corresponds to a project and can comprise one or more source files, wherein the source files refer to source language program files to be compiled, and after the compiling task rule files are run, each source file can correspondingly generate an intermediate file. For example, the compiling task rule file is run to generate an intermediate file, the intermediate file is a binary code file (. O), the representation mode may be different under different construction tools, and the disclosure is not limited.
And step 204, generating a target file corresponding to the processor core based on the intermediate file corresponding to the processor core.
The target file may be at least one of an executable file (. So), a disassembled file (. As), a binary code file (. Bin), and a hexadecimal code file (. Hex), and since the intermediate file includes an intermediate file corresponding to each source file, after the intermediate file is generated, the intermediate file needs to be subjected to a linking operation, a decompiling operation, a file analysis operation, and the like to obtain a corresponding executable file, a disassembled file, a binary code file, and a hexadecimal code file, and a specific compiling process principle is not described herein again.
The compiling and constructing method provided by the embodiment can automatically generate the compiling task rule file corresponding to each processor core and used for controlling compiling aiming at the isomorphic multi-core or the heterogeneous multi-core, further generate the corresponding intermediate files based on the compiling task rule files corresponding to the processor cores respectively, and generate the corresponding target files based on the intermediate files, so that the compiling work of the processor cores is realized, relevant personnel do not need to develop the corresponding makefile scripts aiming at the processor cores, the relevant workload is greatly reduced, and the compiling efficiency is effectively improved.
In an alternative example, fig. 3 is a flowchart of step 202 provided in an exemplary embodiment of the present disclosure, and in this example, step 202 may specifically include the following steps:
The configuration factory class object is an object determined by instantiating a pre-established configuration factory class based on compilation task parameter information, each type of processor core can have at least one corresponding configuration factory class, the configuration factory class can be a derivative subclass of a configuration Base class (configuration Base class), the configuration factory class comprises all members for processing a configuration file, an engineering file and a compilation task parameter of the processor core of the corresponding type and comprises member functions, member variables and the like, the configuration factory class performs deserialization on the compilation task parameter, the configuration file and the engineering file, and a constructor of the configuration Base class instantiates the member class in a factory mode according to the processor core type described by the compilation task parameter to generate the corresponding configuration factory class object. The processor core configuration file is a file for describing information of a cross tool chain of the processor core, such as a YAML file, the cross compilation is generated by compiling on an a machine and running on a B machine, the two machines can have different machine instructions, and the tool chain generally comprises a compiler, a linker, an interpreter, a debugger and the like. For example, in the embedded development process, there are roles of a host machine and a target machine, the host machine is a computer for executing compiling and linking embedded software, and the target machine is a hardware platform for running the embedded software. Thus, the tool chain information includes names of tools such as compiler, assembler, linker, disassembler, code conversion tool, etc., and associated parameter descriptions (e.g., descriptions of compilation parameters, link script files, etc.). A compiler is a program or tool that translates one language into another, such as a high-level language into a low-level language. A linker is a link to one or more intermediate files generated by a compiler or assembler, plus libraries, into an executable file. An intermediate file is a program that includes machine code and linker availability information. The link script is a reference file when a program is linked, and mainly aims to describe how to map segments (segments) in an input file into an output file and control the storage layout of the output file. The specific functional principles of the tools of the cross-compilation toolchain are not described in detail herein.
The factory mode is a design mode realized in an object-oriented language, belongs to a creation mode, provides an optimal mode for creating an object, does not expose creation logic to a client when the object is created in the factory mode, points to a newly created object by using a common interface, generally defines an interface for creating the object in the factory mode, and enables subclasses thereof to decide which factory class to instantiate, based on which, different factory class objects can be instantiated by compiling and constructing different processor cores, thereby realizing mutual independence and resource isolation among compiling tasks of different processor cores. The principles of a specific factory model are not described in detail herein.
The parameter configuration class object is obtained by calling member functions of the parameter configuration class object to execute a parameter analysis process based on the configuration factory class object, obtaining parameters such as tool chain information, engineering catalog information and source file information corresponding to the processor core, and packaging the obtained parameters such as the tool chain information, the engineering catalog information and the source file information. That is, parameters such as tool chain information, engineering catalog information, source file information and the like corresponding to a processor core are encapsulated in a parameter configuration class object corresponding to the processor core and are used for generating a compiling task rule file in a subsequent compiling preparation stage. The tool chain information can be obtained by reading a configuration file of a processor core, and the project directory information and the source file information can be obtained by reading a project file.
The generated factory class object is an object instantiated for generating a factory class based on the parameter information of the compilation task, similar to the configuration factory class, each type of processor core may have a corresponding generated factory class, the generated factory class may be a derivative subclass of a generated Base class (Generator Base class), and the generated factory class includes all member functions for generating an engineering directory of the corresponding processor core and a corresponding compilation task rule file (such as a script file under an automation building tool) according to the configuration parameters encapsulated in the parameter configuration class object. And instantiating the member class of the member constructor of the generation base class in a factory mode according to the type of the processor core described in the corresponding compiling task parameter to obtain a generation factory class object.
Because the generated factory class includes all member functions for generating the engineering catalog of the corresponding processor core and the corresponding compiling task rule file (such as a script file under an automatic construction tool) according to the configuration parameters encapsulated in the parameter configuration class object, after the generated factory class object is determined, the members can be accessed based on the generated factory class object, the establishment of the engineering catalog corresponding to the processor core is realized, and the corresponding compiling task rule file is generated under the engineering catalog.
Illustratively, the member function for generating the engineering catalog is accessed based on the generated factory class object, the member function is executed to create the engineering catalog corresponding to the processor core according to the engineering catalog information encapsulated in the parameter configuration class object, further, the symbolic link corresponding to the source file is created in the engineering catalog based on the engineering catalog information and the source file information corresponding to the processor core, and further, the corresponding compiling task rule file is generated in the engineering catalog according to the configuration parameters and the template file encapsulated in the parameter configuration class object. For example, the template file is a template generation file based on any implementable template engine rule, separation of execution content and the rule is realized, the template file is filled with configuration parameters encapsulated by the parameter configuration class object through the template engine, and a corresponding compiling task rule file is generated.
The object-oriented factory mode enables compilation construction to have better expandability, and when a user wants to compile and construct a new type of processor core, the user can conveniently derive factory classes corresponding to the new type of processor core through various factory base classes to support the compilation task of the new type of processor core, thereby greatly facilitating the work of related personnel and improving the working efficiency.
In an alternative example, fig. 4 is a flowchart of step 2021 provided by an exemplary embodiment of the present disclosure. In this example, the determining, based on the compiling task parameter information in step 2021, the configuration factory class object corresponding to the processor core includes:
at step 20211a, the type corresponding to the processor core is determined based on the compiling task parameter information.
The type corresponding to the processor core refers to a processor core architecture (or architecture) type, in the multi-core system, if all the processor cores have the same architecture, the multi-core system is called a homogeneous multi-core, and if a plurality of processor cores have different architectures, the multi-core system is called a heterogeneous multi-core. The compiling task parameter information comprises a compiling task parameter corresponding to at least one processor core, and the compiling task parameter corresponding to one processor core comprises the type and the number of the processor core and other related information, so that the type corresponding to each processor core can be determined based on the compiling task parameter information, and the number corresponding to each processor core and other related information can be determined.
At step 20212a, based on the type corresponding to the processor core, a configuration factory class object corresponding to the processor core is determined.
For heterogeneous multi-core, because the types of the processor cores are different, various factory class objects corresponding to the processor cores can be determined according to the types of the processor cores, such as configuring factory class objects, generating factory class objects, compiling factory class objects, and the like. Of course, the type and the number may also be combined to determine the corresponding configured plant class object, generate the plant class object, and compile the plant class object, which may be specifically set according to actual requirements. For example, for the compiling tasks of two processor cores belonging to type a and type B, at least one set of factory class a corresponding to type a (configuring factory class a, generating factory class a, compiling factory class a, etc.) is created in advance to support the compiling and constructing of type a, and at least one set of factory class B corresponding to type B is created to support the compiling and constructing of type B, when the compiling and constructing are needed, for the processor core compiling task of type a, a set of factory class a can be selected by default from the at least one set of factory class a according to the corresponding type a, or a set of factory class a can be determined to be instantiated by combining type a and a number specified by a user to determine a corresponding factory class object, where type B is the same as type a, and no further description is given here.
In an alternative example, fig. 5 is a flowchart of step 2021 provided by another exemplary embodiment of the present disclosure. In this example, the determining, based on the compiling task parameter information, the configuration factory class object corresponding to the processor core in step 2021 includes:
at step 20211b, based on the compiling task parameter information, the type and number corresponding to the processor core are determined.
At step 20212b, a configuration factory class object corresponding to the processor core is determined based on the type and number corresponding to the processor core.
For homogeneous multi-core, multiple sets of plant classes may be the same, and thus the type and number may be combined to determine which plant class to instantiate to determine the corresponding plant class object. For example, 8 configuration factory classes C supporting the same type of processor core (for example, type C) and corresponding 8 generation factory classes C and 8 compilation factory classes C are created, that is, the compilation task of each processor core has a set of factory classes (including configuration factory classes, generation factory classes, compilation factory classes, etc.) supporting implementation. The 8 sets of factory classes C are distinguished by numbers (such as 1-8), and when a user needs to perform compilation construction, for a compilation task of a processor core of the type C, the user can select which set of factory classes C is instantiated by the numbers to implement the compilation construction of the processor core. For example, the user may select number 2, and when there are a plurality of compiling tasks for the processor cores of type C, a number may be determined for each processor core. The method can be specifically set according to actual requirements.
In an optional example, for the same factory class, different processing modes can be further subdivided according to actual requirements to meet different compiling requirements of a user on the same processor core, and the specific subdivision can be set according to the actual requirements, which is not limited in the disclosure. For example, for the same factory class, different compiling task rule files can be generated through different member functions, and then different target files are generated. By realizing a finer-grained processing mode, the user experience can be effectively improved.
In an alternative example, fig. 6 is a flowchart of step 203 provided by an exemplary embodiment of the present disclosure. In this example, the step 203 runs the compiling task rule file based on the compiling class object corresponding to the processor core to generate an intermediate file corresponding to the processor core, and includes:
The compiling factory class object is a compiling class object instantiated based on a factory mode, similar to the configuration factory class object, at least one corresponding compiling factory class can be created for each type of processor core, the compiling factory class can be a derivative subclass of a compiling Base class (Compiler Base class), all member functions describing compiling and constructing behaviors of the corresponding type of processor core are contained in the compiling factory class, the member constructing functions of the compiling Base class instantiate the member class in the factory mode according to the type and the number of the processor core described by the compiling task parameters, and the compiling factory class object corresponding to the processor core is determined.
Illustratively, based on the compiling factory class object corresponding to the processor core, the tool function is executed first, the compiling task rule file is run, and the corresponding intermediate file is generated.
The compiling factory class object instantiated based on the factory mode runs the compiling task rule file to generate the corresponding intermediate file, and the mutually independent processing and resource isolation of the core compiling tasks of the processors in the compiling stage are realized.
In an alternative example, fig. 7 is a flowchart of step 2022 provided by an exemplary embodiment of the present disclosure. In this example, the determining, based on the configuration factory class object, the parameter configuration class object corresponding to the processor core in step 2022 includes:
The tool chain information corresponding to the processor core includes names of tools such as a compiler, an assembler, a connector, a disassembler, a code conversion tool, and the like, and descriptions of related parameters, such as descriptions of a compiling parameter, a link script file, and the like. The engineering catalog information comprises engineering catalog related information which needs to be created under a use case simulation target for executing the compiling task. The source file information is information related to a source program file to be compiled, and includes information such as a source file name, a location, and the like. The tool chain information may be obtained by reading a configuration file corresponding to a processor core through a configuration factory class object, where the configuration file is a file used to describe cross tool chain information of the processor core, such as a configuration file of YAML, the configuration file is prepared in advance for the processor core, and different types of processor cores correspond to different configuration files. YAML is a recursive abbreviation for "YAML Ain's a Markup Language" (YAML is not a Markup Language). In developing this language, YAML means that: "Yet Another Markup Language" (again, a Markup Language). YAML is similar in syntax to other high-level languages and may simply express data forms such as lists, hash tables, scalars, and the like. It uses space indentation and a number of appearance-dependent features that are particularly well-suited for expressing or editing data structures, various profiles, typographic debug content, file schemas (e.g., many email header formats are in close proximity to YAML). The profile suffix for YAML is. yml, such as runoob. The method is specifically set according to actual requirements. The project catalog information and the source file information may be obtained by configuring a factory class object to read the project file. The engineering file is a file describing engineering information of a target architecture platform of the multi-core system or subsystem to be built, such as an engineering file which may be YAML. The engineering files comprise macro information, static library information, header file information, starting assembly function information and the like, and the engineering files need to be prepared by users according to the actual requirements of compiling and constructing the engineering.
Specifically, the tool chain information, the engineering catalog information and the source file information corresponding to the processor core are packaged into a parameter configuration class object, so that the subsequent flow can be conveniently called, and the parameter configuration class object is used for generating a compiling task rule file.
In an alternative example, fig. 8 is a schematic flow chart of step 2024 provided by an exemplary embodiment of the present disclosure. In this example, the step 2024 of generating the compiling task rule file corresponding to the processor core based on the generating the factory class object and the parameter configuration class object includes:
step 20241, create an engineering catalog corresponding to the processor core based on the generated factory class object.
And generating a factory class object, calling a member function used for creating the engineering catalog according to the type and the number of the processor core, adding and constructing the independent engineering catalog under the catalog for executing the compilation according to the compiling task of the processor core. For example, in a verification scene, an independent engineering catalog is added and constructed under the use case simulation catalog.
Illustratively, the code that creates the engineering catalog is as follows:
[lisan@login03 HVBS]$cd RI5CY_0
BOOTFILES DIR3 obj SConscript.RI5CY_0tc.c
The symbolic link is a soft link, and is a special file, which contains a reference pointing to other files or directories in the form of an absolute path or a relative path, the operation of the symbolic link is transparent, and the program reading and writing the symbolic link file can be represented as directly operating a destination file (i.e., a source file in the present disclosure) corresponding to the symbolic link file. Some programs that require special handling of symbolic links (e.g., backup programs) may recognize and directly operate on them, where a symbolic link file contains only one text string that is interpreted by the operating system as a path to another file (destination) or directory. It is a stand-alone file whose existence is not dependent on the destination. If a symbolic link is deleted, the destination to which it points is unaffected. If the destination file is moved, renamed or deleted, any symbolic links to it still exist, but they will point to a file that does not exist anymore. The creation principle of the specific symbolic link is not described in detail.
The template file is a template generation file based on any implementable template engine rule, and separation of execution content and the rule is realized. The parameters are provided through the parameter configuration class object, and the corresponding compiling task rule file can be generated by performing parameter filling processing on the template file according to the preset filling rule. The template file may be filled with configuration parameters encapsulated by the parameter configuration class object through the template engine. The template engine is created to separate the user interface from the business data (content), which can generate documents in a specific format.
Illustratively, after creating a symbolic link of a source file in an engineering directory, a template engine is started, and a compiling task rule file corresponding to each source file is generated in the engineering directory according to parameters encapsulated in a parameter configuration class object.
The compiling task rule file generation method and the compiling task rule generation system based on the combination of the parameter configuration class object and the template file effectively achieve automatic generation of the compiling task rule file, greatly reduce development workload of related workers and further improve compiling efficiency.
Fig. 9 is a flowchart illustrating a compilation building method according to another exemplary embodiment of the present disclosure.
In an alternative example, in this example, the generating, based on the intermediate file corresponding to the processor core, the target file corresponding to the processor core in step 204 includes:
Specifically, the intermediate file may be linked by calling a linker in the compiling tool chain through the compiling object or the compiling factory object, so as to obtain a corresponding executable file, and the principle of the specific linking operation is not described in detail.
Specifically, the decompiling tool in the compiling tool chain may be called by the compiling object or the compiling factory object to perform decompiling operation on the executable file, so as to obtain a corresponding decompiled file, which is no longer described in detail in specific principles.
Specifically, a file analysis tool in a compiling tool chain may be called to perform file analysis operation on the executable file through the compiling class object or the compiling factory class object, so as to obtain a corresponding binary code file and/or hexadecimal code file, which is not described in detail in the specific principle.
For example, an executable file, a disassembly file, a binary code file and a hexadecimal code file can be used as the target file, and the target file can be specifically set according to actual requirements.
In an optional example, for implementation of the compiling and building method of the present disclosure, in a specific application scenario, before step 201, symbolic links of the compiling task rule file of the compiling and building apparatus of the present disclosure need to be created under a directory (such as a simulation tool directory) for performing compiling according to requirements of an automated building tool, so as to perform asynchronous path compiling organization work, and implement mutually independent processing and resource isolation between compiling tasks of processor cores of a multi-core heterogeneous system. For different automated building tools, the generated compiling task rule file may include one or more levels of rule files, and is not limited specifically.
In one optional example, the method of the present disclosure further comprises:
When a user needs to add support for compiling and constructing a new type of processor core, relevant files or data can be prepared according to content which needs to be prepared in advance according to the requirement of the new type of processor core in the content, for example, a set of factory classes (configuration factory class, generation factory class, compilation factory class) corresponding to the new type is created, and the set of factory classes can be derived and obtained through corresponding base classes, so that the development work of the user is relatively less, and for example, a configuration file corresponding to the new type is prepared for describing relevant information of a cross-compiling tool chain corresponding to the new type, a template file corresponding to the new type, and the like, which can be specifically set according to actual requirements. After the user is ready, the new type of support content can be registered through a terminal or other means, so that the compiling and building device can support the compiling task of the new type of processor core. The factory class registration request may include the content that needs to be prepared by the user, and is not limited to the factory class information, and may be specifically set according to actual requirements.
After receiving a factory class registration request of a user, the factory class registration request may be responded to the user, and information of each factory class of the user is registered, for example, a configured factory class, a generated factory class, and a compiled factory class are respectively added to corresponding locations, and a configuration file is stored in the corresponding location, so that the functions of the processing flow described above can be implemented in subsequent applications. The specific registration operation may be set according to actual requirements, and the disclosure is not limited.
The method and the system have the advantages that the novel type registration function is provided for the user, the expandability of compiling construction is realized, the work of developers is further facilitated, and the work efficiency is further improved.
In an alternative example, the determining of step 201 compiles task parameter information, including:
in step 2011, a list of compiling task parameters in the form of a character string is obtained.
Specifically, the compiling task parameter list prepared by the user may be a dictionary data structure, which is built in a dictionary form by taking the processor core as a unit, for example, a dictionary form of any automatic building tool, compiling task parameters of each specified processor core are packaged into an independent dictionary data structure, the independent dictionary data structure is input into the compiling and building device in a command line parameter form of the automatic building tool script, when the command line parameter form is input, the dictionary data structure is transmitted into the compiling and building device in a character string form, the dictionary data structures of the plurality of core compiling tasks are independent from each other, and the compiling and building device obtains the compiling and building device, that is, the compiling and task parameter list in the character string form.
Optionally, after the compiling and constructing device obtains the compiling task parameter list, the symbolic link of the compiling task rule file needs to be created in the simulation tool directory according to the requirement of the automatic constructing tool, so as to facilitate the subsequent execution of asynchronous path compiling and constructing work.
And the deserialization is to change the compiling task parameter list in the form of character strings into a dictionary data structure again.
For example, after the compiling and building device receives a compiling task parameter list in a character string form transmitted from the outside, deserialization of character string information is started first, the compiling task parameter list in the character string form is changed into a dictionary data structure again, a plurality of compiling tasks (each processor core corresponds to one compiling task) exist in a list form, and a list member is the dictionary data structure describing compiling task parameters of each processor core. And the compiling and constructing device sequentially extracts all dictionaries from the list and respectively enters the subsequent processing flow. Each compiling task corresponds to an independent object, so that resource isolation of different compiling task working environments is realized.
Any of the above-described embodiments or alternative examples of the disclosure may be implemented alone, or in any combination without conflict, and the disclosure is not limited.
In an optional example, fig. 10 is a flowchart of a compiling and building method according to still another exemplary embodiment of the disclosure, and in this example, taking a simulation case of a Verification scenario as an example, a compiling and building device that executes the compiling and building method of the disclosure is abbreviated as HVBS (Horizon Verification structured System), where the compiling and building method specifically includes:
1. an HVBS compilation task parameter list is prepared.
2. And creating symbolic link of the compiling task rule file of the HVBS under the simulation use case directory.
3. A list of compilation task parameters in the form of a string is passed in to the HVBS.
4. The HVBS performs deserialization of the compilation task parameter list in string form.
5. Processor core information is obtained from a set of compilation task parameters.
The processor core information can be set as a type or a type and a number according to actual requirements. A set of compilation task parameters refers to parameters corresponding to a compilation task, i.e., parameters corresponding to a processor core.
6. And determining the configuration factory class object according to the processor core information.
7. And reading the configuration file based on the configuration factory class object to obtain compiling tool chain information.
Illustratively, the configuration files are structured in the YAML language format. The HVBS uses a config (configuration) file based on the yaml format to define the compilation related configuration of a specific processor architecture, where the inheritance of information is achieved with the anchor and alias functions of yaml. In the config file, a Tag (TAGS) node is used as a basic unit for organizing the compiling parameter group, and the tag node can contain information such as tool chains, calling library directories, macro definitions, compiling parameters, link scripts, assembling startup files and the like. And default BASE (without definition) labels are provided in the config file, so that a user is supported to add a new label container, and the newly defined labels can acquire information of any level node container defined in the config table in an inheritance manner. The configuration files are semi-fixed configuration and are used for adding a new processor architecture or expanding compilation information of an existing architecture, and all the configuration files can be located under an HVBS/config directory and can be specifically set according to actual requirements.
8. And reading the engineering file based on the configuration factory class object to obtain engineering directory information and source file information.
Illustratively, the project files are formed according to the YAML language format, the project files define the YAML configuration table of the project information for the user, and the user can define the source files, the header function files, the assembly start functions, the static libraries, the macro definitions and other related information in the project files. The project file may be transmitted to the HVBS by way of command line parameters. Similarly, the user can use the anchor point characteristic in the yaml format in the engineering file to realize information inheritance for part of the layout.
9. And packaging the obtained compiling tool chain information, the engineering catalog information and the source file information into a parameter configuration class object based on the configuration factory class object.
10. Whether there are other compilation tasks. And if so, returning to the step 5, and continuing the processing of the next compiling task until all compiling tasks in the compiling task parameter list are completed, otherwise, continuing the step 11.
11. And determining to generate the factory class object according to the processor core information.
And for each compiling task, determining a corresponding generated factory class object according to the processor core information of the compiling task.
12. An engineering catalog is created under the name "processor core architecture _ number" based on generating the factory class object.
13. And creating symbolic links of the source files under the engineering catalog according to the source file information and the engineering catalog information based on the generated factory class objects.
14. And starting a template engine to generate a compiling task rule file under the engineering catalog based on the generated factory class object according to the configuration parameters encapsulated by the parameter configuration class object.
15. Whether there are other compilation tasks. If yes, returning to the step 11 to continue processing the next compiling task; if not, continue to step 16.
16. And determining to compile the factory class object according to the processor core information.
This step is also to determine the compilation factory class object for the processor core information of each compilation task.
17. And starting the corresponding compiling task rule file in the corresponding engineering catalogue based on the compiling factory class object to generate a corresponding intermediate file.
18. And executing the link operation based on the compiled factory class object to generate a corresponding executable file.
19. And calling a disassembling tool to generate a disassembling file based on the compiled factory class object.
20. And calling a file analysis tool to generate a corresponding binary file or hexadecimal file based on the compiled factory class object.
21. Whether there are other compilation tasks. If so, the process returns to step 16 to continue the next compilation task, otherwise, the process continues to step 22.
22. The HVBS is ended.
The specific operations of the steps 1-22 are referred to the above, and are not described in detail herein.
Optionally, the workflow of the above steps can be summarized into three phases including a parameter parsing phase, a compilation preparation phase and a compilation operation phase. The parameter parsing phase may include the processing phase of steps 5-9 described above, the compilation preparation phase may include the processing phase of steps 11-14 described above, and the compilation operation phase may include the processing phase of steps 16-20. For a plurality of compiling tasks of the multi-core system, each stage needs to finish processing all the compiling tasks and then enters the next stage, and the setting can be specifically set according to actual requirements.
The HVBS supports multi-architecture multi-core combined compilation in a simulation process, each group of param parameter dictionary character strings transmitted to the HVBS represents a compilation task of a core (namely a processor core), a configuration factory class, a generation factory class and a compilation factory class of each compilation task are independent objects, so that the process of the compilation task and the isolation of resources are realized, meanwhile, each compilation task can independently specify an engineering file to compile and construct aiming at different source files, and the compilation tasks of each core are respectively positioned in independent engineering folders in the process of compilation results, so the HVBS can adapt to the requirements of various compilation tasks such as heterogeneous multi-cores, homogeneous multi-cores, AMPs (asymmetric multi-processes), SMPs (symmetric multi-processes) and the like.
The HVBS of the present disclosure is based on an object-oriented inheritance mode, wherein various types are constructed based on an object-oriented factory mode, and each type can derive different work subclasses according to different architectures, so that independent compiling process flows can be defined for different architectures. Each type can define a Base class, for example, a compilation class exists, a basic class Compiler Base (compilation Base class) exists, in a static member _ pool of a life class in the class, in a structure function of the class, a subclass (for example, a compilation factory class) prototype is stored in a static member list of a parent class (compilation Base class) through initial construction, a corresponding correct subclass object can be determined through relevant information (architecture, type, number and the like) of a processor core, and if the subclass object cannot be determined through the relevant information of the processor core, the parent class structure object can be used by default, and the setting can be specifically performed according to actual requirements. Based on the method, a user can register or add the class corresponding to the corresponding processor core type in each module by using the inheritance characteristics of the class and rewrite the corresponding constructors, and the function names except the called functions can rename and redefine the flow. The initial instantiation of the new extension class may be done automatically by the HVBS at the time of invocation, and the user needs to pay attention to the newly defined class to follow the name specification of the existing subclass.
Illustratively, the HVBS overall software scheme of the present disclosure may be implemented based on any implementable language, for example, may be implemented based on secondary development of an automated construction tool of any language, and automatically generate a specific compilation task rule file using any implementable template engine, and the configuration tables such as the project file and the configuration file adopt the yaml table.
Any of the compilation construction methods provided by the embodiments of the present disclosure may be performed by any suitable device having data processing capabilities, including but not limited to: terminal equipment, a server and the like. Alternatively, any of the compilation building methods provided by the embodiments of the present disclosure may be executed by a processor, such as the processor executing any of the compilation building methods mentioned by the embodiments of the present disclosure by calling corresponding instructions stored in a memory. Which will not be described in detail below.
Exemplary devices
Fig. 11 is a schematic structural diagram of a compilation building apparatus according to an exemplary embodiment of the present disclosure. The apparatus of this embodiment may be used to implement the corresponding method embodiment of the present disclosure, and the apparatus shown in fig. 11 includes: a first determination module 501, a first processing module 502, a second processing module 503, and a third processing module 504.
A first determining module 501, configured to determine compiling task parameter information, where the compiling task parameter information includes a compiling task parameter corresponding to at least one processor core; a first processing module 502, configured to generate a compilation task rule file corresponding to a processor core based on the compilation task parameter information determined by the first determining module 501; the second processing module 503 is configured to run the compiling task rule file generated by the first processing module 502 based on the compiling class object corresponding to the processor core, and generate an intermediate file corresponding to the processor core; the third processing module 504 is configured to generate a target file corresponding to the processor core based on the intermediate file corresponding to the processor core generated by the second processing module 503.
In an alternative example, fig. 12 is a schematic structural diagram of a first processing module 502 according to an exemplary embodiment of the present disclosure. In this example, the first processing module 502 includes: a first determining unit 5021, a second determining unit 5022, a third determining unit 5023 and a first generating unit 5024.
A first determining unit 5021, configured to determine a configuration factory class object corresponding to a processor core based on the compiling task parameter information determined by the first determining module 501; a second determining unit 5022, configured to determine a parameter configuration class object corresponding to the processor core based on the configuration factory class object determined by the first determining unit 5021; a third determining unit 5023, configured to determine, based on the compiling task parameter information determined by the first determining module 501, a generated factory class object corresponding to the processor core; the first generating unit 5024 is configured to generate a compiling task rule file corresponding to the processor core based on the generated factory class object determined by the third determining unit 5023 and the parameter configuration class object determined by the second determining unit 5022.
In an alternative example, fig. 13 is a schematic structural diagram of the first determining unit 5021 provided in an exemplary embodiment of the present disclosure. In this example, the first determination unit 5021 includes: a first determining subunit 50211a and a second determining subunit 50212a.
The first determining subunit 50211a is configured to determine a type corresponding to a processor core based on the compiling task parameter information; a second determining subunit 50212a is configured to determine a configuration factory class object corresponding to the processor core based on the type corresponding to the processor core.
In an alternative example, fig. 14 is a schematic structural diagram of the first determining unit 5021 provided in another exemplary embodiment of the present disclosure. In this example, the first determination unit 5021 includes: a third determining subunit 50211b and a fourth determining subunit 50212b.
A third determining subunit 50211b, configured to determine a type and a number corresponding to a processor core based on the compiling task parameter information; a fourth determining subunit 50212b is configured to determine a configuration factory class object corresponding to the processor core based on the type and the number corresponding to the processor core.
In an alternative example, fig. 15 is a schematic structural diagram of the second processing module 503 according to an exemplary embodiment of the disclosure. In this example, the second processing module 503 includes: a first processing unit 5031 and a second processing unit 5032.
A first processing unit 5031, configured to determine, based on the type and the number corresponding to the processor core, a compiled factory class object corresponding to the processor core; the second processing unit 5032 is configured to run the compiling task rule file based on the compiling factory class object corresponding to the processor core determined by the first processing unit 5031, and generate an intermediate file corresponding to the processor core.
In an alternative example, fig. 16 is a schematic structural diagram of the second determining unit 5022 provided in an exemplary embodiment of the present disclosure. In this example, the second determining unit 5022 includes: a first acquisition subunit 50221 and a packaging subunit 50222.
A first obtaining subunit 50221, configured to obtain tool chain information, engineering catalog information and source file information corresponding to the processor core based on the configuration factory class object; the encapsulating subunit 50222 is configured to encapsulate the tool chain information, the engineering catalog information, and the source file information corresponding to the processor core acquired by the first acquiring subunit 50221, and acquire a parameter configuration class object corresponding to the processor core.
In an alternative example, fig. 17 is a schematic structural diagram of the first generating unit 5024 provided in an exemplary embodiment of the present disclosure. In this example, the first generating unit 5024 includes: a first creating subunit 50241, a second creating subunit 50242, and a generating subunit 50243.
A first creating subunit 50241, configured to create an engineering directory corresponding to the processor core based on the generated factory class object; a second creating subunit 50242, configured to create a symbolic link of a source file corresponding to the processor core under the engineering directory based on the engineering directory information and the source file information corresponding to the processor core; the generating subunit 50243 is configured to generate a compiling task rule file corresponding to the processor core in the engineering directory according to the parameter configuration class object and the corresponding template file.
In an alternative example, fig. 18 is a schematic structural diagram of a third processing module 504 according to an exemplary embodiment of the disclosure. In this example, the third processing module 504 includes: a linking unit 5041, a decompiling unit 5042, an analyzing unit 5043, and a third processing unit 5044.
A link unit 5041, configured to perform a link operation on the intermediate file to obtain an executable file corresponding to the processor core; a decompiling unit 5042, configured to perform decompiling operation on the executable file to obtain a corresponding decompiled file; the analysis unit 5043 is configured to perform file analysis operation on the executable file to obtain a corresponding binary code file and/or hexadecimal code file; a third processing unit 5044, configured to take at least one of an executable file, a disassembled file, a binary file, and a hexadecimal file as a target file.
In an alternative example, fig. 19 is a schematic structural diagram of a compiling and building device according to another exemplary embodiment of the disclosure. In this example, the apparatus of the present disclosure further comprises: a receiving module 505 and a fourth processing module 506.
A receiving module 505, configured to receive a factory class registration request of a user, where the factory class registration request includes information of each factory class to be added by the user and used for supporting compilation and construction of a processor core of a new type; and a fourth processing module 506, configured to register information of each plant class of the user in response to the plant class registration request.
In an alternative example, fig. 20 is a schematic structural diagram of the first determining module 501 provided in an exemplary embodiment of the present disclosure. In this example, the first determining module 501 includes: an acquisition unit 5011 and a fourth processing unit 5012.
An obtaining unit 5011, configured to obtain a compiling task parameter list in a character string form; the fourth processing unit 5012 is configured to perform deserialization on the compiling task parameter list to obtain a dictionary data structure corresponding to at least one processor core, where the dictionary data structure is used as the compiling task parameter information.
In an alternative example, the compiling and building device of the present disclosure may also perform functional module division in other manners, and fig. 21 is a schematic structural diagram of a compiling and building device provided in yet another exemplary embodiment of the present disclosure. In this example, the compiling and building apparatus of the present disclosure may include a configuration module, a generation module, and a compiling module, where the configuration module is configured to execute a flow of a parameter parsing phase and generate a parameter configuration class object; the generating module is used for executing the flow of the compiling preparation stage and generating a compiling task rule file, and the compiling module is used for executing the flow of the compiling operation stage and generating a target file. For the operation of each module, reference is made to the foregoing description, and details are not repeated here.
In an optional example, taking a chip Verification scenario as an example, the HVBS (horizontal Verification Build System) of the present disclosure may include, by function, a Configuration module (composed of a series of classes such as Configuration Base class and its derived subclasses), a generation module (composed of a series of python classes such as Generator Base class and its derived subclasses), a compilation module (composed of a series of python classes such as Compiler Base class and its derived subclasses), a Configuration file (Configuration YAML), a Project YAML, a module library file (i.e., a template file), and a shell program containing a compilation task rule file. Each functional module is developed secondarily by using an automatic construction tool based on any implementable language, a template engine is used for automatically generating a specific compiling task rule file, and configuration tables such as engineering files and configuration files are yaml tables. The HVBS of this example also includes a shell program containing the compilation task rule file, which is a top-level file for organizing the compilation task workflow, and the compilation task rule file needs to generate symbolic links in the working directory of the simulation use case according to the requirements of the automated building tool on executing off-site compilation of the project. And generating a corresponding intermediate file based on a compiling task rule file generated by running an automatic construction tool, and further obtaining target files (. Bin,. Hex,. As,. So) through link operation, disassembling operation and file analysis operation, wherein the target files are used for verifying the chip system or the subsystem.
Exemplary electronic device
An embodiment of the present disclosure further provides an electronic device, including: a memory for storing a computer program;
a processor for executing the computer program stored in the memory, and the computer program, when executed, implements the method of any of the above embodiments of the present disclosure.
Fig. 22 is a schematic structural diagram of an application embodiment of the electronic device of the present disclosure. In this embodiment, the electronic device 10 includes one or more processors 11 and a memory 12.
The processor 11 may be a Central Processing Unit (CPU) or other form of processing unit having data processing capabilities and/or instruction execution capabilities, and may control other components in the electronic device 10 to perform desired functions.
Memory 12 may include one or more computer program products that may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. The volatile memory may include, for example, random Access Memory (RAM), cache memory (cache), and/or the like. The non-volatile memory may include, for example, read Only Memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium and executed by processor 11 to implement the methods of the various embodiments of the disclosure described above and/or other desired functionality. Various content such as an input signal, signal components, noise components, etc. may also be stored in the computer readable storage medium.
In one example, the electronic device 10 may further include: an input device 13 and an output device 14, which are interconnected by a bus system and/or other form of connection mechanism (not shown).
The input means 13 may be, for example, a microphone or a microphone array as described above for capturing an input signal of a sound source.
The input device 13 may also include, for example, a keyboard, a mouse, and the like.
The output device 14 may output various information including the determined distance information, direction information, and the like to the outside. The output devices 14 may include, for example, a display, speakers, a printer, and a communication network and its connected remote output devices, among others.
Of course, for simplicity, only some of the components of the electronic device 10 relevant to the present disclosure are shown in fig. 22, omitting components such as buses, input/output interfaces, and the like. In addition, the electronic device 10 may include any other suitable components depending on the particular application.
Exemplary computer program product and computer-readable storage Medium
In addition to the methods and apparatus described above, embodiments of the present disclosure may also be a computer program product comprising computer program instructions that, when executed by a processor, cause the processor to perform steps in methods according to various embodiments of the present disclosure as described in the "exemplary methods" section of this specification above.
The computer program product may write program code for carrying out operations for embodiments of the present disclosure in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server.
Furthermore, embodiments of the present disclosure may also be a computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, cause the processor to perform steps in a method according to various embodiments of the present disclosure as described in the "exemplary methods" section above of this specification.
The computer-readable storage medium may take any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may include, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
The foregoing describes the general principles of the present disclosure in conjunction with specific embodiments, however, it is noted that the advantages, effects, etc. mentioned in the present disclosure are merely examples and are not limiting, and they should not be considered essential to the various embodiments of the present disclosure. Furthermore, the foregoing disclosure of specific details is for the purpose of illustration and description and is not intended to be limiting, since the disclosure is not intended to be limited to the specific details so described.
In the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts in the embodiments are referred to each other. For the system embodiment, since it basically corresponds to the method embodiment, the description is relatively simple, and reference may be made to the partial description of the method embodiment for relevant points.
The block diagrams of devices, apparatuses, devices, systems involved in the present disclosure are only given as illustrative examples and are not intended to require or imply that the connections, arrangements, configurations must be made in the manner shown in the block diagrams. These devices, apparatuses, devices, systems may be connected, arranged, configured in any manner, as will be appreciated by one skilled in the art. Words such as "including," "comprising," "having," and the like are open-ended words that mean "including, but not limited to," and are used interchangeably herein. The words "or" and "as used herein mean, and are used interchangeably with, the word" and/or, "unless the context clearly dictates otherwise. The word "such as" is used herein to mean, and is used interchangeably with, the phrase "such as but not limited to".
The methods and apparatus of the present disclosure may be implemented in a number of ways. For example, the methods and apparatus of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order for the steps of the method is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above unless specifically stated otherwise. Further, in some embodiments, the present disclosure may also be embodied as programs recorded in a recording medium, the programs including machine-readable instructions for implementing the methods according to the present disclosure. Thus, the present disclosure also covers a recording medium storing a program for executing the method according to the present disclosure.
It is also noted that in the devices, apparatuses, and methods of the present disclosure, each component or step can be decomposed and/or recombined. These decompositions and/or recombinations are to be considered equivalents of the present disclosure.
The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The foregoing description has been presented for purposes of illustration and description. Furthermore, this description is not intended to limit embodiments of the disclosure to the form disclosed herein. While a number of example aspects and embodiments have been discussed above, those of skill in the art will recognize certain variations, modifications, alterations, additions and sub-combinations thereof.
Claims (13)
1. A compilation build method comprising:
determining compiling task parameter information, wherein the compiling task parameter information comprises compiling task parameters corresponding to at least one processor core;
generating a compiling task rule file corresponding to the processor core based on the compiling task parameter information;
running the compiling task rule file based on the compiling class object corresponding to the processor core to generate an intermediate file corresponding to the processor core;
and generating a target file corresponding to the processor core based on the intermediate file corresponding to the processor core.
2. The method of claim 1, wherein the generating a compilation task rule file corresponding to the processor core based on the compilation task parameter information comprises:
determining a configuration factory class object corresponding to the processor core based on the compiling task parameter information;
determining a parameter configuration class object corresponding to the processor core based on the configuration factory class object;
determining a generated factory class object corresponding to the processor core based on the compiling task parameter information;
and generating the compiling task rule file corresponding to the processor core based on the generated factory class object and the parameter configuration class object.
3. The method of claim 2, wherein the determining a configuration factory class object corresponding to the processor core based on the compilation task parameter information comprises:
determining a type corresponding to the processor core based on the compiling task parameter information;
and determining a configuration factory class object corresponding to the processor core based on the type corresponding to the processor core.
4. The method of claim 2, wherein the determining a configuration factory class object corresponding to the processor core based on the compilation task parameter information comprises:
determining the type and the number corresponding to the processor core based on the compiling task parameter information;
and determining the configuration factory class object corresponding to the processor core based on the type and the number corresponding to the processor core.
5. The method of claim 4, wherein the running the compilation task rule file based on the compilation class object corresponding to the processor core to generate an intermediate file corresponding to the processor core comprises:
determining a compiling factory class object corresponding to the processor core based on the type and the number corresponding to the processor core;
and running the compiling task rule file based on the compiling factory class object corresponding to the processor core to generate the intermediate file corresponding to the processor core.
6. The method of claim 2, wherein the determining a parameter configuration class object corresponding to the processor core based on the configuration factory class object comprises:
acquiring tool chain information, engineering catalog information and source file information corresponding to the processor core based on the configuration factory class object;
and packaging the tool chain information, the engineering catalog information and the source file information corresponding to the processor core to obtain the parameter configuration class object corresponding to the processor core.
7. The method of claim 6, wherein generating the compilation task rule file corresponding to the processor core based on the generated factory class object and the parameter configuration class object comprises:
creating an engineering catalog corresponding to the processor core based on the generated factory class object;
creating symbolic links of source files corresponding to the processor cores under the engineering directories based on the engineering directory information and the source file information corresponding to the processor cores;
and generating the compiling task rule file corresponding to the processor core under the project directory according to the parameter configuration class object and the corresponding template file.
8. The method of claim 1, wherein the generating a target file corresponding to the processor core based on the intermediate file corresponding to the processor core comprises:
performing link operation on the intermediate file to obtain an executable file corresponding to the processor core;
performing decompiling operation on the executable file to obtain a corresponding disassembled file;
performing file analysis operation on the executable file to obtain a corresponding binary code file and/or a corresponding hexadecimal code file;
and taking at least one of the executable file, the disassembled file, the binary code file and the hexadecimal code file as the target file.
9. The method of claim 1, further comprising:
receiving a factory class registration request of a user, wherein the factory class registration request comprises each factory class information to be added by the user and used for supporting compiling and constructing of a processor core of a new type;
and responding to the factory class registration request, and registering each piece of factory class information of the user.
10. The method of any of claims 1-9, wherein the determining compilation task parameter information comprises:
acquiring a compiling task parameter list in a character string form;
and deserializing the compiling task parameter list to obtain a dictionary data structure corresponding to at least one processor core as the compiling task parameter information.
11. A compilation build apparatus comprising:
the device comprises a first determining module, a second determining module and a third determining module, wherein the first determining module is used for determining compiling task parameter information, and the compiling task parameter information comprises compiling task parameters corresponding to at least one processor core;
the first processing module is used for generating a compiling task rule file corresponding to the processor core based on the compiling task parameter information;
the second processing module is used for running the compiling task rule file based on the compiling class object corresponding to the processor core and generating an intermediate file corresponding to the processor core;
and the third processing module is used for generating a target file corresponding to the processor core based on the intermediate file corresponding to the processor core.
12. A computer-readable storage medium storing a computer program for executing the compilation construction method of any one of claims 1-10.
13. An electronic device, the electronic device comprising:
a processor;
a memory for storing the processor-executable instructions;
the processor is configured to read the executable instructions from the memory and execute the instructions to implement the compile construction method according to any one of claims 1 to 10.
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| CN116450250A (en) * | 2023-06-16 | 2023-07-18 | 天津金城银行股份有限公司 | Dynamic scenario execution method, system and storage medium |
| CN116450250B (en) * | 2023-06-16 | 2023-09-19 | 天津金城银行股份有限公司 | Dynamic scenario execution method, system and storage medium |
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