CN115379069A - Image data acquisition and transmission method and system with LVDS sampling clock phase self-calibration function - Google Patents
Image data acquisition and transmission method and system with LVDS sampling clock phase self-calibration function Download PDFInfo
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Abstract
The invention relates to an image data acquisition and transmission method with LVDS sampling clock phase self-calibration, which comprises the following steps: the FPGA chip configures a register in the image acquisition equipment through an SPI interface; a CIS of the image acquisition equipment acquires image data and transmits the image data to the LVDS interface, and the image data output by the LVDS interface is subjected to automatic phase adjustment through a clock phase calibration unit; parallel data in the five data channels completing the clock phase adjustment are transmitted to a virtual BRAM of the FPGA chip for caching; according to the method, the clock phase of each image data is calibrated and then the image data is transmitted to the storage area for storage, so that the offset between a sampling clock and the sampling data can be avoided, and the stability and the accuracy of the sampling data are ensured; and the transmission rate of the data after the clock phase adjustment can reach 175MB/s, so that a large amount of image information can be transmitted in real time, and the timeliness of data transmission is ensured.
Description
Technical Field
The invention relates to the technical field of image data processing, in particular to an image data acquisition and transmission method and system with LVDS sampling clock phase self-calibration.
Background
In recent years, image acquisition and transmission systems have been widely used in various fields such as industry, military, medicine, etc., for example, face recognition, remote monitoring, video telephone, etc. The image is acquired in many ways, and a camera is usually used to acquire the image in real time. In the image data acquisition and transmission process, the data transmission speed and the cacheable data capacity are generally considered. The image data acquisition and transmission system in the prior art mainly has the following defects: 1. the capacity of an internal memory of the system is small, and a large amount of image data cannot be cached; 2. the real-time bandwidth of the system is low, and the real-time high-bandwidth data transmission cannot be met; 3. in order to meet the requirement of caching a large amount of image data, an external memory needs to be added, and the cost is high.
The FPGA is a programmable logic device and is widely applied to the fields of communication, video image processing and the like. These applications require a large amount of BRAMs in the FPGA, and when the capacity of the BRAMs cannot meet the requirements, it may be considered to replace the FPGA with a larger model, or to extend storage devices such as SDRAM and DDR outside. However, similar memory devices are expanded, support of an FPGA and a memory IP is required, and for a small FPGA device or an FPGA device without a memory hard IP, the system cost is greatly increased by adding storage.
An LVDS (Low Voltage Differential Signaling) interface is also called an RS-644 bus interface, and is currently widely used in the field of video image processing. With the continuous improvement of the LVDS transmission rate, the clock period occupied by each bit of the data signal is continuously shortened, which results in the reduction of the sampling accuracy of the sampling clock in the effective clock period of the data, and in addition, the delay time of the data signal and the data sampling clock reaching the receiving end is not always consistent, which may result in the offset between the sampling clock and the data, and the error of the sampling data.
Disclosure of Invention
The invention aims to solve the technical problem of providing an image data acquisition and transmission method and system with LVDS sampling clock phase self-calibration, which can meet the requirement of real-time high-bandwidth data transmission and avoid the deviation between a sampling clock and sampling data, thereby improving the timeliness, stability and accuracy of data transmission.
The invention adopts the technical scheme that an image data acquisition and transmission method with LVDS sampling clock phase self-calibration comprises the following steps:
s1, an ARM processor transmits a control instruction for configuring a register in image acquisition equipment and acquiring image data by the image acquisition equipment to an FPGA chip through a serial port, and the FPGA chip configures the register in the image acquisition equipment through an SPI interface after receiving the control instruction;
s2, after configuration is completed, a CIS of the image acquisition device acquires image data and transmits the image data to the LVDS interface, the image data output by the LVDS interface is subjected to automatic phase adjustment through the clock phase calibration unit, and the specific process of the image data subjected to automatic phase adjustment through the clock phase calibration unit is as follows:
s2.1, converting the differential data signals in the five data channels and the differential data signal in one clock channel output by the LVDS interface into single-ended data signals to obtain the single-ended data signals of the five data channels and the single-ended data signal of the clock channel;
s2.2, converting the obtained single-ended data signals in the five data channels into parallel data;
s2.3, selecting any one data channel, and adjusting the clock phase of the parallel data in the data channel; then sequentially selecting the parallel data in the other data channels for clock phase adjustment until the parallel data in the five data channels complete the clock phase adjustment; the process of adjusting the clock phase of the parallel data in the data channel comprises the following steps:
s2.31, taking an initial clock phase value of the parallel data in the data channel as a relative stable phase value, sampling the parallel data in the data channel according to the relative stable phase value, and performing serial conversion and parallel operation on the sampled data according to a deserializing mode with a set proportion to obtain a plurality of data with different characteristics;
s2.32, taking the relative stable phase value as a reference, decreasing the relative stable phase value progressively, adjusting the sampling clock phase according to the phase value obtained by each decreasing, and adjusting the clock phaseThen sampling the parallel data, and performing serial-to-parallel operation on the sampled data in a deserializing mode according to a set proportion; until one piece of data obtained by deserializing does not belong to one of the data with different characteristics obtained in the step S2.31, stopping decrementing relative to the stable phase value, and taking the currently decremented phase value as a critical value tap min ；
S2.33, taking the relative stable phase value as a reference, increasing the relative stable phase value, adjusting the sampling clock phase according to the phase value obtained by each increasing, sampling the parallel data after adjusting the clock phase, and then performing serial-to-parallel operation on the sampling data according to a deserializing mode with a set proportion; until one data obtained by deserializing does not belong to one of the data with different characteristics obtained in the step S2.31, stopping increasing the relative stable phase value, and taking the phase value obtained by current increasing as a critical value tap max ；
S2.34, obtaining the critical value tap min And a threshold value tap max Taking an average value, namely:
the obtained mean value
As the final sampling clock phase value;
s2.35, phase shifting is carried out on the sampling clock according to the obtained final sampling clock phase value, so that the edge of the sampling clock is positioned at the center of the sampling data;
and S2.4, transmitting the parallel data in the five data channels completing the clock phase adjustment to a virtual BRAM of the FPGA for caching.
The beneficial effects of the invention are: by adopting the image data acquisition and transmission method with LVDS sampling clock phase self-calibration, each image data acquired by the method is subjected to clock phase calibration and then transmitted to the storage area for storage, so that the offset between the sampling clock and the sampling data can be avoided, and the stability and the accuracy of the sampling data are ensured; and the transmission rate of the data after the clock phase adjustment can reach 175MB/s, so that a large amount of image information can be transmitted in real time, and the timeliness of data transmission is ensured.
Preferably, the virtual BRAM is 64M SDRAM, and 64M SDRAM can buffer large capacity data information.
An image data acquisition and transmission system with LVDS sampling clock phase self-calibration, the system comprising: the system comprises a power management unit, a system main control unit and an FPGA chip; the system main control unit comprises an ARM processor, the FPGA chip comprises an FPGA control module, a clock phase calibration unit and an FPGA storage module, the FPGA control module is connected with the ARM processor through a serial port, the FPGA control module is connected with the image acquisition equipment through an SPI interface, the ARM processor transmits a control instruction for configuring a register in the image acquisition equipment and acquiring image data by the image acquisition equipment to the FPGA through the serial port, and the FPGA configures the register in the image acquisition equipment through the SPI interface after receiving the control instruction; the clock phase calibration unit comprises a differential-to-single-ended module, a serial-to-parallel conversion module, a channel selection module, a phase alignment module and a delay adjustment module, wherein the differential-to-single-ended module is connected with an LVDS interface in the image acquisition equipment, and is used for converting differential data signals in five data channels output by the LVDS interface and differential data signals in one clock channel into single-ended data signals; the serial-parallel conversion module is used for converting the obtained single-ended data signals in the five data channels into parallel data; the channel selection module is used for selecting a data channel to carry out phase adjustment, the phase alignment module is used for calculating a final sampling clock phase value, and the delay adjustment module is used for carrying out phase shift on a sampling clock according to the calculated final sampling clock phase value so that the edge of the sampling clock is positioned at the center position of sampling data.
Preferably, the FPGA storage module comprises a virtual BRAM, an FIFO memory and an MIPI interface, the virtual BRAM is a 64M SDRAM, the virtual BRAM is used for caching parallel data in five data channels for completing clock phase adjustment, the virtual BRAM transmits the parallel data to the MIPI interface through the FIFO memory, and the MIPI interface sends the parallel data to the ARM processor for data sequencing operation. By adopting the structure, large-capacity data information can be cached, caching and reading and writing operations of a large amount of image data are realized, external memories are prevented from being expanded by the module, system cost is saved, and development difficulty is reduced.
By adopting the image data acquisition and transmission system with LVDS sampling clock phase self-calibration, each image data acquired can be subjected to clock phase calibration and then transmitted to the storage area for storage, so that the offset between the sampling clock and the sampling data can be avoided, and the stability and the accuracy of the sampling data are ensured; and the transmission rate of the data after the clock phase adjustment can reach 175MB/s, so that a large amount of image information can be transmitted in real time, and the timeliness of data transmission is ensured.
Drawings
FIG. 1 is a system structure diagram of an image data acquisition and transmission system with LVDS sampling clock phase self-calibration according to the present invention;
FIG. 2 is a schematic diagram illustrating an image data output by the LVDS interface according to the present invention being automatically adjusted in phase by the clock phase calibration unit;
FIG. 3 is a schematic diagram of parallel data in data channels being clocked out of phase;
fig. 4 is a schematic structural diagram of an FPGA storage module in the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings in combination with specific embodiments so that those skilled in the art can implement the invention with reference to the description, and the scope of the invention is not limited to the specific embodiments.
The invention relates to an image data acquisition and transmission method with LVDS sampling clock phase self-calibration, taking the acquisition and transmission of image data as an example, the method comprises the following steps:
s1, as shown in figure 1, an ARM processor RK3399 transmits a control instruction for configuring a register in image acquisition equipment and acquiring image data of the image acquisition equipment to an FPGA chip through a serial port, and after receiving the control instruction, the FPGA chip configures the register in the image acquisition equipment through an SPI interface;
s2, after configuration is completed, a CIS of the image acquisition equipment acquires image data and transmits the image data to the LVDS, the image data output by the LVDS is subjected to automatic phase adjustment through the clock phase calibration unit, and the specific process of the image data subjected to automatic phase adjustment through the clock phase calibration unit is as follows:
s2.1, as shown in fig. 2, converting the differential data signals in the five data channels and the differential data signal in one clock channel output by the LVDS interface into single-ended data signals, so as to obtain single-ended data signals of the five data channels and a single-ended data signal of the clock channel; for example, a pair of differential data lvds _ data _ p [0] and lvds _ data _ n [0] is converted into a single-ended data signal lvds _ data [0];
s2.2, converting the obtained single-ended data signals in the five data channels into parallel data;
s2.3, selecting any one data channel, and adjusting the clock phase of the parallel data in the data channel; then sequentially selecting the parallel data in the other data channels for clock phase adjustment until the parallel data in the five data channels complete the clock phase adjustment; therefore, the situation that the multi-channel phase adjustment is carried out simultaneously and excessive internal storage resources are occupied can be avoided; the process of adjusting the clock phase of the parallel data in the data channel comprises the following steps:
s2.31, as shown in FIG. 3, data comes before a clock, an initial clock phase value of parallel data in a data channel is taken as a relatively stable phase value, the parallel data in the data channel is sampled according to the relatively stable phase value, and the sampled data is deserialized and operated according to a set proportion deserializing mode to obtain a plurality of different data; for example, taking an image of 200-bit data as an example, the image is transmitted through five data channels, each data channel transmits 40 bits, and the parallel data output by each data channel is set to be 10 bits, which is 1111100000, so that the output of 40-bit data needs to be completed four times in succession, and the output data of four times in succession is 1111100000_1111100000 _1111100000, which is 1: the 40bit data is deserialized by the proportion of 8, and the data which can be obtained has ten characteristics, which are respectively: 1111_1000, 1111_0000, 1110 _u0000, 1100 _u0001, 1000 _u0011, 0000_0111, 0000_1111, 0001_1111, 0011_1110, 0111_1100, that is, data with ten different characteristics;
s2.32, taking the relative stable phase value as a reference, decreasing the relative stable phase value, adjusting the sampling clock phase according to the phase value obtained by each decreasing, sampling the parallel data after adjusting the clock phase, and then performing serial-to-parallel operation on the sampling data according to a deserializing mode with a set proportion; stopping decreasing the relative stable phase value until certain data obtained by deserialization does not belong to one of the ten kinds of data with different characteristics obtained in the step S2.31, and taking the phase value obtained by current decreasing as a critical value tapmin;
s2.33, taking the relative stable phase value as a reference, increasing the relative stable phase value, adjusting the sampling clock phase according to the phase value obtained by each increasing, sampling the parallel data after adjusting the clock phase, and then performing serial-to-parallel operation on the sampling data according to a deserializing mode with a set proportion; until certain data obtained by deserialization is not one of the ten different data obtained in the step S2.31, stopping increasing the relative stable phase value, and taking the phase value obtained by current increasing as a critical value tapmax;
s2.34, averaging the obtained critical value tapmin and critical value tapmax, namely:
the obtained mean value
As the final sampling clock phase value;
s2.35, phase shifting is carried out on the sampling clock according to the obtained final sampling clock phase value, so that the edge of the sampling clock is positioned at the center of the sampling data; the phase shift of the sampling clock is adjusted, so that the clock edge is positioned at the center of the data, the clock bit alignment is met, the metastable state is avoided, and the stability of data transmission is ensured;
and S2.4, transmitting parallel data in the five data channels completing the clock phase adjustment to a virtual BRAM of the FPGA for caching, wherein the virtual BRAM is 64M SDRAM (synchronous dynamic random access memory), and the 64M SDRAM can cache large-capacity data information.
The image data in the method of the invention is transmitted to the virtual BRAM of the FPGA for caching in an LVDS transmission mode, and the transmission bandwidth is 175MB/s; in order to solve the problem of offset between a sampling clock and data, the invention provides an LVDS sampling phase automatic adjusting function, an LVDS delay single path is added, and the relative phase of the clock and the data is adjusted by adjusting the delay of the data and the clock, so that stable data sampling is realized.
By adopting the image data acquisition and transmission method with LVDS sampling clock phase self-calibration, each image data acquired by the method is subjected to clock phase calibration and then transmitted to the storage area for storage, so that the offset between the sampling clock and the sampling data can be avoided, and the stability and the accuracy of the sampling data are ensured; and the transmission rate of the data after the clock phase adjustment can reach 175MB/s, so that a large amount of image information can be transmitted in real time, and the timeliness of data transmission is ensured.
In step S2.3, the deserializing of the sampled data according to the predetermined ratio is mainly performed by deserializing the parallel data by using a deserializer in the FPGA chip, where the predetermined ratio is 1: and 8, performing deserialization by using an area speed change strategy and adopting a DDR (double data rate) working mode.
An image data acquisition and transmission system with LVDS sampling clock phase self-calibration, as shown in fig. 1, includes: the system comprises a power management unit, a system main control unit and an FPGA chip; the system main control unit comprises an ARM processor, the FPGA chip comprises an FPGA control module, a clock phase calibration unit and an FPGA storage module, the FPGA control module is connected with the ARM processor through a serial port, the FPGA control module is connected with the image acquisition equipment through an SPI interface, the ARM processor transmits a control instruction for configuring a register in the image acquisition equipment and acquiring image data by the image acquisition equipment to the FPGA through the serial port, and the FPGA configures the register in the image acquisition equipment through the SPI interface after receiving the control instruction; the clock phase calibration unit comprises a differential-to-single-ended module, a serial-to-parallel conversion module, a channel selection module, a phase alignment module and a delay adjustment module, wherein the differential-to-single-ended module is connected with an LVDS interface in the image acquisition equipment, and is used for converting differential data signals in five data channels output by the LVDS interface and differential data signals in one clock channel into single-ended data signals; the serial-parallel conversion module is used for converting the obtained single-ended data signals in the five data channels into parallel data; the channel selection module is used for selecting a data channel to carry out phase adjustment, the phase alignment module is used for calculating a final sampling clock phase value, and the delay adjustment module is used for carrying out phase shift on a sampling clock according to the calculated final sampling clock phase value so that the edge of the sampling clock is positioned at the center position of sampling data.
The FPGA storage module comprises a virtual BRAM, an FIFO memory and an MIPI interface, wherein the virtual BRAM is a 64M SDRAM, a phase-locked loop PLL provides a clock to control the work of the memory, and then a user stores the image data after LVDS decoding into the virtual BRAM according to an internal BRAM data reading and writing method to perform reading and writing operation, so that caching and reading and writing operation of a large amount of image data are realized. The module avoids expanding an external memory, saves the system cost and reduces the development difficulty; the virtual BRAM transmits the parallel data to the MIPI through the FIFO memory, and the MIPI sends the parallel data to the ARM processor for data sorting operation.
The FPGA storage module comprises SDRAM (synchronous dynamic random access memory) provided with devices, an external interface of the FPGA storage module is similar to a BRAM (block address register) in the FPGA, and the external interface is equivalent to mounting a virtual BRAM and is used for caching data information acquired by a Contact Image Sensor (CIS for short).
By adopting the image data acquisition and transmission system with the LVDS sampling clock phase self-calibration, each image data acquired by the system can be subjected to clock phase calibration and then transmitted to the storage region for storage, so that the offset between the sampling clock and the sampling data can be avoided, and the stability and the accuracy of the sampling data are ensured; and the transmission rate of the data after the clock phase adjustment can reach 175MB/s, so that a large amount of image information can be transmitted in real time, and the timeliness of data transmission is ensured.
Claims (4)
1. An image data acquisition and transmission method with LVDS sampling clock phase self-calibration is characterized in that: the method comprises the following steps:
s1, an ARM processor transmits a control instruction for configuring a register in image acquisition equipment and acquiring image data by the image acquisition equipment to an FPGA chip through a serial port, and the FPGA chip configures the register in the image acquisition equipment through an SPI interface after receiving the control instruction;
s2, after configuration is completed, a CIS of the image acquisition device acquires image data and transmits the image data to the LVDS interface, the image data output by the LVDS interface is subjected to automatic phase adjustment through the clock phase calibration unit, and the specific process of the image data subjected to automatic phase adjustment through the clock phase calibration unit is as follows:
s2.1, converting the differential data signals in the five data channels and the differential data signal in the clock channel output by the LVDS interface into single-ended data signals to obtain the single-ended data signals of the five data channels and the single-ended data signal of the clock channel;
s2.2, converting the obtained single-ended data signals in the five data channels into parallel data;
s2.3, selecting any one data channel, and adjusting the clock phase of the parallel data in the data channel; then sequentially selecting the parallel data in the other data channels for clock phase adjustment until the parallel data in the five data channels complete the clock phase adjustment; the process of adjusting the clock phase of the parallel data in the data channel comprises the following steps:
s2.31, taking an initial clock phase value of the parallel data in the data channel as a relative stable phase value, sampling the parallel data in the data channel according to the relative stable phase value, and performing serial conversion and parallel operation on the sampled data according to a deserializing mode with a set proportion to obtain a plurality of data with different characteristics;
s2.32, taking the relative stable phase value as a reference, decreasing the relative stable phase value, adjusting the sampling clock phase according to the phase value obtained by each decreasing, sampling the parallel data after adjusting the clock phase, and then performing serial-to-parallel operation on the sampling data according to a deserializing mode with a set proportion; until one piece of data obtained by deserializing does not belong to one of the data with different characteristics obtained in the step S2.31, stopping decrementing relative to the stable phase value, and taking the currently decremented phase value as a critical value tap min ；
S2.33, taking the relative stable phase value as a reference, increasing the relative stable phase value, adjusting the sampling clock phase according to the phase value obtained by each increasing, sampling the parallel data after adjusting the clock phase, and then performing serial conversion and parallel operation on the sampling data in a deserializing mode according to a set proportion; until one data obtained by deserializing does not belong to one of the data with different characteristics obtained in the step S2.31, stopping increasing the relative stable phase value, and taking the phase value obtained by current increasing as a critical value tap max ；
S2.34, obtaining the critical value tap min And a threshold value tap max Taking an average value, namely:
the obtained mean value
As the final sampling clock phase value;
s2.35, phase shifting is carried out on the sampling clock according to the obtained final sampling clock phase value, so that the edge of the sampling clock is positioned at the center of the sampling data;
and S2.4, transmitting the parallel data in the five data channels completing the clock phase adjustment to a virtual BRAM of the FPGA for caching.
2. The method of claim 1 for image data acquisition and transmission with LVDS sampling clock phase self-calibration, characterized in that: the virtual BRAM is 64M SDRAM.
3. An image data acquisition and transmission system with LVDS sampling clock phase self-calibration, for implementing the image data acquisition and transmission method with LVDS sampling clock phase self-calibration according to any one of claims 1 to 2, the system comprising: the system comprises a power management unit, a system main control unit and an FPGA chip; the system main control unit comprises an ARM processor, the FPGA chip comprises an FPGA control module, a clock phase calibration unit and an FPGA storage module, the FPGA control module is connected with the ARM processor through a serial port, the FPGA control module is connected with the image acquisition equipment through an SPI (serial peripheral interface), the ARM processor transmits a control instruction for configuring a register in the image acquisition equipment and acquiring image data by the image acquisition equipment to the FPGA through the serial port, and the FPGA configures the register in the image acquisition equipment through the SPI after receiving the control instruction; the clock phase calibration unit comprises a differential-to-single-ended module, a serial-to-parallel conversion module, a channel selection module, a phase alignment module and a delay adjustment module, wherein the differential-to-single-ended module is connected with an LVDS interface in the image acquisition equipment, and is used for converting differential data signals in five data channels output by the LVDS interface and differential data signals in one clock channel into single-ended data signals; the serial-parallel conversion module is used for converting the obtained single-ended data signals in the five data channels into parallel data; the channel selection module is used for selecting a data channel to perform phase adjustment, the phase alignment module is used for calculating a final sampling clock phase value, and the delay adjustment module is used for performing phase shift on a sampling clock according to the calculated final sampling clock phase value so that the edge of the sampling clock is positioned at the center of the sampling data.
4. The system according to claim 3, wherein the system comprises: the FPGA storage module comprises a virtual BRAM, an FIFO memory and an MIPI interface, wherein the virtual BRAM is a 64M SDRAM, the virtual BRAM is used for caching parallel data in five data channels for completing clock phase adjustment, the virtual BRAM transmits the parallel data to the MIPI interface through the FIFO memory, and the MIPI interface sends the parallel data to the ARM processor for data sorting operation.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115941398A (en) * | 2022-12-01 | 2023-04-07 | 电子科技大学 | Cross-chip interconnection system and LVDS parallel data software and hardware collaborative calibration method |
| CN116996590A (en) * | 2023-07-03 | 2023-11-03 | 芯启源(上海)半导体科技有限公司 | Ethernet speed reducer of FPGA prototype verification platform and data transmission method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115941398A (en) * | 2022-12-01 | 2023-04-07 | 电子科技大学 | Cross-chip interconnection system and LVDS parallel data software and hardware collaborative calibration method |
| CN115941398B (en) * | 2022-12-01 | 2024-03-05 | 电子科技大学 | Cross-chip interconnection system and LVDS parallel data software and hardware collaborative calibration method |
| CN116996590A (en) * | 2023-07-03 | 2023-11-03 | 芯启源(上海)半导体科技有限公司 | Ethernet speed reducer of FPGA prototype verification platform and data transmission method |
| CN116996590B (en) * | 2023-07-03 | 2024-04-05 | 芯启源(上海)半导体科技有限公司 | Ethernet speed reducer of FPGA prototype verification platform and data transmission method |
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