CN115376938A - Method for manufacturing semiconductor ultrathin stack structure - Google Patents

Method for manufacturing semiconductor ultrathin stack structure Download PDF

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CN115376938A
CN115376938A CN202110544381.XA CN202110544381A CN115376938A CN 115376938 A CN115376938 A CN 115376938A CN 202110544381 A CN202110544381 A CN 202110544381A CN 115376938 A CN115376938 A CN 115376938A
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semiconductor
substrate
layer
semiconductor wafer
stop layer
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邱志威
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    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/3105—After-treatment
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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Abstract

A manufacturing method of semiconductor ultra-thin stacked structure comprises forming a stop layer structure in a semiconductor substrate by ion implantation, and arranging an electric element and an interconnection layer on the active surface of the semiconductor substrate to form a semiconductor wafer; the inner connecting layers of the two semiconductor wafers are oppositely connected together in an up-down mode; removing part of the semiconductor substrate and the stop layer structure of the upper semiconductor wafer from the back surface of the upper semiconductor wafer by back grinding and thinning process to form a thinned semiconductor wafer from the upper semiconductor wafer, then performing bonding, back grinding and thinning process to another semiconductor wafer on the thinned semiconductor wafer one by one, stacking another thinned semiconductor wafer one by one, and finally performing back grinding and thinning process to the lowest semiconductor wafer. The manufacturing method can stack a plurality of layers of thinned semiconductor wafers to meet the requirement of high integration.

Description

Method for manufacturing semiconductor ultrathin stack structure
Technical Field
The present invention relates to a method for fabricating a semiconductor structure, and more particularly, to a method for fabricating a semiconductor ultra-thin stacked structure.
Background
With the rapid development of the electronic industry, electronic products gradually enter into a multi-functional and high-performance development direction, wherein semiconductor technology is widely applied to manufacturing chip sets such as memories, central processing units, etc. In order to achieve high Integration and high speed, the size of semiconductor integrated circuits is continuously reduced, and various materials and techniques have been developed to achieve the Integration and speed requirements, and stacked structures including multi-layer substrates (multi substrates) have been developed to improve the operating speed of the circuits. When the related technologies of semiconductor planar packaging reach the limit, the demand for miniaturization can be met by integration, and the technology of stacking wafers has great assistance to future technologies, and is also a target of great improvement in the related fields at present.
Disclosure of Invention
The invention provides a method for manufacturing a semiconductor ultrathin stack structure, which can ensure that the semiconductor ultrathin stack structure can meet the requirements of high integration and speed and has better electrical characteristics and efficiency.
The invention provides a method for manufacturing a semiconductor ultrathin stack structure, which comprises the following steps: manufacturing a plurality of semiconductor wafers, wherein a semiconductor wafer is selected as a first semiconductor wafer of a bottom layer, and a part of the semiconductor wafers are used as a second semiconductor wafer and a third semiconductor wafer to be stacked, and each semiconductor wafer manufacturing step comprises: providing a semiconductor substrate with an active surface and a back surface which are opposite; forming a stop layer structure in a semiconductor substrate, and dividing the semiconductor substrate into a first substrate part and a second substrate part, wherein the first substrate part is positioned between the stop layer structure and an active surface, the second substrate part is positioned between the stop layer structure and a back surface, the stop layer structure at least comprises a silicon nitride layer, the manufacturing of the silicon nitride layer comprises a nitrogen ion injection process performed before the first depth of the semiconductor substrate, and then a high-temperature treatment process is performed, so that the nitrogen ion injection region forms the silicon nitride layer; and arranging a plurality of electric elements and an interconnection layer on the active surface, wherein the interconnection layer comprises a plurality of interconnection points, and arranging a plurality of conductive structures on the first part of the substrate to connect the interconnection layer and the stop layer. The second semiconductor wafer is inverted relative to the first semiconductor wafer, so that the interconnection layer of the first semiconductor wafer and the interconnection layer of the second semiconductor wafer are opposite and are connected together by a hybrid bonding technology; performing a first back side grinding process to grind the back side of the second semiconductor wafer to remove a portion of the second portion of the substrate of the second semiconductor wafer; performing a first thinning process to form a thinned second semiconductor wafer; performing a second back side grinding process to grind the back side of the first semiconductor wafer to remove a portion of the second portion of the substrate of the first semiconductor wafer; performing a second thinning process to form a thinned first semiconductor wafer, wherein the first thinning process and the second thinning process comprise a substrate removing step and a stop layer removing step, and the substrate removing step removes a second part of the remaining substrate to expose the stop layer structure; the stop layer removing step removes the stop layer structure to expose the first portion of the substrate and the conductive structure.
In an embodiment of the invention, before the second back-grinding process, a plurality of thinned third semiconductor wafers may be sequentially stacked on the thinned second semiconductor wafer, wherein each step of stacking the thinned third semiconductor wafers includes: inverting the third semiconductor wafer relative to the first semiconductor wafer such that the interconnect layer of the third semiconductor wafer and the first portion of the substrate of the thinned second semiconductor wafer oppose and are bonded together; performing a third back side grinding process to grind the back side of the third semiconductor wafer to remove a portion of the second portion of the substrate of the third semiconductor wafer; and performing a third thinning process including a substrate removing step and a stop layer removing step.
In an embodiment of the invention, the stop layer structure further includes a silicon dioxide layer disposed on the silicon nitride layer so as to be between the silicon nitride layer and the active surface.
In an embodiment of the present invention, the step of forming the silicon dioxide layer includes: after the nitrogen ion implantation process, firstly, an oxygen ion implantation process is carried out on the semiconductor substrate at a second depth, wherein the second depth is smaller than the first depth, and then, a high-temperature treatment process is carried out to form a silicon dioxide layer in the oxygen ion implantation area.
In an embodiment of the invention, the step of removing the stop layer includes: the silicon nitride layer is removed first, and then the silicon dioxide layer is removed.
In an embodiment of the invention, the substrate removing step is selected from one of chemical mechanical polishing, wet etching and plasma dry etching, wherein the selectivity ratio of silicon to silicon nitride is between 20 and 80.
In an embodiment of the invention, the method for removing the silicon nitride layer and the silicon dioxide layer is selected from one of chemical mechanical polishing and plasma dry etching, wherein a selectivity ratio of silicon nitride to silicon dioxide is between 10 and 20, and a selectivity ratio of silicon dioxide to silicon is about 5.
In an embodiment of the invention, a distance between the stop layer structure and the active surface is between 1 micron and 5 microns, and a thickness of the thinned second semiconductor wafer is not greater than 12 microns.
In an embodiment of the present invention, after the step of forming the thinned first semiconductor wafer, the method further includes the steps of: arranging a plurality of solder balls on one side of the thinned first semiconductor wafer far away from the thinned second semiconductor wafer so as to be respectively electrically connected with the conductive structures; and performing electrical test and singulation.
The invention provides a method for manufacturing a semiconductor ultrathin stack structure, which comprises the steps of manufacturing a plurality of semiconductor wafers, wherein the manufacturing step of each semiconductor wafer comprises the following steps: providing a semiconductor substrate with an active surface and a back surface which are opposite; forming a stop layer structure in a semiconductor substrate, dividing the semiconductor substrate into a first substrate part and a second substrate part, wherein the first substrate part is positioned between the stop layer structure and the active surface, the second substrate part is positioned between the stop layer structure and the back surface, the stop layer structure at least comprises a silicon nitride layer, the manufacturing of the silicon nitride layer comprises a nitrogen ion injection process performed before the first depth of the semiconductor substrate, and then a high-temperature treatment process is performed, so that the nitrogen ion injection region forms the silicon nitride layer; and arranging a plurality of electric elements and an interconnection layer on the active surface, wherein the interconnection layer comprises a plurality of interconnection points, and arranging a plurality of conductive structures on the first part of the substrate to connect the interconnection layer and the stop layer. Selecting one of the semiconductor wafers as a first semiconductor wafer of a bottom layer, and cutting a part of the semiconductor wafers to be used as a first batch of semiconductor chips and at least one second batch of semiconductor chips to be stacked; the first batch of semiconductor chips are inverted relative to the first semiconductor wafer, so that the interconnection layers of the first batch of semiconductor chips and the interconnection layers of the first semiconductor wafer are opposite and are connected together by a hybrid bonding technology; performing a first molding process to form a first encapsulant on the first semiconductor wafer to encapsulate the first semiconductor chips; performing a first back grinding process to remove a portion of the first encapsulant from a side of the first encapsulant away from the first semiconductor wafer and to remove a portion of the second portion of the substrate of the first batch of semiconductor chips; performing a first thinning process to form a first semiconductor chip layer; performing a second back side grinding process to grind the back side of the first semiconductor wafer to remove a portion of the second portion of the substrate of the first semiconductor wafer; and performing a second thinning process to form a thinned first semiconductor wafer, wherein the first thinning process and the second thinning process comprise a substrate removing step and a stop layer removing step, wherein the substrate removing step removes the remaining second part of the substrate to expose the stop layer structure, and the stop layer removing step removes the stop layer structure to expose the first part of the substrate and the conductive structure.
In an embodiment of the invention, before performing the second back-grinding process, at least one second semiconductor chip floor may be sequentially stacked on the first semiconductor chip floor, wherein the stacking of each second semiconductor chip floor includes: inversely installing the second batch of semiconductor chips relative to the first semiconductor wafer, so that the interconnection layer of the second batch of semiconductor chips and the first part of the substrate of the first semiconductor chip layer are opposite and are bonded together; performing a second molding process to form a second encapsulant on the first semiconductor chip layer to encapsulate the second batch of semiconductor chips; performing a third back grinding process to remove a portion of the second encapsulant from a side of the second encapsulant away from the first semiconductor chip layer and to remove a portion of the second portion of the substrate of the second batch of semiconductor chips; and performing a third thinning process including a substrate removing step and a stop layer removing step.
The invention provides a manufacturing method of a semiconductor ultrathin stack structure, which comprises the following steps: providing a bearing plate, and forming a plurality of first conductive columns on the bearing plate. Providing a plurality of semiconductor chips, each of the semiconductor chips being fabricated by steps comprising: providing a semiconductor substrate with an active surface and a back surface which are opposite; forming a stop layer structure in a semiconductor substrate, and dividing the semiconductor substrate into a first substrate part and a second substrate part, wherein the first substrate part is positioned between the stop layer structure and an active surface, the second substrate part is positioned between the stop layer structure and a back surface, the stop layer structure at least comprises a silicon nitride layer, the manufacturing of the silicon nitride layer comprises a nitrogen ion injection process performed before the first depth of the semiconductor substrate, and then a high-temperature treatment process is performed, so that the nitrogen ion injection region forms the silicon nitride layer; arranging a plurality of electric elements and an interconnection layer on the active surface, wherein the interconnection layer comprises a plurality of interconnection points, and arranging a plurality of conductive structures on the first part of the substrate to connect the interconnection layer and the stop layer; and performing singulation. The semiconductor chips are sorted into a first batch of semiconductor chips and at least one second batch of semiconductor chips, wherein the first batch of semiconductor chips comprises a plurality of first semiconductor chips, and the second batch of semiconductor chips comprises a plurality of second semiconductor chips. The first semiconductor chips are arranged on the bearing plate in an inverted mode, the first conductive columns are arranged between the adjacent first semiconductor chips, the interconnection layers of the first semiconductor chips are adjacent to the bearing plate, and the semiconductor substrate is far away from the bearing plate. A first molding process is performed to form a first encapsulant on the carrier plate to encapsulate the first semiconductor chips and the first conductive pillars. And performing a first back grinding process to remove a part of the first encapsulant from the side of the first encapsulant away from the carrier plate and to remove a part of the second portion of the substrate of the first semiconductor chips. The first thinning process includes sequentially removing the remaining second portions of the substrate and the stop layer structure of the first batch of semiconductor chips to expose the first portions of the substrate, the conductive structures and the first conductive pillars. A plurality of second conductive columns are arranged to be electrically connected with part of the conductive structures of the first semiconductor chip layer. The second semiconductor chips are arranged on the first semiconductor chip layers in a flip-chip mode, wherein the second semiconductor chips are respectively bridged between the adjacent first semiconductor chips, the interconnection layer of the second semiconductor chips is electrically connected with the exposed first conductive columns and part of the conductive structures of the first semiconductor chip layers, and part of the second conductive columns are arranged between the adjacent second semiconductor chips. And performing a second molding process to form a second encapsulant on the first semiconductor chip layer to encapsulate the second semiconductor chips and the second conductive pillars. And performing a second back grinding process to remove a part of the second packaging colloid from the side of the second packaging colloid far away from the first semiconductor chip layer and remove a part of the second part of the substrate of the second batch of semiconductor chips. And performing a second thinning process to form a second semiconductor chip layer, wherein the second thinning process comprises removing the remaining second portions of the substrates and the stop layer structure of the second batch of semiconductor chips in sequence to expose the first portions of the substrates, the conductive structures and the second conductive columns. The carrier is removed to expose the interconnect layer and the first conductive pillar of the first semiconductor chip layer.
In an embodiment of the invention, after removing the carrier plate, the method further includes the following steps: arranging a plurality of solder balls on one side of the first semiconductor chip layer, which is far away from the second semiconductor chip layer, so as to be respectively and electrically connected with the interconnection layer and the first conductive posts; and performing singulation.
In an embodiment of the invention, the plurality of first semiconductor chips of the first group of semiconductor chips have different electrical functions.
In an embodiment of the invention, the second semiconductor chips of the second group of semiconductor chips have different electrical functions.
When manufacturing a semiconductor wafer, firstly, forming a stop layer structure in a semiconductor substrate by an ion implantation process, and then arranging an electric element and an interconnection layer on an active surface of the semiconductor substrate; then, the two semiconductor wafers are bonded up and down, or the semiconductor wafers are singulated to form a plurality of semiconductor chips, and then the semiconductor chips in the lot are bonded to the semiconductor wafer at the lowermost layer. After each bonding (and molding encapsulation colloid) of the semiconductor wafer/chip, a part of the semiconductor substrate and the stop layer structure of the upper semiconductor wafer/chip are removed from the back of the upper semiconductor wafer/chip by a back grinding and thinning process, so that the upper semiconductor wafer/chip forms a thinned semiconductor wafer/chip layer, then bonding (and molding encapsulation colloid) and back grinding and thinning processes of the other semiconductor wafer/chip are carried out on the thinned semiconductor wafer/chip one by one, another thinned semiconductor wafer/semiconductor chip layer is stacked upwards, and finally the back grinding and thinning process is carried out on the lowest semiconductor wafer. Since the thickness of each thinned semiconductor wafer/semiconductor chip layer is not more than 12 microns, the thinned semiconductor wafer/semiconductor chip layers can be stacked to 57 chip layers under the limitation that the total thickness of the chips is limited to 700 microns, and the requirements of high integration and speed are further met.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.
Drawings
Fig. 1A to fig. 1S are schematic cross-sectional views illustrating a method for manufacturing a semiconductor ultra-thin stacked structure according to a first embodiment of the invention.
Fig. 2A to 2K are schematic cross-sectional views illustrating a method for manufacturing a semiconductor ultra-thin stacked structure according to a second embodiment of the invention.
Fig. 3A to 3L are schematic cross-sectional views illustrating a method for manufacturing an ultra-thin semiconductor stack structure according to a third embodiment of the invention.
Detailed Description
Fig. 1A to fig. 1S are schematic cross-sectional views illustrating a method for manufacturing a semiconductor ultra-thin stacked structure according to a first embodiment of the invention. First, a plurality of semiconductor wafers 10 (shown in fig. 1E) are manufactured, one of the semiconductor wafers 10 is selected as a first semiconductor wafer 10a (shown in fig. 1F) at the bottom of the stack, and the other semiconductor wafers 10 are selected as a second semiconductor wafer 10b (shown in fig. 1F) and a third semiconductor wafer 10c (shown in fig. 1L) to be stacked, the manufacturing processes of the plurality of semiconductor wafers 10 are the same or similar, and fig. 1A to 1E are schematic cross-sectional views of the manufactured semiconductor wafers 10. As shown in fig. 1A, a semiconductor substrate 12 is provided, the semiconductor substrate 12 is, for example, a silicon substrate (silicon substrate), an epitaxial silicon substrate (epitaxial silicon substrate), a silicon germanium substrate (silicon germanium substrate), a silicon carbide substrate (silicon carbide substrate) or a Silicon On Insulator (SOI) substrate, in one embodiment, the thickness of the semiconductor substrate is, for example, 700 to 800 micrometers (um), preferably 775 micrometers, and the semiconductor substrate 12 has an active surface 121 and a back surface 122 opposite to each other.
Next, a stop layer structure is formed in the semiconductor substrate 12. In one embodiment, the fabricating of the stop layer structure includes performing at least one of an ion implantation process and a high temperature treatment process. In one embodiment, the ion implantation process comprises nitrogen ion implantation followed by oxygen ion implantation. As shown in fig. 1B and fig. 1C, a nitrogen ion implantation process 14 is performed at a first depth D1 of the semiconductor substrate 12, and an oxygen ion implantation process 16 is performed at a second depth D2 of the semiconductor substrate 12, wherein in one embodiment, the first depth D1 of the nitrogen ion implantation region 14' is about 1 to 5 μm from the active surface 121, and the second depth D2 of the oxygen ion implantation region 16' is smaller than the first depth D1 of the nitrogen ion implantation region 14, that is, the oxygen ion implantation region 16' is closer to the active surface 121.
Then, a high temperature process is performed to form silicon nitride (Si) in the nitrogen ion implantation region 14', as shown in FIG. 1D 3 N 4 ) Layer 14a, silicon dioxide (SiO) formed in the oxygen ion implanted region 16 2 ) In the embodiment, the silicon nitride layer 14a and the silicon dioxide layer 16a form the above-mentioned stop layer structure 18, wherein the silicon dioxide layer 16a is located on the silicon nitride layer 14 and between the silicon nitride layer 14a and the active surface 121, and the silicon nitride layer 14a is located closer to the active surface 121 and the back surface 122. In one embodiment, the thickness of the silicon nitride layer 14a and the silicon dioxide layer 16a is, for example, 500 nanometers (nm). For convenience of explanation, the semiconductor substrate 12 between the silicon dioxide layer 16a of the stop layer structure 18 and the active surface 121 is referred to as a substrate first portion 123, and the semiconductor substrate 12 between the silicon nitride layer 14a of the stop layer structure 18 and the back surface 122 is referred to as a substrate second portion 124. In one embodiment, the semiconductor wafer 10 is subsequently subjected to metal oxidationIn the fabrication of a semiconductor field effect transistor (MOSFET), the depth of the N-well is about 2 μm, so that the thickness of the first portion 123 of the substrate is not less than 2 μm, i.e., the first depth D1 of the nitrogen ion implantation region 14 'and the second depth of the oxygen ion implantation region 16' are both slightly greater than 2 μm when the nitrogen ion implantation process 14 and the oxygen ion implantation process 16 are performed.
To continue the above description, as shown in fig. 1E, a plurality of electrical elements 20 and an interconnection layer 22 having interconnection points 221 are disposed on the active surface 121, the electrical elements 20 include, for example, metal Oxide Semiconductors (MOS), and a plurality of conductive structures are disposed on the substrate first portion 123, in an embodiment, the conductive structures include, for example, through Silicon Vias (TSVs) 24, and the TSV 24 vertically connects the interconnection layer 22 and the Silicon dioxide layer 16a of the stop layer structure 18. The process flow of the electrical component 20, the interconnect layer 22 and the through-silicon-via 24 includes front-end-of-line (FEOL) processes and back-end-of-line (BEOL) processes of a general semiconductor process, wherein the front-end processes include forming resistors, capacitors, diodes, transistors, etc. on the semiconductor substrate 12, and the back-end processes include forming metal wires for connection and interconnection points 221 between the components; in one embodiment, the interconnection point 221 is a copper contact. Fig. 1E is a schematic diagram of a semiconductor wafer 10 according to an embodiment of the invention, and the first semiconductor wafer 10a, the second semiconductor wafer 10b, and the third semiconductor wafer 10c are described using reference numerals of the semiconductor wafer 10. The through-silicon vias 24 of the first semiconductor wafer 10a correspond to the solder ball mounting locations in the subsequent process, and the through-silicon vias 24 of the second semiconductor wafer 10b correspond to the interconnection points 221 of the interconnection layer 22 of the third semiconductor wafer 10 c.
As shown in fig. 1F, the second semiconductor wafer 10b is flipped over with respect to the first semiconductor wafer 10a, such that the interconnect layers 22 of the first semiconductor wafer 10a and the second semiconductor wafer 10b are opposite and the interconnect points 221 are corresponding to each other; next, the first semiconductor wafer 10a and the second semiconductor wafer 10b are stacked on top of each other by Hybrid bonding (Hybrid bonding) including copper-to-copper bonding and annealing processes, as shown in fig. 1G.
Then, a first back side grinding (Grind) process is performed to remove a portion of the second portion 124 of the substrate from the second semiconductor wafer 10b by grinding the back side 122 of the second semiconductor wafer 10b, as shown in FIG. 1H, leaving a very thin second portion 124 of the substrate, and in one embodiment, leaving the second portion 124 of the substrate with a thickness of about 20 a.
Then, a first thinning process is performed to form a thinned second semiconductor wafer, the first thinning process includes a substrate removing step and a stop layer removing step, and fig. 1I to fig. 1K are schematic diagrams of the first thinning process. A substrate removal step, as shown in fig. 1I, is performed to remove the remaining second portion 124 of the substrate to reveal the stop layer structure 18, for example, to reveal the silicon nitride layer 14a, in one embodiment, the substrate removal step is a first Chemical Mechanical Polishing (CMP) process, wherein the selectivity of silicon to silicon nitride is, for example, 20, i.e., si/Si 3 N 4 Is 20; the stop layer removal step is to remove the stop layer structure 18, i.e. sequentially remove the silicon nitride layer 14a and the silicon dioxide layer 16a to expose the substrate first portion 123 and the through-silicon via 24; in one embodiment, the silicon nitride layer 14a is removed by a second CMP process, as shown in FIG. 1J, to reveal the silicon dioxide layer 16a, wherein the silicon nitride and silicon dioxide have a selectivity of, for example, 10, i.e., si 3 N 4 /SiO 2 Is 10; the silicon dioxide layer 16a is then removed by a third CMP process, as shown in FIG. 1K, to expose the first portion 123 of the substrate and the through-silicon-vias 24, wherein the silicon dioxide and silicon have a selectivity of, for example, 5, i.e., siO 2 The value of/Si is 5. The thinned second semiconductor wafer 10b' is formed by the exposure of the substrate first portion 123 and the through-silicon-vias 24.
Continuing with the above description, the stacking of the completed first semiconductor wafer 10a and the thinned second semiconductor wafer 10b' is performed; next, as shown in fig. 1L, the third semiconductor wafer 10c is flipped with respect to the first semiconductor wafer 10a such that the interconnect layers 22 of the third semiconductor wafer 10c face the substrate first portion 123 of the thinned second semiconductor wafer 10b ', and in one embodiment, the interconnect points 221 of the interconnect layers 22 of the third semiconductor wafer 10c respectively correspond to the through-silicon vias 24 of the thinned second semiconductor wafer 10b'. Thereafter, the first back grinding process and the first thinning process are repeated to complete the stacking of the thinned third semiconductor wafer 10c 'and the thinned second semiconductor wafer 10b', and in one embodiment, the thickness of the thinned second semiconductor wafer 10b 'or the thinned third semiconductor wafer 10c' is, for example, 12 μm. In this way, on the premise of having a plurality of semiconductor wafers 10, the bonding process, the first back grinding process and the first thinning process of the semiconductor wafers 10 are repeated one by one, so as to complete the stacking of the multi-layer thinned semiconductor wafer 10 'and the first semiconductor wafer 10a, as shown in fig. 1M, in an embodiment, the first portion 123 of the substrate as the thinned semiconductor wafer 10' stacked at the top may not need to be formed with the through-silicon vias 24.
After stacking of a predetermined number of thinned semiconductor wafers 10' is completed, grinding the back surface 122 of the first semiconductor wafer 10a using a second back grinding process, as shown in fig. 1N, to remove a portion of the substrate second portion 124 of the first semiconductor wafer 10a, leaving an extremely thin substrate second portion 124; next, a second thinning process is performed, as shown in fig. 1O to fig. 1Q, by using the substrate removing step and the stop layer removing step, the substrate second portion 124, the silicon nitride layer 14a and the silicon dioxide layer 16a remaining on the first semiconductor wafer 10a are sequentially removed, and the substrate first portion 123 and the through-silicon via 24 of the thinned first semiconductor wafer 10a ' are exposed, so as to complete the stacking of the thinned semiconductor wafers 10' such as the thinned first semiconductor wafer 10a ', the thinned second semiconductor wafer 10b ', and the thinned third semiconductor wafer 10c '.
Then, as shown in fig. 1R, a plurality of solder balls 26 are disposed on a side of the thinned first semiconductor wafer 10a 'away from the thinned second semiconductor wafer 10b' to electrically connect the exposed through-silicon vias 24, respectively; after performing wafer Probing (CP) for electrical performance testing (Test), a die saw (die saw) is performed to complete the semiconductor ultra-thin stacked structure 28 shown in fig. 1S, wherein each thinned semiconductor wafer 10' is cut into individual semiconductor Chip layers 10', and since the thickness of each thinned semiconductor wafer 10' may be, for example, 12 microns, and the limitation of the total Chip thickness being 700 microns, 57 thinned semiconductor Chip layers 10 "may be stacked in the semiconductor ultra-thin stacked structure 28 according to the embodiment of the present invention, which can satisfy the requirements of high integration and speed, and has better electrical characteristics and efficiency.
In the first thinning process and the second thinning process, the substrate removing step and the stop layer removing step include three cmp processes, but not limited thereto, in another embodiment, the first/second thinning process includes a wet etching process and two cmp processes, that is, in the substrate removing step, the wet etching process is used to replace the first cmp process, the cross-sectional view of the thinning process can still refer to fig. 1H to 1K or fig. 1N to 1Q, the remaining substrate second portion 124 is removed by the wet etching process to expose the silicon nitride layer 14a, the selectivity of silicon and silicon nitride in the wet etching process is, for example, 40, that is, si/Si 3 N 4 Is 40; then, the second CMP process and the third CMP process are sequentially performed to sequentially remove the silicon nitride layer 14a and the silicon dioxide layer 16a.
In another embodiment, the first and second thinning processes may also be replaced by three plasma dry etching (plasma dry etching) processes, the cross-sectional view of the thinning process can still be shown in fig. 1H to 1K or fig. 1N to 1Q, the remaining second portion 124 of the substrate is removed by the first plasma dry etching process to expose the silicon nitride layer 14a, in one embodiment, the selectivity of silicon to silicon nitride in the first plasma dry etching is, for example, 80, i.e., si/Si 3 N 4 Is 80; the silicon nitride layer 14a is then removed by a second plasma dry etch process to expose the silicon dioxide layer 16a, in one embodiment, the selectivity of silicon nitride to silicon dioxide in the second plasma dry etch process is, for example, 20, i.e., si 3 N 4 /SiO 2 Is 20; then, a third plasma dry etching process is performed to remove the silicon dioxide layer 16a to expose the first portion 123 of the substrate and the through-silicon via 24In one embodiment, the selectivity of silicon dioxide to silicon in the third plasma dry etching process is, for example, 5, i.e., siO 2 The value of/Si is 5.
In the first embodiment, the Wafer on Wafer (WoW) process is used, but not limited thereto, and fig. 2A to 2K are schematic cross-sectional views illustrating a method for manufacturing a semiconductor ultra-thin stacked structure according to a second embodiment of the present invention. In the second embodiment, a plurality of semiconductor wafers 10 are provided, and the manufacturing steps thereof are disclosed in fig. 1A to 1E, which are not described herein again; next, a first semiconductor wafer 10a (shown in fig. 2B) with a portion of the semiconductor wafer 10 as a bottom layer is selected, and another portion of the semiconductor wafer 10 is subjected to an electrical function test, and dies with good electrical functions are selected and singulated as shown in fig. 2A, so as to obtain a plurality of semiconductor chips 30, each semiconductor chip 30 still includes an electrical component 20, an interconnection layer 22 and a semiconductor substrate 12, a stop layer structure 18 is formed in the semiconductor substrate 12, the stop layer structure 18 divides the semiconductor substrate 12 into a first substrate portion 123 and a second substrate portion 124, and a through silicon via 24 is formed in the first substrate portion 123 to connect the stop layer structure 18 and the interconnection layer 22. For convenience of description, the semiconductor chips 30 are divided into a first lot 30a and a second lot 30b according to the sequence of the subsequent processes, and each lot includes a plurality of semiconductor chips 30.
As shown in fig. 2B, the first semiconductor chips 30a are flipped over with respect to the first semiconductor wafer 10a, such that the interconnect layers 22 of the first semiconductor chips 30a and the interconnect layers 22 of the first semiconductor wafer 10a are opposite and the interconnects 221 are corresponding to each other; next, the first semiconductor wafer 10a and the first semiconductor chips 30a are bonded together by a hybrid bonding technique, as shown in fig. 2C.
Next, a first molding (molding) process is performed, as shown in fig. 2D, a first molding compound (molding compound) 32a is formed on the first semiconductor wafer 10a to encapsulate the first batch of semiconductor chips 30a; thereafter, a portion of the first encapsulant 32a and a portion of the second substrate portions 124 of the first semiconductor chips 30a are removed from the side of the first encapsulant 32a away from the first semiconductor wafer 10a by a first back-grinding process, as shown in fig. 2E, the first semiconductor chips 30a have the second substrate portions 124 with an extremely thin thickness and the first encapsulant 32a flush with the second substrate portions 124.
Thereafter, a first thinning process is performed, including the substrate removing step and the stop layer removing step described in the first embodiment, to remove the remaining second portions 124 of the substrates, the stop layer structures 18 and a portion of the encapsulant 32 of the first semiconductor chips 30a, as shown in fig. 2F, to expose the first portions 123 of the substrates and the through-silicon vias 24 of the first semiconductor chips 30a, so as to form thinned first semiconductor chip layers 30a ', and the first semiconductor chip layers 30a' are stacked on the first semiconductor wafer 10 a.
Next, the second semiconductor chips 30b are still flipped over with respect to the first semiconductor wafer 10a so that the interconnection layers 22 of the second semiconductor chips 30b correspond to the first portions 123 of the substrate of the first semiconductor chip layers 30a ', respectively, and bonding of the second semiconductor chips 30b to the first semiconductor chip layers 30a' is performed; performing a second molding process to form a second encapsulant 32b on the first semiconductor chip layer 30a' to encapsulate the second semiconductor chips 30b; a back grinding process and a thinning process are performed to remove a portion of the second encapsulant 32b, a second portion (not shown) of the substrate of the second semiconductor chips 30b and a stop layer structure (not shown) from a side of the second encapsulant 32b away from the first semiconductor chip layer 30a ', so as to expose the first portion 123 of the substrate of the second semiconductor chips 30b and the through-silicon vias 24, as shown in fig. 2G, to form a thinned second semiconductor chip layer 30b'. Thus, the bonding process, the molding process, the back grinding process and the first thinning process of the semiconductor chips 30 of the batch are repeated batch by batch to complete the stacking of the first semiconductor chip layer 30a ' and the plurality of second semiconductor chip layers 30b ' with the first semiconductor wafer 10a, as shown in fig. 2H, in one embodiment, the first portion 123 of the substrate as the second semiconductor chip layer 30b ' stacked on the top may not need to be formed with the through-silicon vias 24.
Next, as in the first embodiment, after the stacking of the predetermined number of second semiconductor chip layers 30b 'is completed, the second back grinding process and the second thinning process are used to sequentially remove the substrate second portion 124 and the stop layer structure 18 of the first semiconductor wafer 10a from the back surface 122 of the first semiconductor wafer 10a, as shown in fig. 2I, to expose the substrate first portion 123 and the through-silicon via 24, so as to complete the stacking of the thinned first semiconductor wafer 10a' and the plurality of semiconductor chips 30.
The first and second thinning processes include the substrate removing step and the stop layer removing step described in the first embodiment, wherein the process selection for the substrate removing step and the stop layer removing step, such as three chemical mechanical polishing processes, or a wet etching process and a chemical mechanical polishing process, or both of them, and the selection ratio of silicon, silicon nitride and silicon dioxide are described in the first embodiment, and will not be described herein again
Then, as shown in fig. 2J, solder balls are disposed on the exposed through-silicon vias 24 of the thinned first semiconductor wafer 10a', and after performing an electrical function test, singulation is performed along the scribe lines 321 of the first encapsulant 32a and the second encapsulant 32b to complete the ultra-thin semiconductor stacked structure 34 shown in fig. 2K. In the semiconductor ultra-thin stacked structure 34 of this embodiment, since the stacked semiconductor chips 30 are tested and sorted for electrical function, the yield of the semiconductor ultra-thin stacked structure 34 is high.
Fig. 3A to 3L are schematic cross-sectional views illustrating a method for manufacturing a semiconductor ultra-thin stacked structure according to a third embodiment of the invention. In the third embodiment, first, a carrier 40 is provided, and a plurality of first conductive pillars 42 are formed on the carrier 40, as shown in fig. 3A, the carrier 40 is, for example, glass with a thickness of 500 micrometers and a length of 301 millimeters (mm), and the first conductive pillars 42 are, for example, copper pillars.
Next, a plurality of semiconductor chips 44 (labeled in fig. 3B) subjected to electrical function testing are selected, the semiconductor chips 44 may have the same or different electrical functions, the plurality of semiconductor chips 44 are obtained by respectively dicing a plurality of semiconductor wafers 10, and the manufacturing steps of each semiconductor wafer 10 are disclosed in fig. 1A to 1E and are not repeated herein. Each semiconductor die 44 still includes electrical component 20, interconnect layer 22, and semiconductor substrate 12, with stop layer structure 18 formed in semiconductor substrate 12, stop layer structure 18 separating semiconductor substrate 12 into a first substrate portion 123 and a second substrate portion 124, with first substrate portion 123 having through-silicon-vias 24 formed therein to connect stop layer structure 18 and interconnect layer 22. In one embodiment, semiconductor substrate 12 has a thickness of 775 microns, for example, and interconnect layer 22 has a thickness of 10 microns, for example.
The first semiconductor chips 44 of the first batch are flip-chip bonded to the carrier 40, as shown in fig. 3B, for example, the first semiconductor chips 44 include three first semiconductor chips 44a, the three first semiconductor chips 44a may have the same or different electrical functions, and the first conductive pillars 42 are interposed between the adjacent first semiconductor chips 44a, in one embodiment, when the first semiconductor chips 44a are flip-chip bonded, the interconnection layer 22 is bonded in a flip-chip manner adjacent to the carrier 40 and the semiconductor substrate 12 is away from the carrier 10.
Thereafter, a first molding process is performed, as shown in fig. 3C, a first encapsulant 46a is formed on the carrier 40 to encapsulate the three first semiconductor chips 44a and the first conductive pillars 42. Next, by using the first back grinding process and the first thinning process, a portion of the first encapsulant 46a, the substrate second portion 124 of the first semiconductor chip 44a and the stop layer structure 18 are removed from the side of the first encapsulant 46a away from the carrier 40, as shown in fig. 3D, the substrate first portion 123, the through-silicon via 24 and the first conductive pillar 44 are exposed, so as to form a thinned first semiconductor chip layer 44a'.
Then, a second conductive pillar 48 is disposed, for example, the second conductive pillar 48 is vertically disposed on a portion of the through-silicon via 24, as shown in fig. 3E, the second conductive pillar 48 is disposed on at least one through-silicon via 24 of each thinned first semiconductor chip 44a, and the second conductive pillar 48 is, for example, a copper pillar. Then, the sorted second semiconductor chips are flip-chip connected between two adjacent thinned first semiconductor chips 44a, as shown in fig. 3F, taking the second semiconductor chips comprising two second semiconductor chips 44b as an example, the two semiconductor chips 44b may have the same or different electrical functions, in one embodiment, the interconnect layer 22 of the second semiconductor chip 44b is opposite to the first portion 123 of the substrate of the first semiconductor chip layer 44a', the interconnect point 221 of the second semiconductor chip 44b is electrically connected to a portion of the through-silicon via 24 and the first conductive pillar 42, and a portion of the second conductive pillar 48 is interposed between the adjacent second semiconductor chips 44 b.
Then, a second molding process, a second back grinding process and a second thinning process are sequentially performed to form a second encapsulant 46b on the first semiconductor chip layer 44a 'to encapsulate the second semiconductor chip 44b and the second conductive pillars 48, and then the second back grinding process and a second thinning process are performed to remove the second portion 124 of the substrate, the stop structure layer 18 and a portion of the second encapsulant 46b of the second semiconductor chip 44b, as shown in fig. 3G, exposing the first portion 123 of the substrate, the through silicon vias 124 and the second conductive pillars 48, thereby forming a thinned second semiconductor chip layer 44b'.
Thus, the third conductive pillars 50, the flip-chip mounting of the third semiconductor chip 44c on the second semiconductor chip layer 44b ', the molding process, the back grinding process and the thinning process are repeated to complete the stacking of the third semiconductor chip layer 44c', as shown in fig. 3H, and the stacking of the successive more semiconductor chip layers, as shown in fig. 3I.
Thereafter, the carrier 40 is removed, as shown in fig. 3J, to expose the interconnection layer 22 and the first conductive pillars 42 of the first semiconductor chip layer, and the solder balls 26 are disposed on the circuit contacts (not shown) and the first conductive pillars preset on the interconnection layer 22, as shown in fig. 3K, and singulation is performed to complete the semiconductor ultra-thin stacked structure 52 shown in fig. 3L.
In the method for manufacturing the semiconductor ultra-thin stacked structure of the first, second and third embodiments, the stop layer structure is manufactured by sequentially implanting nitrogen ions and oxygen ions and performing a high temperature treatment to form a silicon nitride layer and a silicon dioxide layer, but not limited thereto, in one embodiment, the stop layer structure may only include a silicon nitride layer, that is, a high temperature treatment process is performed after a nitrogen ion implantation process is performed in the semiconductor substrate, so as to form a silicon nitride layer at a depth of 1 to 5 micrometers from the active surface; correspondingly, the stop layer removal step of the subsequent first/second thinning process only needs to remove the silicon nitride layer, and other subsequent processes are the same and are not described again.
In the embodiment of the present invention, by forming the stop layer structure at a depth of the semiconductor substrate, and by performing the substrate removing step and the stop layer structure step by step in the subsequent thinning process, the semiconductor substrate can be reliably polished or etched until only the first portion of the substrate is retained, that is, only the substrate thickness of 1 to 5 micrometers is retained, so that the overall thickness of each semiconductor chip layer is not greater than 12 micrometers, and under the limitation that the total thickness of the chip is limited to 700 micrometers, 50 layers of thinned semiconductor chip layers can be stacked in the semiconductor ultra-thin stacked structure 28 in the embodiment of the present invention, which can meet the requirements of high integration and speed, and has better electrical characteristics and efficiency.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (16)

1. A method for fabricating a semiconductor ultra-thin stack structure, comprising:
manufacturing a plurality of semiconductor wafers, wherein one of the semiconductor wafers is selected as a first semiconductor wafer of the bottom layer, and the other part of the semiconductor wafers is used as a second semiconductor wafer and at least one third semiconductor wafer to be stacked, and each manufacturing step of the semiconductor wafers comprises the following steps: providing a semiconductor substrate having an active surface and a back surface opposite to each other; forming a stop layer structure in the semiconductor substrate, dividing the semiconductor substrate into a first substrate part and a second substrate part, wherein the first substrate part is positioned between the stop layer structure and the active surface, the second substrate part is positioned between the stop layer structure and the back surface, the stop layer structure at least comprises a silicon nitride layer, the manufacturing of the silicon nitride layer comprises a nitrogen ion injection process performed at a first depth of the semiconductor substrate, and then a high-temperature treatment process is performed, so that the nitrogen ion injection region forms the silicon nitride layer; and disposing a plurality of electrical elements on the active surface to form an interconnect layer, the interconnect layer including a plurality of interconnect points, and disposing a plurality of conductive structures on the first portion of the substrate to connect the interconnect layer and the stop layer;
flipping the second semiconductor wafer over the first semiconductor wafer such that the interconnect layer of the first semiconductor wafer and the interconnect layer of the second semiconductor wafer are opposite and bonded together by a hybrid bonding technique;
performing a first back side grinding process to grind the back side of the second semiconductor wafer to remove a portion of the second portion of the substrate of the second semiconductor wafer;
performing a first thinning process to form a thinned second semiconductor wafer;
performing a second back grinding process to grind the back of the first semiconductor wafer to remove a portion of the second portion of the substrate of the first semiconductor wafer; and
performing a second thinning process to form a thinned first semiconductor wafer, wherein the first thinning process and the second thinning process comprise: a substrate removing step, removing the remaining second part of the substrate to expose the stop layer structure; and a stop layer removing step, removing the stop layer structure to expose the first part of the substrate and the conductive structures.
2. The method of claim 1, further comprising stacking a plurality of thinned third semiconductor wafers on the thinned second semiconductor wafer in sequence before the second backside grinding process, wherein each stacking step of the thinned third semiconductor wafers comprises:
flipping the third semiconductor wafer upside down relative to the first semiconductor wafer such that the interconnect layer of the third semiconductor wafer and the first portion of the substrate of the thinned second semiconductor wafer are opposed and bonded together;
performing a third back side grinding process to grind the back side of the third semiconductor wafer to remove a portion of the second portion of the substrate of the third semiconductor wafer; and
a third thinning process is performed, including the substrate removing step and the stop layer removing step.
3. The method of claim 1, wherein the stop layer further comprises a silicon dioxide layer disposed on the silicon nitride layer between the silicon nitride layer and the active surface.
4. The method of claim 3, wherein the step of forming the silicon dioxide layer comprises: after the nitrogen ion implantation process, firstly, an oxygen ion implantation process is carried out on the semiconductor substrate at a second depth, wherein the second depth is smaller than the first depth, and then the high-temperature treatment process is carried out, so that the silicon dioxide layer is formed in the oxygen ion implanted region.
5. The method of claim 4, wherein said stop layer removing step comprises: the silicon nitride layer is removed first, and then the silicon dioxide layer is removed.
6. The method as claimed in claim 5, wherein the substrate removing step is selected from one of chemical mechanical polishing, wet etching and plasma dry etching, wherein the selectivity of Si to SiN is between 20 and 80.
7. The method as claimed in claim 5, wherein the silicon nitride layer and the silicon dioxide layer are removed by one of chemical mechanical polishing and plasma dry etching, wherein the selectivity of silicon nitride to silicon dioxide is between 10 and 20, and the selectivity of silicon dioxide to silicon is 5.
8. The method of claim 1, wherein the stop layer structure is spaced from the active surface by a distance of 1 micron to 5 microns, and the thinned second semiconductor wafer has a thickness of no greater than 12 microns.
9. The method of claim 1, further comprising, after forming the thinned first semiconductor wafer:
arranging a plurality of solder balls on one side of the thinned first semiconductor wafer far away from the thinned second semiconductor wafer so as to be respectively electrically connected with the conductive structures; and
and performing electrical test and singulation.
10. A method for fabricating a semiconductor ultra-thin stack structure, comprising:
fabricating a plurality of semiconductor wafers, each of the plurality of semiconductor wafers comprising: providing a semiconductor substrate having an active surface and a back surface opposite to each other; forming a stop layer structure in the semiconductor substrate, dividing the semiconductor substrate into a first substrate part and a second substrate part, wherein the first substrate part is positioned between the stop layer structure and the active surface, the second substrate part is positioned between the stop layer structure and the back surface, the stop layer structure at least comprises a silicon nitride layer, the manufacturing of the silicon nitride layer comprises a nitrogen ion implantation process performed at a first depth prior to the semiconductor substrate, and then a high-temperature treatment process is performed, so that the silicon nitride layer is formed in a region where the nitrogen ions are implanted; and disposing a plurality of electrical elements on the active surface to form an interconnect layer, the interconnect layer including a plurality of interconnection points, and disposing a plurality of conductive structures on the first portion of the substrate to connect the interconnect layer and the stop layer;
selecting one of the semiconductor wafers as a first semiconductor wafer of the bottom layer, and cutting the other part of the semiconductor wafers to be used as a first batch of semiconductor chips and at least one second batch of semiconductor chips to be stacked;
flipping the first batch of semiconductor chips relative to the first semiconductor wafer so that the interconnect layer of the first batch of semiconductor chips and the interconnect layer of the first semiconductor wafer are opposite and bonded together by a hybrid bonding technique;
performing a first molding process to form a first encapsulant on the first semiconductor wafer to encapsulate the first semiconductor chips;
performing a first back grinding process to remove a portion of the first encapsulant and a portion of the second portion of the substrate of the first batch of semiconductor chips from a side of the first encapsulant away from the first semiconductor wafer;
performing a first thinning process to form a first semiconductor chip layer;
performing a second back grinding process to grind the back surface of the first semiconductor wafer to remove a portion of the second portion of the substrate of the first semiconductor wafer; and
performing a second thinning process to form a thinned first semiconductor wafer, wherein the first thinning process and the second thinning process comprise: a substrate removing step, removing the remaining second part of the substrate to expose the stop layer structure; and a stop layer removing step, removing the stop layer structure to expose the first part of the substrate and the conductive structures.
11. The method of claim 10, further comprising sequentially stacking at least one second semiconductor die on the first semiconductor die prior to performing the second back grinding process, wherein each second semiconductor die stacking step comprises:
flipping the at least one second semiconductor chip relative to the first semiconductor wafer such that the interconnect layer of the at least one second semiconductor chip is opposite to and bonded to the first portion of the substrate of the first semiconductor chip layer;
performing a second molding process to form a second encapsulant on the first semiconductor chip layer to encapsulate the second semiconductor chips;
performing a third backside grinding process to remove a portion of the second encapsulant from a side of the second encapsulant away from the first semiconductor chip layer and to remove a portion of the second portion of the substrate of the second plurality of semiconductor chips; and
a third thinning process is performed, including the substrate removing step and the stop layer removing step.
12. The method of claim 10, further comprising, after forming the thinned first semiconductor wafer:
arranging a plurality of solder balls on one side of the thinned first semiconductor wafer, which is far away from the first semiconductor chip layer, so as to be respectively electrically connected with the conductive structures; and performing electrical test and singulation.
13. A method for fabricating a semiconductor ultra-thin stack structure, comprising:
providing a bearing plate, and forming a plurality of first conductive columns on the bearing plate;
providing a plurality of semiconductor chips, each of the semiconductor chips comprising: providing a semiconductor substrate having an active surface and a back surface opposite to each other; forming a stop layer structure in the semiconductor substrate, dividing the semiconductor substrate into a first substrate part and a second substrate part, wherein the first substrate part is positioned between the stop layer structure and the active surface, the second substrate part is positioned between the stop layer structure and the back surface, the stop layer structure at least comprises a silicon nitride layer, the manufacturing of the silicon nitride layer comprises a nitrogen ion implantation process performed at a first depth prior to the semiconductor substrate, and then a high-temperature treatment process is performed, so that the silicon nitride layer is formed in a region where the nitrogen ions are implanted; arranging a plurality of electric elements and an interconnection layer on the active surface, wherein the interconnection layer comprises a plurality of interconnection points, and arranging a plurality of conductive structures on the first part of the substrate to connect the interconnection layer and the stop layer structure; and performing singulation;
selecting a first batch of semiconductor chips and at least one second batch of semiconductor chips from the semiconductor chips, wherein the first batch of semiconductor chips comprises a plurality of first semiconductor chips, and the at least one second batch of semiconductor chips comprises a plurality of second semiconductor chips;
the first semiconductor chips are arranged on the bearing plate in an inverted mode, the first conductive columns are arranged between the adjacent first semiconductor chips, the interconnection layer of the first semiconductor chips is adjacent to the bearing plate, and the semiconductor substrate is far away from the bearing plate;
performing a first molding process to form a first encapsulant on the carrier plate to encapsulate the first semiconductor chips and the first conductive pillars;
performing a first back grinding process to remove a portion of the first encapsulant and a portion of the second portion of the substrate of the first semiconductor chips from a side of the first encapsulant away from the carrier;
performing a first thinning process to form a first semiconductor chip layer, wherein the first thinning process comprises sequentially removing the remaining second portions of the substrate and the stop layer structures of the first batch of semiconductor chips to expose the first portions of the substrate, the conductive structures and the first conductive pillars;
arranging a plurality of second conductive columns to be electrically connected with part of the conductive structures of the first semiconductor chip layer;
the second batch of semiconductor chips are arranged on the first semiconductor chip layer in a flip-chip mode, wherein the second semiconductor chips are respectively bridged between the adjacent first semiconductor chips, the interconnection layers of the second semiconductor chips are electrically connected with the exposed first conductive columns and part of the conductive structures of the first semiconductor chip layer, and part of the second conductive columns are arranged between the adjacent second semiconductor chips;
performing a second molding process to form a second encapsulant on the first semiconductor chip layer to encapsulate the second semiconductor chips and the second conductive pillars;
performing a second back grinding process to remove a portion of the second encapsulant from a side of the second encapsulant away from the first semiconductor chip layer and to remove a portion of the second portion of the substrate of the second batch of semiconductor chips;
performing a second thinning process to form a second semiconductor chip layer, wherein the second thinning process includes sequentially removing the remaining second portions of the substrate and the stop layer structure of the second batch of semiconductor chips to expose the first portions of the substrate, the conductive structures and the second conductive pillars; and
the carrier is removed to expose the interconnect layer of the first semiconductor chip layer and the first conductive pillars.
14. The method of claim 13, further comprising the step of removing the carrier plate by:
arranging a plurality of solder balls on one side of the first semiconductor chip layer, which is far away from the second semiconductor chip layer, so as to electrically connect the interconnection layer and the first conductive posts respectively; and performing singulation.
15. The method of claim 13, wherein the first semiconductor chips of the first plurality of semiconductor chips have different electrical functions.
16. The method of claim 13, wherein the second semiconductor chips of the second plurality of semiconductor chips have different electrical functions.
CN202110544381.XA 2021-05-19 2021-05-19 Method for manufacturing semiconductor ultrathin stack structure Pending CN115376938A (en)

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