CN115327333A

CN115327333A - Addressable test array

Info

Publication number: CN115327333A
Application number: CN202210962772.8A
Authority: CN
Inventors: 林曦; 沈忱; 伍宏
Original assignee: Fangsiwei Shanghai Semiconductor Co ltd
Current assignee: Suzhou Peifengtunan Semiconductor Co ltd
Priority date: 2022-08-11
Filing date: 2022-08-11
Publication date: 2022-11-11
Also published as: WO2024031797A1

Abstract

The invention discloses an addressable test array, which is used for solving the problems of low test structure area and low time utilization rate in the test process, and comprises a plurality of addressable control on-off low-leakage switches, wherein each low-leakage switch comprises: the drain end of the first MOS tube is connected to the drain end voltage signal wire; a second MOS tube, the drain terminal of which is connected to a signal protection path, the signal protection path is configured to be equal to the voltage on the drain terminal voltage signal wire; the well end voltage of the first MOS tube and the second MOS tube is configured to be equal to the voltage on the signal protection path, and the source ends of the first MOS tube and the second MOS tube are interconnected; each low leakage switch is configured to: loading a first voltage control signal at the grid end of the first MOS tube to enable the first MOS tube to be conducted, and loading a second voltage control signal at the grid end of the second MOS tube to enable the second MOS tube to be closed, wherein the low leakage switch is conducted; and when the grid end of the second MOS tube loads the second voltage-controlled signal to conduct the second voltage-controlled signal, the low leakage switch is switched off.

Description

Addressable test array

Technical Field

The invention belongs to the technical field of semiconductor testing, and particularly relates to an addressable test array.

Background

During semiconductor development, it is often desirable to test process maturity and semiconductor device performance using semiconductor test structures. Referring to fig. 1, a conventional test structure includes pads (pads) for connecting test lines led out from ports of a device under test, and the pads are contacted by probes connected to a meter to read corresponding measurement data.

In such a test structure, for example, the size of the device under test is 1 μm × 1 μm, and the size of one Pad is 60 μm × 60 μm, since one device under test needs to test by 2 to 4 or more pads, most of the area of the test structure is occupied by the pads, and the area utilization rate of the test structure is very low. In addition, when different devices to be tested are tested, mechanical parts such as a motor and the like are also required to move the probe to the Pad of other test structures; in some cases, the probe moving process time may be longer than the measurement time, so that the time utilization efficiency of the test process is also low.

Disclosure of Invention

The invention aims to provide an addressable test array, which is used for solving the problems of low area utilization rate of the current test structure and low time utilization rate of the test process.

To achieve the above object, the present invention provides an addressable test array for testing a plurality of devices under test, including a plurality of low leakage switches which can be addressable to control switching, each of the low leakage switches including:

the drain end of the first MOS tube is connected to a drain end voltage signal line;

a second MOS tube, wherein the drain terminal of the second MOS tube is connected to a first signal protection path, and the first signal protection path is configured to be equal to the voltage on a drain terminal voltage signal wire;

the well end voltage of the first MOS tube and the second MOS tube is configured to be equal to the voltage on the first signal protection path, and the source ends of the first MOS tube and the second MOS tube are interconnected and used for connecting a device to be tested; each of the low leakage switches is configured to:

loading a first voltage control signal at the grid end of the first MOS transistor to enable the first MOS transistor to be conducted, and loading a second voltage control signal at the grid end of the second MOS transistor to enable the second MOS transistor to be closed, wherein the low leakage switch is conducted;

and when a first voltage control signal is loaded at the grid end of the first MOS transistor to close the first MOS transistor and a second voltage control signal is loaded at the grid end of the second MOS transistor to close and conduct the second MOS transistor, the low leakage switch is switched off.

In one embodiment, the first signal protection path replicates the voltage on the drain voltage signal line through a voltage follower buffer; or the like, or a combination thereof,

the drain terminal voltage signal line and the first signal protection path are respectively connected to the bonding pads with equal voltage.

In one embodiment, the well terminal of the first MOS transistor is connected to the drain terminal voltage signal line or the first signal protection path, and the well terminal of the second MOS transistor is connected to the drain terminal voltage signal line or the first signal protection path.

In one embodiment, the well terminals of the first and second MOS transistors are connected to each other and to the drain terminal voltage signal line or the first signal protection path.

In one embodiment, the first signal protection path is disposed around a peripheral side of the drain voltage signal line in an extending direction of the drain voltage signal line.

In one embodiment, each of the low leakage switches further includes a high resistance voltage measurement loop capable of being controlled to be switched on and off, one end of the high resistance voltage measurement loop is connected to the source end of the first MOS transistor, and the other end of the high resistance voltage measurement loop is connected to the drain end induction signal line;

wherein the addressable test array further comprises a second signal protection path configured to be equal to a voltage on the drain sense signal line.

In an embodiment, the high-resistance voltage measurement circuit includes a third MOS transistor, a source of the third MOS transistor is connected to a source of the first MOS transistor, a drain of the third MOS transistor is connected to the drain sense signal line, a gate of the third MOS transistor is interconnected with a gate of the first MOS transistor, and a well of the third MOS transistor is connected to the second signal protection path.

In one embodiment, the second signal protection path copies the voltage on the drain sense signal line through a voltage follower buffer; or the like, or, alternatively,

the drain end induction signal line and the second signal protection path are respectively connected to the bonding pads with equal voltage.

In one embodiment, in the extending direction of the drain sensing signal line, the second signal protection path is disposed to surround the periphery of the drain sensing signal line.

The invention also provides an addressable test array, which is used for testing a plurality of devices to be tested and comprises a plurality of low-leakage switches which can be controlled to be switched on and off in an addressable mode, wherein each low-leakage switch comprises:

one end of the high-resistance voltage measuring loop is connected to the source end of the first MOS tube, and the other end of the high-resistance voltage measuring loop is connected to a drain end induction signal line;

the drain end of the second MOS tube is connected to the signal protection path;

the voltage of the well ends of the first MOS tube and the second MOS tube is configured to be equal to the voltage on the signal protection path, and the source ends of the first MOS tube and the second MOS tube are interconnected and used for connecting a device to be tested; each of the low leakage switches is configured to:

the drain end of the second MOS tube can be controllably connected to the drain end voltage signal line or the drain end induction signal line;

a signal protection path configured to be equal to a voltage on a drain side voltage signal line and a drain side sense signal line;

the well end voltage of the first MOS tube and the second MOS tube is configured to be equal to the voltage on the signal protection path, and the source ends of the first MOS tube and the second MOS tube are interconnected and used for connecting a device to be tested; each of the low leakage switches is configured to:

In an embodiment, the high-resistance voltage measurement circuit includes a third MOS transistor, a source of the third MOS transistor is connected to a source of the first MOS transistor, a drain of the third MOS transistor is connected to the drain sense signal line, a gate of the third MOS transistor is interconnected with a gate of the first MOS transistor, and a well of the third MOS transistor is connected to the signal protection path.

In one embodiment, the signal protection path copies the voltage on the drain sense signal line or the drain voltage signal line through a voltage follower buffer; or the like, or a combination thereof,

and the drain end induction signal line, the drain end voltage signal line and the signal protection path are respectively connected to the pads with equal voltage.

In one embodiment, the signal protection path is disposed around the drain voltage signal line and the drain sensing signal line in the extending direction of the drain voltage signal line and the drain sensing signal line.

In one embodiment, the plurality of low leakage switches, the drain voltage signal line, the drain sense signal line, and the signal protection path form an addressable test circuit, and the addressable test array includes:

the addressable test circuit is used for being connected to the drain terminals of a plurality of devices to be tested; and/or the presence of a gas in the atmosphere,

the addressable test circuit is used for being connected to the grid ends of a plurality of devices to be tested; and/or the presence of a gas in the gas,

the addressable test circuit is used for connecting to a plurality of device source terminals to be tested; and/or the presence of a gas in the gas,

the addressable test circuit is used for being connected to the well ends of a plurality of devices to be tested.

In one embodiment, the addressable test array further comprises a coaxial cable connected between the probe and the dashboard, and the outer portion of the coaxial cable replicates the voltage of the lead-out wire at the device under test via a voltage following buffer.

Compared with the prior art, the addressable test array can selectively switch on and off the devices to be tested connected with each low leakage switch according to the test requirement by arranging the plurality of addressable control on-off low leakage switches, and the test ends of the plurality of devices to be tested can share the Pad, so that the area of a test structure and the time utilization rate of the test process are improved;

on the other hand, because the signal protection circuit of the testable array is configured to be equal to the voltage on the drain voltage signal line, the drain leakage inherent to the first MOS transistor when the low leakage switch is switched off and the drain-to-well leakage of the first MOS transistor when the low leakage switch is switched on can be eliminated;

on the other hand, the signal protection path of the addressable test is arranged to surround the periphery of the drain end voltage signal line and the drain end induction signal line, and the signal protection path, the drain end voltage signal line and the drain end induction signal line have equal voltage, so that the influence of electric leakage on the drain end voltage signal line and the drain end induction signal line on the measurement result can be reduced;

on the other hand, the coaxial cable between the addressable test array connection probe and the instrument panel copies the electric wire of the lead-out wire at the current device to be tested through the voltage following buffer, so that the potential difference between the lead at the device to be tested and the coaxial cable is eliminated, and the electric leakage of the external coaxial cable is reduced;

on the other hand, the addressable test array can be set to be multi-end addressable according to the requirements of the devices to be tested, so that the phenomenon that when the low-leakage switch is in an off and on intermediate state, the leakage of other ends of the devices to be tested is accumulated to the signal protection path and finally flows into the shared end of the current devices to be tested to cause influence on detection is reduced.

Drawings

FIG. 1 is a schematic diagram of a prior art semiconductor test structure;

FIG. 2 is a schematic diagram of one embodiment of an addressable test array;

FIG. 3 is a schematic diagram of an addressable test array according to an embodiment of the present application;

FIG. 4 is a schematic diagram of an addressable test array according to yet another embodiment of the present application;

FIG. 5 is a schematic diagram of a structure of a signal protection path surrounding a drain voltage signal line in an addressable test array according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of an addressable test array with addressable drain and gate terminals according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a four-terminal addressable test array according to an embodiment of the present application;

FIG. 8 is a schematic structural diagram of an addressable test array according to an embodiment of the present disclosure;

FIG. 9 is a schematic structural diagram of an addressable test array according to yet another embodiment of the present application;

FIG. 10 is a schematic diagram of a four-terminal addressable test array according to yet another embodiment of the present application;

FIG. 11 is a schematic structural diagram of an addressable test array according to yet another embodiment of the present application;

FIG. 12 is a schematic circuit diagram of a 32X 1 row-column addressable test array according to the present application.

Detailed Description

Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the specific embodiments.

Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.

Referring to fig. 2, a common Pad test array is described. Taking the device to be tested with a gate terminal (G), a source terminal (S), a drain terminal (D), and a well terminal (B) as an example, the gate terminals, the source terminals, and the well terminals of a plurality of devices to be tested can be connected to a common Pad (Pad), while the drain terminal that cannot be multiplexed is connected to another Pad through a plurality of switches. The test array can control whether the switch is communicated with the drain end of the device to be tested or not through the controller, and only one device to be tested can be selected to be tested by the test array at the same moment.

Referring to FIG. 3, an embodiment of an addressable test array 100 of the present application is described. In this embodiment, the addressable test array 100 includes a plurality of low leakage switches 11 that can be addressable to control switching.

The addressable test array 100 may be used for testing of a plurality of devices under test, typically one device under test for each low leakage switch 11. It should be noted that, according to the different devices to be tested, the number of the test ports corresponding to each device to be tested may also be different, and the phrase "each low leakage switch 11 corresponds to one device to be tested" here means that the low leakage switch 11 only correspondingly controls to communicate with the device to be tested or a certain port of the device to be tested.

Each low leakage switch 11 comprises two MOS transistors: a first MOS transistor 111 and a second MOS transistor 112. The drain terminal of the first MOS transistor 111 is connected to the drain terminal voltage signal line 12, the drain terminal of the second MOS transistor 112 is connected to the first signal protection path 131, and the well terminal voltages of the first MOS transistor 111 and the second MOS transistor 112 are configured to be equal to the voltage on the first signal protection path 131, and the source terminals of the first MOS transistor 111 and the second MOS transistor 112 are interconnected.

In such a low leakage switch 11, the gate terminals of the first MOS transistor 111 and the second MOS transistor 112 may be loaded with different voltage control signals to control the on/off of the whole low leakage switch 11. Specifically, when a first voltage control signal is applied to the gate terminal of the first MOS transistor 111 to turn on the first MOS transistor 111, and a second voltage control signal is applied to the gate terminal of the second MOS transistor 112 to turn off the second MOS transistor 112, the low leakage switch 11 is turned on; correspondingly, when the first voltage control signal is applied to the gate terminal of the first MOS transistor 111 to turn off the first MOS transistor 111, and the second voltage control signal is applied to the gate terminal of the second MOS transistor 112 to turn off the second MOS transistor 112, the low leakage switch 11 is turned off.

Taking the measurement of the current and voltage at the drain of the dut as an example, a corresponding voltage may be applied to the drain of the dut, and the corresponding current and voltage may be measured at a suitable location on the drain voltage signal line 12.

In the low leakage switch 11 of the above structure, there is still a possibility of leakage. The method comprises the following steps: (1) when the low leakage switch 11 is turned off, the inherent drain terminal of the first MOS transistor 111 leaks to the source terminal; (2) when the low leakage switch 11 is turned on, the drain terminal of the first MOS transistor 111 leaks to the well terminal. Correspondingly, in the present embodiment, the first signal protection path 131 is configured to be equal to the voltage on the drain terminal voltage signal line 12, so as to eliminate the leakage.

Specifically, the drain leakage inherent to the first MOS transistor 111 when the low leakage switch 11 is turned off includes: drain to well leakage, drain to source leakage, and well to source leakage. At this time, since the second MOS transistor 112 is in the on state and the well terminal voltage of the first MOS transistor 111 is equal to the voltage on the drain terminal voltage signal line 12, the drain terminal voltage, the well terminal voltage, and the source terminal voltage of the first MOS transistor 111 are pulled to be equal, thereby effectively eliminating the source terminal leakage inherent to the first MOS transistor 111 at this time. Similarly, for the drain-to-well leakage of the first MOS transistor 111 when the low leakage switch 11 is turned on, the drain-to-well leakage can also be effectively eliminated because the well terminal voltage of the first MOS transistor 111 is pulled to be equal to the drain terminal voltage.

In a specific structure, the first signal protection path 131 may be a voltage replica on the drain voltage signal line 12 through the voltage follower buffer 15 as shown in fig. 3, or the drain voltage signal line 12 and the first signal protection path 131 may be connected to pads of equal voltage, respectively, as shown in fig. 4.

In this embodiment, each of the low leakage switches 11 may be disposed in a deep well for isolation from the substrate, thereby eliminating the well-to-substrate leakage. In the above embodiment, the first MOS transistor 111 and the second MOS transistor 112 may select an NMOS transistor or a PMOS transistor according to different application scenarios to construct the basic function of the low leakage switch 11.

Taking the first MOS transistor 111 and the second MOS transistor 112 in the low leakage switch 11 as NMOS as an example, in such an embodiment, the low leakage switch 11 may be disposed in a Deep N-WELL (DNW). Because the NMOS is manufactured on the P-type substrate, the crosstalk of current noise passing through the P-type substrate can be effectively eliminated through the isolation of the deep N well.

Continuing to refer to fig. 3, in this embodiment, the well terminals of the first and

second MOS transistors

111 and 112 are interconnected and connected to the first signal protection path 131 to achieve that both well terminal voltages are equal to the voltage on the first signal protection path 131.

In some alternative embodiments, since the voltages on the drain terminal voltage signal line 12 and the first signal protection path 131 are equal, the well terminals of the first MOS transistor 111 and the second MOS transistor 112 may be connected to the drain terminal voltage signal line 12 after being interconnected, or the well terminals of the first MOS transistor 111 and the second MOS transistor 112 may not be interconnected, the well terminal of the first MOS transistor 111 may be selectively connected to the drain terminal voltage signal line 12 or the first signal protection path 131, and the well terminal of the second MOS transistor 112 may be selectively connected to the drain terminal voltage signal line 12 or the first signal protection path 131.

In this embodiment, the addressable test array 100 further includes a coaxial cable (not shown) connected between the probe and the dashboard, the outer portion of which replicates the voltage of the lead at the device under test via a voltage follower buffer. Thus, no potential difference exists between the lead and the coaxial cable at the position of the current device to be tested, and the leakage of the external coaxial cable on the path is reduced to the maximum extent.

It should be noted that, the "lead wire led out from the device under test at present" mentioned herein refers to a lead wire led out from the testing end of the device under test at present. For example, when the addressable test array 100 measures the drain current of a MOS transistor, the addressable test array 100 has a segment of conducting wire connected to the drain of the MOS transistor, and this segment of conducting wire is understood as the lead-out conducting wire at the MOS transistor.

Referring to fig. 5 in cooperation, in the present embodiment, the first signal protection path 131 is provided around the peripheral side of the drain voltage signal line 12 in the extending direction of the drain voltage signal line 12. When the leakage current of the device under test is measured, the leakage current on the drain terminal voltage signal line 12 will also affect the measurement result, especially when the device under test is turned off, the leakage current strength is close to the weak current strength flowing through the circuit. By arranging the first signal protection path 131 around the periphery of the drain voltage signal line 12, the measurement error source can be effectively eliminated because the voltages of the two are equal.

In the present embodiment, the plurality of low leakage switches 11, the drain terminal voltage signal line 12, and the first signal protection path 131 together constitute an addressable test circuit. In the embodiment shown in fig. 3, addressable test array 100 includes the addressable test circuitry connected to the drains of a plurality of devices under test, i.e., addressable test array 100 implements "drain-addressable" addressing of a plurality of devices under test via the addressable test circuitry.

In the embodiment with only the addressable drain terminal, no leakage can be realized when the low-leakage switch 11 is switched off and on, and the leakage measurement of the device to be tested is not influenced. However, all the devices to be tested share the gate terminal control, all the devices to be tested are controlled simultaneously, the current of the corresponding port of the currently-tested device which is selected to be conducted is on the drain terminal voltage signal line 12, and the electric leakage of other terminals of all the devices to be tested flows into the first signal protection circuit 131 to be accumulated, for example, the electric leakage can reach milliampere level, and finally flows to the gate terminal of the currently-tested device, which will affect the electric leakage detection of the currently-tested device.

To address the above challenges, and in conjunction with fig. 6, in one embodiment, addressable test array 100 may be configured to be "gate-addressable," i.e., to include the addressable test circuits described above, which may be coupled to the gates of a plurality of devices under test. Therefore, when the corresponding end (such as a drain end) of the current device to be measured is measured, the low leakage switch 11 corresponding to the gate end of the other device to be measured can be disconnected, so that the leakage current is blocked at the low leakage switch 11, the current is prevented from flowing to the gate end of the current device to be measured, and the accuracy of the current measurement of the corresponding end of the device to be measured is ensured.

By analogy, in the embodiment where the device to be detected shares the source terminal and the well terminal, in the intermediate state between the turn-off and the turn-on of the low leakage switch 11, the accumulated leakage may also flow into the source terminal and the well terminal of the current device to be detected, and may also affect the leakage detection of the current device to be detected.

Similarly, referring to fig. 7, in one embodiment, the addressable array may be configured to be "source addressable and well addressable," i.e., to include the addressable test circuit described above that may be coupled to the source terminals of a plurality of devices under test, and the addressable test circuit described above that may be coupled to the well terminals of a plurality of devices under test.

In the above embodiments/embodiments, the source terminals of the first MOS transistor 111 and the second MOS transistor 112 in each low-leakage switch 11 are interconnected to be used for connecting the device under test, that is, the source terminals of the first MOS transistor 111 and the second MOS transistor 112 are interconnected to form a "connection terminal" of the low-leakage switch 11 for connecting the device under test. For example, in a drain addressable embodiment, the connection is connected to the drain of each dut; in the same way, in the embodiment that the addressable terminals are provided at other terminals, the connection terminals of the low leakage switches 11 in the corresponding addressable circuits are also respectively connected to the corresponding terminals of the device under test. In addition, in the above embodiments/examples, the addressable setting of the addressable test array 100 for a specific end of a device under test may be determined according to factors such as test accuracy requirements and cost.

Referring to fig. 8, in this embodiment, the addressable test array 100 may further include a second signal protection path 132, and a high-resistance voltage measurement loop capable of controlling opening and closing, where one end of the high-resistance voltage measurement loop is connected to the source terminal of the first MOS transistor 111, the other end of the high-resistance voltage measurement loop is connected to the drain terminal sensing signal line 14, and the second signal protection path 132 is configured to be equal to the voltage on the drain terminal sensing signal line 14.

Similarly, taking the example of measuring the voltage at the drain of the dut, a corresponding voltage may be applied to the drain of the dut and measured at the voltage measurement terminal on the drain sense signal line 14 (DS in fig. 8).

As used herein, a "high resistance voltage measurement loop" may refer to a measurement loop that can be connected to a measurement instrument having an extremely high input resistance, such that the current flowing therethrough can approach zero during measurement. Because the low leakage switch 11 may flow a current at a milliampere level in a conducting state, and the inherent on-resistance of the low leakage switch 11, the current at the milliampere level may cause an obvious voltage transmission loss, and finally, an error may occur in a leakage current measurement result. The voltage measurement of the drain sensing signal line 14 is configured to be connected to a high-voltage resistance measurement circuit, so that the interference of the resistance of the addressable test array 100 can be eliminated, and the voltage on the drain voltage signal line 12 does not affect the voltage on the high-resistance voltage measurement circuit, so that the voltage of the device to be measured can be accurately measured at the voltage measurement end of the drain sensing signal line 14.

It can be seen that, by the high resistance voltage measurement circuit, the voltage of the device to be measured can be measured on the drain terminal sensing signal line 14, and the measurement of the current of the device to be measured on the drain terminal voltage signal line 12 is not affected.

In different embodiments, the high-resistance voltage measurement loop can be implemented in various forms, for example, a resistor with an extremely high resistance value can be connected in series to the loop, or alternatively, a high-resistance voltmeter can be directly configured at the voltage measurement end of the drain terminal sensing signal line 14 for voltage measurement. It can be seen that the "high-resistance voltage measurement loop" may have a high-resistance characteristic itself, or may be used in combination with an external high-resistance measurement apparatus to implement high-resistance measurement.

It should be noted that the "current measuring terminal" and the "voltage measuring terminal" mentioned in the embodiments/examples of the present application are not limited to the existence of the structure or the component set for measuring the current or the voltage; in practice, the current measuring terminal and the voltage measuring terminal may be, for example, at any suitable positions on the corresponding signal lines.

With reference to fig. 8, in this embodiment, the high-resistance voltage measurement circuit includes a third MOS transistor 113, and the third MOS transistor 113 controls on/off of the high-resistance voltage measurement circuit. Specifically, the source terminal of the third MOS transistor 113 is connected to the source terminal of the first MOS transistor 111, the drain terminal of the third MOS transistor 113 is connected to the drain terminal sensing signal line 14, the gate terminal of the third MOS transistor 113 is interconnected with the gate terminal of the first MOS transistor 111, and the well terminal of the third MOS transistor 113 is connected to the second signal protection path 132.

When a certain device to be tested is selected for measurement in the addressable test array 100, the corresponding low leakage switch 11 is turned on, and the first voltage control signal is simultaneously loaded on the gate ends of the first MOS transistor 111 and the third MOS transistor 113, so that the first MOS transistor 111 and the third MOS transistor 113 are turned on; the second voltage-controlled signal is loaded at the gate terminal of the second MOS transistor 112, so that the second MOS transistor 112 is turned off, and the measurement of the current and the voltage of the corresponding port of the device to be measured is realized.

Correspondingly, when the low leakage switch 11 is turned off, the first voltage control signal simultaneously controls the first MOS transistor 111 and the third MOS transistor 113 to be turned off, and the second voltage control signal controls the second MOS transistor 112 to be turned on, so as to maintain the low leakage characteristic of the low leakage switch 11 in the off state.

In the extending direction of the drain sensing signal line 14, the second signal protection path 132 is disposed to surround the periphery of the drain sensing signal line 14, so as to also reduce the influence of the leakage on the drain sensing signal line 14 on the measurement result.

In this embodiment, the second signal protection path 132 may duplicate the voltage on the drain sensing signal line 14 through a voltage follower buffer, or the drain sensing signal line 14 and the second signal protection path 132 may be connected to pads of equal voltage, respectively.

It can be understood that, after the drain sensing signal line 14 is added in the addressable test array 100, the drain sensing signal line 14 may also be a component of the addressable test circuit, and cooperatively, the addressable test array 100 implements "multi-terminal addressing" of the multiple devices under test through the addressable test circuit.

Referring to FIG. 9, yet another embodiment of an addressable test array 200 of the present application is described. In this embodiment, the addressable test array 200 includes a plurality of addressable controlled on/off low leakage switches 11.

Similarly to the previous embodiment, each low leakage switch 11 includes a first MOS transistor 111 and a second MOS transistor 112, a drain terminal of the first MOS transistor 111 is connected to the drain terminal voltage signal line 12, a drain terminal of the second MOS transistor 112 is connected to the signal protection path 13, and a well terminal voltage of the first MOS transistor 111 and the second MOS transistor 112 is configured to be equal to a voltage on the signal protection path 13, and source terminals of the first MOS transistor 111 and the second MOS transistor 112 are interconnected and used for connecting a device under test.

Taking the example of measuring the current at the drain of the dut, a corresponding voltage may be applied to the drain voltage signal line 12 (DF in fig. 9), and the low leakage switch connected thereto is set to the on state, and then the corresponding current is measured at the current measuring terminal on the drain voltage signal line 12 (DF in fig. 9).

In this embodiment, the addressable test array 200 also includes a high-resistance voltage measurement loop capable of controlling opening and closing, one end of the high-resistance voltage measurement loop is connected to the source end of the first MOS transistor 111, and the other end is connected to the drain end sensing signal line 14.

Similarly, taking the example of measuring the voltage at the drain of the dut, a corresponding voltage may be applied to the drain of the dut and measured at the voltage measurement terminal on the drain sense signal line 14 (DS in fig. 9).

With reference to fig. 9, in this embodiment, the high-resistance voltage measurement circuit includes a third MOS transistor 113, and the third MOS transistor 113 controls on/off of the high-resistance voltage measurement circuit. Specifically, the source terminal of the third MOS transistor 113 is connected to the source terminal of the first MOS transistor 111, the drain terminal of the third MOS transistor 113 is connected to the drain terminal sensing signal line 14, the gate terminal of the third MOS transistor 113 is interconnected with the gate terminal of the first MOS transistor 111, and the well terminal of the third MOS transistor 113 is connected to the signal protection path 13 (GRD in fig. 9).

When the addressable test array 100 selects a certain device to be tested for measurement, the corresponding low leakage switch 11 is turned on, and the first voltage control signal is simultaneously loaded on the gate ends of the first MOS transistor 111 and the third MOS transistor 113, so that the first MOS transistor 111 and the third MOS transistor 113 are turned on; the second voltage-controlled signal is loaded at the gate terminal of the second MOS transistor 112, so that the second MOS transistor 112 is turned off, and the measurement of the current and the voltage of the corresponding port of the device to be measured is realized.

Correspondingly, when the low leakage switch 11 is turned off, the first voltage-controlled signal simultaneously controls the first MOS transistor 111 and the third MOS transistor 113 to be turned off, and the second voltage-controlled signal controls the second MOS transistor 112 to be turned on, so as to maintain the low leakage characteristic of the low leakage switch 11 in the off state.

In this embodiment, the well terminal of the third MOS transistor 113 and the drain terminal of the second MOS transistor 112 are connected to the signal protection path 13. Of course, in an alternative embodiment, the well terminal of the third MOS transistor 113 may also be directly connected to the signal protection path 13.

Referring to fig. 5 and 9 in combination, in the present embodiment, in the extending direction of the drain terminal voltage signal line 12 and the drain terminal sensing signal line 14, the signal protection path 13 is disposed to surround the peripheral sides of the drain terminal voltage signal line 12 and the drain terminal sensing signal line 14, so as to reduce the influence of the leakage on the drain terminal voltage signal line 12 and the drain terminal sensing signal line 14 on the measurement result.

In a specific structure, the drain voltage signal line 12 and the drain sensing signal line 14 may have substantially the same direction, and surround the drain voltage signal line 12 and the drain sensing signal line 14 simultaneously through a signal protection path 13. Alternatively, the drain side voltage signal line 12 and the drain side sense signal line 14 may be provided with corresponding signal protection paths 13.

In this embodiment, the signal protection path 13 may copy the voltage on the drain sensing signal line 14 or the drain voltage signal line 12 through a voltage follower buffer, or the drain sensing signal line 14, the drain voltage signal line 12, and the signal protection path 13 may be connected to pads of equal voltage, respectively.

Among these, due to the inherent on-resistance of the low leakage switch 11, there is a non-negligible voltage transfer loss on the drain terminal voltage signal line 12; since the drain terminal sensing signal line 14 is connected to the high-resistance voltage measuring loop, the current on the drain terminal sensing signal line is almost zero, and the voltage transmission loss can be ignored. In this way, the signal protection path 13 can more accurately copy the voltage applied to the corresponding port of the device under test from the drain terminal sensing signal line 14, which can avoid the leakage from the well terminal to the source terminal of the first MOS transistor 111 in the low leakage switch 11 during the large current measurement.

Referring to fig. 10 in combination, in the present embodiment, the plurality of low leakage switches 11, the drain terminal voltage signal line 12, the drain terminal sensing signal line 14, and the signal protection path 13 together constitute an addressable test circuit. Similarly, the addressable test circuits in the addressable test array 100 may also be set to "drain addressable," "gate addressable," "source addressable," and "well addressable" according to the test requirements of the device to be tested, and the specific setting modes thereof may all refer to the previous embodiment, and are not described herein again.

Referring to FIG. 11, yet another embodiment of an addressable test array 300 of the present application is described. In this embodiment, the addressable test array 300 also includes a plurality of addressable controlled on/off low leakage switches 11.

Unlike the previous embodiment, the drain of the second MOS transistor 112 in this embodiment can be controllably connected to the drain voltage signal line 12 or the drain sensing signal line 14. That is, the drain voltage of the second MOS transistor 112 can be controlled to be equal to the voltage on the drain voltage signal line 12 or the drain sensing signal line 14.

In one embodiment, the drain terminals of the second MOS transistors 112 of the low leakage switches 11 may be all connected to a drain leakage protection signal line 15, and control the drain leakage protection signal line 15 to be connected to the drain voltage signal line 12 or the drain sensing signal line 14. Illustratively, the drain leakage protection signal line 15 may selectively copy the voltage from the drain voltage signal line 12 or the drain sensing signal line 14 through a voltage follower buffer to connect the drain of the second MOS transistor 112 to the drain voltage signal line 12 or the drain sensing signal line 14.

In a specific application scenario, the drain of the second MOS transistor 112 may be selectively connected to the drain voltage signal line 12 or the drain sensing signal line 14, and the signal protection path 13 may also be selectively replicated on the drain voltage signal line 12 or the drain sensing signal line 14, according to the type of the device under test.

Exemplarily, the type of the device under test here may be a differentiated NMOS transistor or PMOS transistor.

It should be noted that, because of the precise measurement field, in the embodiments/examples of the present application, "equal" defined in a functionally limited manner does not take into account the influence of unavoidable factors such as the characteristics of each device in the circuit and the circuit transfer loss. Therefore, in these embodiments, the definition of "equal" should be considered as an ideal state definition after ignoring these factors, and should not be considered as an absolute definition of an equal state between comparison objects. Exemplarily, taking "the signal protection path 13 is configured to be equal to the voltage on the drain voltage signal line 12" as an example, the voltage transmission loss on the drain voltage signal line 12 is not considered, and the actual purpose of this setting is to make the voltage on the signal protection path 13 infinitely approach the actual voltage at the measurement end of the device under test; therefore, in an embodiment where a high resistance voltage measurement loop is provided, the signal protection path 13 may be better provided as: the voltage on the voltage sense signal line with little voltage transfer loss is replicated.

Referring to fig. 12, the technical solution of the above-mentioned embodiments of the present application will be described by taking an addressable test array of 32 × 1 rows as an example.

In this embodiment, the devices under test in the same row are controlled by the shift register driving low leakage switches. The RN initializes all triggers to zero to close all switches; the SI is a scanning input signal and comprises specific parameter information for controlling the low-leakage switch; CK is the clock of the line and column shift register, at the rising edge of every CK signal, the register moves forward one bit, change the low leakage switch controlled; SO is the scan out signal that determines the turn on of the low leakage switch corresponding to the particular DUT. The shift register can only select one DUT at any time, and the drain voltage signal line DF for testing current and the drain sensing signal line DS for testing voltage are always wired in the signal protection circuit GRD to prevent leakage.

When the device to be measured is in a conducting state and measures the current of the device to be measured, other devices to be measured are in a closing state, and at the moment, the measurement error mainly comes from the voltage drop loss caused by the conducting resistance of the low leakage switch in the conducting state. By connecting the voltage sensing signal line DS, the voltage sensing signal line DS is connected with the high-resistance voltmeter, the voltage borne by the device to be measured can be accurately measured, and the problem of voltage measurement errors caused by the voltage drop of the series resistor when the low-leakage switch corresponding to the device to be measured is closed is solved.

When the device under test is in a low current state and its current is measured, any minor leakage will also significantly affect the measurement result. The low current state of the device under test may be that the device under test itself is in an off state, or that the device under test is in an on state but the current applied thereto is small. Therefore, in order to ensure that no leakage exists at the in-out node (each end of the device) of the device to be tested, the low leakage switch 1 is turned on, the well end of each MOS transistor in the low leakage switch 1 is connected with the signal protection circuit GRD, and the leakage of the low leakage switch 1 is almost zero. At this time, the low leakage switches 2 to 32 are turned off, and the current is connected through the signal protection path GRD without disturbing the measurement on the drain voltage signal line DF and the drain sensing signal line DS of the test voltage.

The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims

1. An addressable test array for testing a plurality of devices under test, comprising a plurality of addressable controlled on/off low leakage switches, each of said low leakage switches comprising:

a second MOS tube, wherein the drain terminal of the second MOS tube is connected to a first signal protection path, and the first signal protection path is configured to be equal to the voltage on a drain terminal voltage signal line;

and when a first voltage control signal is loaded at the grid end of the first MOS transistor to close the first MOS transistor and a second voltage control signal is loaded at the grid end of the second MOS transistor to switch on the second MOS transistor, the low leakage switch is switched off.

2. The addressable test array of claim 1, wherein the first signal protection path replicates the voltage on the drain voltage signal line through a voltage follower buffer; or the like, or, alternatively,

the drain terminal voltage signal line and the first signal protection path are respectively connected to the pads of equal voltage.

3. The addressable test array of claim 1, wherein the well terminal of the first MOS transistor is connected to the drain terminal voltage signal line or the first signal protection path, and the well terminal of the second MOS transistor is connected to the drain terminal voltage signal line or the first signal protection path.

4. The addressable test array of claim 3, wherein the well terminals of the first and second MOS transistors are interconnected and connected to the drain voltage signal line or the first signal protection path.

5. The addressable test array of claim 1, wherein the first signal protection path is disposed around a circumference side of the drain voltage signal line in an extending direction of the drain voltage signal line.

6. The addressable test array of claim 1, wherein each low leakage switch further comprises a high resistance voltage measurement loop capable of being controlled to be switched on and off, one end of the high resistance voltage measurement loop is connected to a source end of the first MOS transistor, and the other end of the high resistance voltage measurement loop is connected to a drain end induction signal line;

7. The addressable test array of claim 6, wherein the high resistance voltage measurement circuit comprises a third MOS transistor, a source terminal of the third MOS transistor is connected to a source terminal of the first MOS transistor, a drain terminal of the third MOS transistor is connected to the drain terminal sensing signal line, a gate terminal of the third MOS transistor is interconnected with a gate terminal of the first MOS transistor, and a well terminal of the third MOS transistor is connected to the second signal protection path.

8. The addressable test array of claim 6, wherein the second signal protection path replicates the voltage on the drain sense signal line through a voltage follower buffer; or the like, or, alternatively,

and the drain end induction signal line and the second signal protection path are respectively connected to the bonding pads with equal voltage.

9. The addressable test array of claim 6, wherein the second signal protection path is disposed around a periphery side of the drain sense signal line in an extending direction of the drain sense signal line.

10. An addressable test array for testing a plurality of devices under test, comprising a plurality of addressable controlled on/off low leakage switches, each of said low leakage switches comprising:

11. An addressable test array for testing a plurality of devices under test, comprising a plurality of addressable controlled on/off low leakage switches, each of said low leakage switches comprising:

loading a first voltage control signal on the grid end of the first MOS transistor to enable the first MOS transistor to be conducted, and loading a second voltage control signal on the grid end of the second MOS transistor to enable the second MOS transistor to be closed, wherein the low leakage switch is conducted;

12. The addressable test array of claim 10 or 11, wherein the high resistance voltage measurement circuit comprises a third MOS transistor, a source terminal of the third MOS transistor is connected to a source terminal of the first MOS transistor, a drain terminal of the third MOS transistor is connected to the drain terminal sensing signal line, a gate terminal of the third MOS transistor is interconnected with a gate terminal of the first MOS transistor, and a well terminal of the third MOS transistor is connected to the signal protection path.

13. The addressable test array of claim 10 or 11, wherein the signal protection path replicates the voltage on the drain sense signal line or drain voltage signal line through a voltage following buffer; or the like, or, alternatively,

14. The addressable test array of claim 10 or 11, wherein the signal protection path is arranged around the periphery of the drain voltage signal line and the drain sensing signal line in the extending direction of the drain voltage signal line and the drain sensing signal line.

15. The addressable test array of claim 10 or 11, wherein the plurality of low leakage switches, the drain voltage signal line, the drain sense signal line, and the signal protection path comprise an addressable test circuit, the addressable test array comprising:

the addressable test circuit is used for being connected to drain terminals of a plurality of devices to be tested; and/or the presence of a gas in the gas,

the addressable test circuit is used for being connected to the grid ends of a plurality of devices to be tested; and/or the presence of a gas in the atmosphere,

16. The addressable test array of any of claims 1 to 11, further comprising a coaxial cable connected between the probe and the dashboard, the outer portion of the coaxial cable replicating the voltage of the lead-out wire at the device under test via a voltage follower buffer.