CN115220557A

CN115220557A - Power-on system, power-on method, readable storage medium and electronic device

Info

Publication number: CN115220557A
Application number: CN202110432588.8A
Authority: CN
Inventors: 雷长发; 彭国杰
Original assignee: Actions Technology Co Ltd
Current assignee: Actions Technology Co Ltd
Priority date: 2021-04-21
Filing date: 2021-04-21
Publication date: 2022-10-21

Abstract

The disclosure relates to a power supply starting system, a power supply starting method, a readable storage medium and an electronic device, which are used for reducing power consumption of the device during dormancy and improving endurance of a battery of the device. The power supply opening system includes: the device comprises an IO interface, a wake-up detection device and a power supply of a high-voltage power supply domain, wherein the wake-up detection device is connected with the IO interface, and the IO interface and the wake-up detection device are uniformly distributed in the high-voltage power supply domain to supply power to the IO interface and the wake-up detection device by the power supply of the high-voltage power supply domain; the IO interface is used for controlling the level change of the IO interface according to preset IO configuration information when a target event is received; the awakening detection device is connected with a power supply of the low-voltage power supply domain, detects the level change of the IO interface, and sends a starting instruction to the power supply of the low-voltage power supply domain when the level change meets a preset awakening condition so as to electrify the low-voltage power supply domain and further awaken the system chip.

Description

Power-on system, power-on method, readable storage medium and electronic device

Technical Field

The present disclosure relates to the field of electronic technologies, and in particular, to a power-on system, a power-on method, a readable storage medium, and an electronic device.

Background

Internet of Things (IoT) devices have small sizes and small battery capacities, and in order to extend battery endurance of the IoT devices and enhance customer experience, sleep modes are generally technically designed. When a System Chip SOC (System on Chip) of the equipment of the Internet of things does not work, the equipment of the Internet of things is controlled to enter a sleep mode, and when external events need to happen, the System Chip SOC is waken up to continue working.

For example, in the remote controller device, in order to save standby power consumption of the remote controller device as much as possible, the system chip SOC of the remote controller device is put into a low power consumption sleep mode when idle. When a wake-up event (for example, a key press, a serial interface transmission signal, IO overturn, etc.) is detected to occur, the system chip SOC is controlled to exit the low power consumption sleep mode, and the system chip SOC enters a working mode to complete the processing of the event.

However, in the related art, when the system chip SOC of the internet of things device enters the low power consumption sleep mode, since whether a wake-up event occurs needs to be detected, the related detection circuit needs to operate normally, that is, the internal power supply of the internet of things product needs to operate normally to supply power to the related detection circuit, so that the power consumption of the internet of things device is too large during standby or sleep, and the cruising ability of the battery is poor.

Disclosure of Invention

The disclosure aims to provide a power supply starting system, a power supply starting method, a readable storage medium and an electronic device, so as to effectively reduce the power consumption of the device during dormancy and improve the cruising ability of a battery of the device.

In order to achieve the above object, a first aspect of the present disclosure provides a power supply turning-on system, including: the device comprises an IO interface, a wake-up detection device and a power supply of a high-voltage power supply domain, wherein the wake-up detection device is connected with the IO interface, and the power supply of the high-voltage power supply domain supplies power to the IO interface and the wake-up detection device;

the IO interface is used for controlling the level change of the IO interface according to preset IO configuration information when a target event is received;

the wake-up detection device is connected with a power supply of a low-voltage power supply domain, detects the level change of the IO interface, and sends a starting instruction to the power supply of the low-voltage power supply domain when the level change meets a preset wake-up condition so as to electrify the low-voltage power supply domain to wake up the system chip, wherein the power supply of the low-voltage power supply domain is disconnected when the system chip enters a dormant state.

Optionally, the target event includes that a key is pressed; the IO configuration information comprises a type identifier, a resistance identifier and an output level of each IO interface, wherein the type identifier comprises an input interface identifier and an output interface identifier, and the resistance identifier comprises a pull-up resistance identifier and a pull-down resistance identifier;

when the key is pressed down, the level of the input interface corresponding to the key is changed to be consistent with the output level of the output interface.

Optionally, the wake-up condition includes a change in a level of the input interface from a first level to a second level, and/or a change from the second level to the first level, where the first level is different from the second level.

Optionally, the wake-up detection device includes an IO interface level detection module, a wake-up judgment module, and a state conversion module, which are connected in sequence;

the IO interface level detection module is connected with the IO interface and used for detecting the level change of the IO interface;

the awakening judgment module is used for acquiring the awakening condition, judging whether the level change meets the awakening condition or not and sending a judgment result to the state conversion module;

and the state conversion module is used for generating a starting instruction for indicating the power supply of the low-voltage power supply domain to be started when the judgment result represents that the level change meets the preset awakening condition, and sending the starting instruction to the power supply of the low-voltage power supply domain.

Optionally, the system further comprises: a latch for storing the IO configuration information and the wake-up condition;

the IO interface is connected with the latch and used for acquiring the IO configuration information from the latch;

and the awakening judgment module is connected with the latch and used for acquiring the awakening condition from the latch.

Optionally, the IO configuration information and the wake-up condition are both set by the system chip before entering the sleep state.

Optionally, the target event includes a transmission signal of a serial interface, and the IO configuration information includes a type identifier for indicating that the IO interface is an input interface and an initial level of the IO interface; the wake-up condition comprises the IO interface changing from the initial level to a level opposite to the initial level;

and when the IO interface detects the event of the serial interface transmission signal, changing the level of the IO interface from the initial level to a level opposite to the initial level.

A second aspect of the present disclosure provides a power supply turning-on method, which is applied to the power supply turning-on system provided by the first aspect of the present disclosure, and the method includes:

responding to the received target event, and controlling the level change of an IO interface according to preset IO configuration information;

judging whether the level change meets a preset awakening condition or not;

and when the awakening condition is met, sending a starting instruction to a power supply of a low-voltage power supply domain so as to electrify the low-voltage power supply domain and further awaken the system chip.

A third aspect of the disclosure provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the method provided by the second aspect of the disclosure.

A fourth aspect of the present disclosure provides an electronic device, comprising: the power supply starting system comprises a system chip, a power supply of a low-voltage power supply domain and the power supply starting system provided by the first aspect of the disclosure, wherein the power supply starting system is connected with the power supply of the low-voltage power supply domain, and the power supply of the low-voltage power supply domain is connected with the system chip;

the power supply starting system is used for starting the power supply of the low-voltage power supply domain when the system chip is switched from a dormant state to a working state, so that the low-voltage power supply domain is electrified to wake up the system chip.

Through above-mentioned technical scheme, establish IO interface and awaken up detection device equipartition in the high voltage power supply domain to supply power for IO interface and awaken up detection device by the power in high voltage power supply domain. Therefore, when the system chip SOC is in the dormant state, the power supply of the low-voltage power supply domain can be in the power-off state, the power consumption of normal work of the low-voltage power supply when the system chip is in the dormant state is avoided, the dormant power consumption of the electronic equipment is reduced, and the cruising ability of the battery of the electronic equipment is further improved. And when the system chip SOC is in a dormant state, the IO interface and the awakening detection device can work normally to detect whether an event for awakening the system chip SOC occurs or not, and control the low-voltage power domain to be electrified when the event for awakening the system chip SOC is detected, so as to awaken the system chip SOC. Therefore, the dormancy power consumption of the electronic equipment is effectively reduced, and meanwhile, the system chip can be ensured to be awakened normally, so that the electronic equipment works normally.

Additional features and advantages of the present disclosure will be set forth in the detailed description which follows.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure, but do not constitute a limitation of the disclosure. In the drawings:

fig. 1 is a block diagram illustrating a power turn-on system according to an exemplary embodiment.

Fig. 2 is a block diagram illustrating another power turn-on system in accordance with an exemplary embodiment.

FIG. 3 is a flow diagram illustrating a system chip entering a sleep state in accordance with an exemplary embodiment.

FIG. 4 is a flow diagram illustrating a wake-up system chip in accordance with an example embodiment.

FIG. 5 is a schematic diagram illustrating a key scan matrix in accordance with an exemplary embodiment.

Fig. 6 is a flow chart illustrating a power up method according to an example embodiment.

FIG. 7 is a block diagram illustrating an electronic device in accordance with an example embodiment.

Detailed Description

Under the normal condition, no matter the clock gate technology or the power gate technology is used for reducing the power consumption of the equipment of the internet of things, at least a high-voltage power supply and a low-voltage power supply work, a system chip SOC is divided into an identification awakening source circuit and other circuits, and in a sleep mode, the identification awakening source circuit works normally, and the other circuits do not work.

Because the identification awakening source circuit needs to utilize a low-voltage power supply of the internet of things equipment to supply power to the identification awakening source circuit, the low-voltage power supply needs to work normally in a sleep mode. And when the low-voltage power supply normally works, the power consumption of the equipment of the Internet of things comprises the following steps: the low-frequency clock power consumption, the key circuit scanning power consumption, the GPIO detection power consumption, the serial port awakening detection circuit, the power consumption of the control circuit for maintaining the power gate, the power consumption of the power gate cell, the power consumption of the low-voltage power supply and the like. Therefore, the power consumption of the equipment in a standby or sleep mode is increased, the power consumption of the equipment in the sleep mode of the Internet of things cannot be effectively reduced, and the cruising ability of the battery is poor.

In view of this, the present disclosure provides a power-on system, a power-on method, a readable storage medium and an electronic device, so as to effectively reduce power consumption of the device during sleep and improve endurance of a battery of the device.

The following detailed description of specific embodiments of the present disclosure is provided in connection with the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present disclosure, are given by way of illustration and explanation only, not limitation.

Fig. 1 is a block diagram illustrating a power turn-on system according to an exemplary embodiment. The power supply starting system is used for starting a power supply of a low-voltage power supply domain, wherein the power supply of the low-voltage power supply domain is an internal power supply of electronic equipment (such as internet of things equipment, a remote controller and the like), namely, a power supply for supplying power to a system chip SOC of the electronic equipment.

As shown in fig. 1, the power supply system 100 may include an IO interface 101, a wake-up detection device 102, and a power supply 103 of a high voltage power domain. The wake-up detection device 102 is connected to the IO interface 101, and the IO interface 101 and the wake-up detection device 102 are both disposed in a high-voltage power domain, so that the IO interface 101 and the wake-up detection device 102 are powered by a power supply 103 of the high-voltage power domain. Further, the power supply 103 of the high voltage power domain refers to an external power supply of the electronic device.

The system chip of the electronic device may be awakened by a key mode, a serial interface mode, a GPIO (General-purpose input/output) mode, and the like, and these awakening modes may be collectively referred to as IO awakening. Therefore, in the present disclosure, the IO interface 101 may be used as a key interface, a serial interface, a GPIO interface, or the like.

In this disclosure, the IO interface 101 is configured to control a level change of the IO interface 101 according to preset IO configuration information when a target event is received. The target event may be an event for waking up the system chip SOC, which may be a key being pressed, a serial interface transmitting signal, or the like. That is to say, when an event of waking up the system chip SOC occurs, the IO interface 101 may control the level change of the IO interface 101 according to the preset IO configuration information. For example, it may be changed from a low level to a high level, or from a high level to a low level.

In addition, the wake-up detection device 102 is connected to the power supply 200 of the low voltage power domain, detects a level change of the IO interface 101, and sends a start instruction to the power supply 200 of the low voltage power domain when the level change satisfies a preset wake-up condition, so that the low voltage power domain is powered on to wake up the system chip.

It should be noted that, because the wake-up detection device is disposed in the high-voltage power domain and the power supply in the high-voltage power domain is adopted for supplying power, when the system chip SOC enters the sleep state, the power supply 200 in the low-voltage power domain may be directly turned off, that is, when the system chip SOC is in the sleep state, the low-voltage power domain may be completely powered off. For example, the power supply of the low voltage power domain may be in a power-off state by controlling the circuit generating the low voltage VDD to be in an off state. Therefore, the power consumption of normal work of the low-voltage power supply when the system chip is in the dormant state can be effectively avoided.

By adopting the technical scheme, the IO interface and the awakening detection device are uniformly distributed in the high-voltage power supply domain, so that the power supply of the high-voltage power supply domain supplies power to the IO interface and the awakening detection device. Therefore, when the system chip SOC is in a dormant state, the power supply of the low-voltage power supply domain can be in a power-off state, the low-voltage power supply domain is prevented from generating power consumption, the dormant power consumption of the electronic equipment is reduced, and the cruising ability of the battery of the electronic equipment is improved. And when the system chip SOC is in a dormant state, the IO interface and the awakening detection device can work normally to detect whether an event for awakening the system chip SOC occurs or not, and control the low-voltage power domain to be electrified when the event for awakening the system chip SOC is detected, so as to awaken the system chip SOC. Therefore, the dormancy power consumption of the electronic equipment is effectively reduced, and meanwhile, the system chip can be ensured to be awakened normally, so that the electronic equipment works normally.

Fig. 2 is a block diagram illustrating another power turn-on system in accordance with an exemplary embodiment. As shown in fig. 2, the wake-up detection apparatus 102 may include an IO interface level detection module 1021, a wake-up determination module 1022, and a state transition module 1023, which are connected in sequence.

The IO interface level detection module 1021 is connected with the IO interface 101 and is used for detecting level change of the IO interface 101; the wakeup judging module 1022 is configured to obtain a wakeup condition, judge whether the level change meets the wakeup condition, and send a judgment result to the state transition module 1023; the state transition module 1023 is configured to generate a start instruction for instructing the power supply of the low-voltage power supply domain to start when the determination result represents that the level change meets the preset wake-up condition, and send the start instruction to the power supply 200 of the low-voltage power supply domain. In addition, the state transition module 1023 may be further configured to generate an instruction for instructing the low-voltage power domain to maintain the power supply in the off state when the determination result indicates that the level change does not satisfy the preset wake-up condition, so as to control the power supply 200 in the low-voltage power domain to maintain the off state.

It should be noted that, in the present disclosure, the IO configuration information and the wake-up condition are both set by the system chip before entering the sleep state. That is, the IO configuration information and the wake-up condition are set in the low voltage power domain. In order that the IO interface 101 and the wake-up detection device 102 working in the high-voltage power domain can normally use the IO configuration information and the wake-up condition after the power supply 200 of the low-voltage power domain is powered off, the high-voltage power domain needs to acquire the IO configuration information and the wake-up condition before the power supply 200 of the low-voltage power domain is powered off.

The power supply turning-on system 100 may further include a latch, where the latch is capable of temporarily storing the IO configuration information and the wake-up condition set by the system chip in the normal operating mode to maintain a certain state, so as to turn on the power supply of the low-voltage power supply domain according to the IO configuration information and the wake-up condition in the sleep state, so as to wake up the system chip.

Illustratively, the latch is connected to the system chip, and may acquire the IO configuration information and the wake-up condition from the system chip and store the IO configuration information and the wake-up condition. The IO interface is connected with the latch and can acquire IO configuration information from the latch, and the wake-up judging module is connected with the latch and can acquire the wake-up condition from the latch.

In the present disclosure, the number of latches may be one or two, and when the power supply turning-on system 10 includes one set of latches, the IO configuration information and the wake-up condition are both stored in the set of latches. When the power turn-on system 10 includes two sets of latches (hereinafter referred to as a first latch and a second latch), IO configuration information may be stored in the first latch and a wake-up condition may be stored in the second latch. As shown in fig. 2, the IO interface 101 is connected to the first latch 104, and can obtain IO configuration information from the first latch 104, and the wakeup judging module 1022 is connected to the second latch 105, and can obtain a wakeup condition from the second latch 105. It is to be noted that the first latch 104 and the second latch 105 are not shown in fig. 2 to be connected to the system chip.

FIG. 3 is a flow diagram illustrating a system chip entering a sleep state in accordance with an exemplary embodiment. As shown in fig. 3, the process of the system chip entering the sleep state includes: firstly, the system chip sets IO configuration information and awakening conditions before entering a sleep mode, then, a latch in a high-voltage power supply domain acquires and stores the IO configuration information and the awakening conditions from the system chip, and then, a state conversion module controls power-off of a power supply of a low-voltage power supply domain so that the system chip enters the sleep mode.

It should be noted that the IO interface level detection module and the wakeup determination module may be in a working state all the time, or may enter the working state only after the system chip enters the sleep state, which is not specifically limited by the present disclosure.

FIG. 4 is a flow diagram illustrating a wake-up system chip according to an example embodiment. As shown in fig. 4, the process of waking up the system chip includes: firstly, an IO interface level detection module detects the level change of an IO interface, then a wake-up judgment module judges whether the level change meets a wake-up condition so as to determine whether an event occurring in the IO interface is a wake-up event, and then a state conversion module controls the power supply of a low-voltage power supply domain to be turned on when the level change meets the wake-up condition according to the judgment result so as to wake up a system chip.

Therefore, according to the mode, the dormancy power consumption of the electronic equipment is effectively reduced, meanwhile, the system chip can be controlled to enter the dormancy state, and the system chip can be controlled to be awakened normally, so that the electronic equipment works normally.

In one embodiment, the electronic device is a key-wake up device, i.e. the system chip is wake up by using a key, and therefore, the target event includes that the key is pressed.

In the related art, when a system chip is awakened by a key, an output interface periodically outputs a low level or a high level according to a certain rule, an input interface periodically connects with a pull-up resistor or a pull-down resistor according to a certain rule, and periodically detects the level of the input interface according to a certain rule, and when the level of the input interface is detected to be changed from the high level to the low level or from the low level to the high level, it is determined that an event that the key is pressed down occurs. It should be noted that, in order to enable the output interface to periodically output a low level or a high level according to a certain rule, the input interface to periodically connect with the pull-up resistor or the pull-down resistor according to a certain rule, and to periodically detect the level of the input interface according to a certain rule, the input interface needs to be controlled by a clock, and the clock also consumes power during operation.

In order to further reduce the sleep power consumption, in the present disclosure, whether a key is pressed may be detected using a simplified key scanning manner. For example, the periodic output of the output interface can be changed into a fixed output, the periodic connection of the input interface with the pull-up resistor or the pull-down resistor can be changed into a fixed connection with the pull-up resistor or the pull-down resistor, and the periodic detection of the level of the input interface can be changed into real-time detection. Therefore, the control is not needed by the clock, namely, the clock does not need to work, the power consumption of the clock during working is avoided, and the sleep power consumption is further reduced.

In this embodiment, the IO configuration information includes a type identifier of each IO interface, a resistance identifier of a resistor connected to each IO interface, and an output level of the output interface. The type identification comprises an input interface identification and an output interface identification, and the resistance identification comprises a pull-up resistance identification and a pull-down resistance identification. It is worth to be noted that, when the IO interface is connected to the pull-up resistor, the level of the IO interface is high, and when the IO interface is connected to the pull-down resistor, the level of the IO interface is low. The resistor described herein may be a conventionally understood resistor (or resistance wire) or a MOS transistor used as a resistor function, and the disclosure is not limited thereto.

For example, the IO configuration information includes an output enable signal OE, an input enable signal IE, a pull-up enable signal PU, a pull-down enable signal PD, and an output level O of the output interface. If the IO configuration information of a certain IO interface is OE =1, IE =0, PU =0, PD =0, and O =0, it indicates that the IO interface is an output interface, and the output interface fixes an output low level. If the IO configuration information of a certain interface is OE =0, IE =1, PU =1, and PD =0, it indicates that the IO interface is an input interface, and the input interface is connected to a pull-up resistor. Therefore, the IO interface can be divided into an input interface and an output interface according to the IO configuration.

It should be noted that, the configuration information of the three output interfaces included in the group a IO interface may be the same or different, and similarly, the configuration information of the three input interfaces included in the group B IO interface may be the same or different, which is not limited in this disclosure.

Illustratively, FIG. 5 is a schematic diagram illustrating a key scan matrix according to an exemplary embodiment. As shown in fig. 5, it is assumed that the group a (including A1, A2, and A3) IO interface is an output interface, and the group B (including B1, B2, and B3) IO interface is an input interface. When a key is pressed, the level of the input interface corresponding to the key changes to be consistent with the output level of the output interface. The input interface corresponding to the key is the input interface where the key is located. In fig. 5, when a key at the intersection of the A1 interface and the B1 interface is pressed, the level of the B1 interface, which is the input interface, changes to be equal to the output level of the output interface, that is, to be equal to the output level of the A1 interface.

Accordingly, the wake-up condition may include a change in a level of the input interface from a first level to a second level, and/or a change from the second level to the first level, wherein the first level is different from the second level. Illustratively, the first level is a low level, and the second level is a high level. Assuming that the level of the B1 interface is changed from low level to high level and/or the level of the B1 interface is changed from high level to low level, at least one key in the three keys of the B1 interface is considered to be pressed.

For example, the A1 interface is set to output a low level fixedly, the B1 interface is connected to a pull-up resistor, and when the B1 interface is detected to output a low level (i.e., the level of the B1 interface changes from a high level to a low level), it is considered that the key is detected to be pressed. Assuming that the A1 interface is set to output a high level fixedly, and the B1 interface is connected to the pull-down resistor, when it is detected that the B1 interface outputs a high level (i.e., the level of the B1 interface changes from a low level to a high level), it can be considered that the key is detected to be pressed.

In another embodiment, the electronic device is a device that wakes up by transmitting a signal through the serial interface, that is, wakes up the system chip by transmitting a signal through the serial interface, and thus the target event includes transmitting a signal through the serial interface. The IO configuration information may include a type identifier indicating that the IO interface is an input interface and an initial level of the IO interface, and accordingly, the wake-up condition includes that the level of the IO interface changes from the initial level to a level opposite to the initial level. When detecting the event of the serial interface transmission signal, the IO interface changes the level of the IO interface from the initial level to a level opposite to the initial level. It should be noted that, in this embodiment, the serial interface is an IO interface.

Therefore, when the awakening detection device detects that the level of the IO interface is changed from the initial level to the level opposite to the initial level, the awakening detection device sends a starting instruction to the power supply of the low-voltage power supply domain, so that the low-voltage power supply domain is electrified to awaken the system chip, and the system chip is awakened by utilizing the serial interface transmission signal.

In one embodiment, the IO interface is connected to the pull-up resistor, and sets an initial level of the IO interface to a high level, where a level opposite to the initial level is a low level, that is, the level of the IO interface changes from the high level to the low level in a wake-up condition, and accordingly, when the IO interface detects an event of a serial interface transmission signal, the level of the IO interface changes from the high level to the low level. In another embodiment, the IO interface is connected to the pull-down resistor, and the initial level of the IO interface is set to a low level, and at this time, a level opposite to the initial level is a high level, that is, the level of the IO interface changes from the low level to the high level in the wake-up condition, and accordingly, the IO interface changes the level of the IO interface from the low level to the high level when detecting an event of a serial interface transmission signal.

It should be noted that, in the embodiment where the IO interface is connected to the pull-down resistor, that is, the initial level is a low level, since the Universal Asynchronous Receiver/Transmitter (UART) protocol defaults that the level of the serial interface is a high level when no signal is transmitted, and the level is pulled down to a low level when a signal is transmitted, if the wake-up condition is set such that the level of the IO interface changes from a low level to a high level, it is necessary to pull down the level of the serial interface to a low level first, and then pull up the level to a high level, which may result in low detection efficiency.

Based on the same inventive concept, the disclosure also provides a power supply starting method. Fig. 6 is a flowchart illustrating a power-on method applied to the power-on system provided in the present disclosure according to an exemplary embodiment. As shown in fig. 6, the method may include the following steps.

In step 601, in response to a received target event, controlling level change of an IO interface according to preset IO configuration information;

in step 602, determining whether the level change satisfies a preset wake-up condition;

in step 603, when the wake-up condition is satisfied, a power-on command is sent to a power supply of a low-voltage power domain, so that the low-voltage power domain is powered on to wake up the system chip.

With regard to the method in the above-described embodiment, the specific manner in which each step performs the operation has been described in detail in the embodiment related to the system, and will not be elaborated upon here.

The present disclosure also provides an electronic device, including: the power supply starting system is connected with the power supply of the low-voltage power supply domain, and the power supply of the low-voltage power supply domain is connected with the system chip; the power supply starting system is used for starting the power supply of the low-voltage power supply domain when the system chip is switched from a dormant state to a working state, so that the low-voltage power supply domain is electrified to further wake up the system chip.

The electronic equipment can be a remote controller, in order to save standby power consumption of the remote controller as much as possible, the system chip enters a low-power-consumption sleep mode when the system chip is idle, and the IO interface and the awakening detection device are arranged in a high-voltage power domain to supply power to the high-voltage power domain. Thus, when the system chip is in a dormant state, the power supply of the low-voltage domain can be directly powered off. When the events such as key pressing, serial port transmission request, IO overturn and the like are detected, the power supply of the low-voltage domain is controlled to be powered on to supply power to the system chip so as to wake up the system chip and enable the system chip to enter a working mode to complete the processing of the events.

Illustratively, FIG. 7 is a block diagram of an electronic device shown in accordance with an exemplary embodiment. As shown in fig. 7, the electronic device 700 may include: a processor 701 and a memory 702. The electronic device 700 may also include one or more of a multimedia component 703, an input/output (I/O) interface 704, and a communication component 705.

The processor 701 is configured to control the overall operation of the electronic device 700, so as to complete all or part of the steps of the power-on method. The memory 702 is used to store various types of data to support operation at the electronic device 700, such as instructions for any application or method operating on the electronic device 700 and application-related data, such as contact data, transmitted and received messages, pictures, audio, video, and so forth. The Memory 702 may be implemented by any type of volatile or non-volatile Memory device or combination thereof, such as Static Random Access Memory (SRAM), electrically Erasable Programmable Read-Only Memory (EEPROM), erasable Programmable Read-Only Memory (EPROM), programmable Read-Only Memory (PROM), read-Only Memory (ROM), magnetic Memory, flash Memory, magnetic disk, or optical disk. The multimedia components 703 may include screen and audio components. Wherein the screen may be, for example, a touch screen and the audio component is used for outputting and/or inputting audio signals. For example, the audio component may include a microphone for receiving external audio signals. The received audio signal may further be stored in the memory 702 or transmitted through the communication component 705. The audio assembly further comprises at least one speaker for outputting audio signals. The I/O interface 704 provides an interface between the processor 701 and other interface modules, such as a keyboard, mouse, buttons, etc. These buttons may be virtual buttons or physical buttons. The communication component 705 is used for wired or wireless communication between the electronic device 700 and other devices. Wireless Communication, such as Wi-Fi, bluetooth, near Field Communication (NFC), 2G, 3G, 4G, NB-IOT, eMTC, or other 5G, or combinations thereof, which is not limited herein. The corresponding communication component 705 may thus include: wi-Fi module, bluetooth module, NFC module, etc.

In an exemplary embodiment, the electronic Device 700 may be implemented by one or more Application Specific Integrated Circuits (ASICs), digital Signal Processors (DSPs), digital Signal Processing Devices (DSPDs), programmable Logic Devices (PLDs), field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components for performing the above-described power-on method.

In another exemplary embodiment, a computer readable storage medium comprising program instructions which, when executed by a processor, implement the steps of the power-up method described above is also provided. For example, the computer readable storage medium may be the above-mentioned memory 702 comprising program instructions that are executable by the processor 701 of the electronic device 700 to perform the above-mentioned power-on method.

In another exemplary embodiment, a computer program product is also provided, which comprises a computer program executable by a programmable apparatus, the computer program having code portions for performing the above-mentioned power-on method when executed by the programmable apparatus.

The preferred embodiments of the present disclosure are described in detail above with reference to the accompanying drawings, however, the present disclosure is not limited to the specific details in the above embodiments, and various simple modifications may be made to the technical solution of the present disclosure within the technical idea of the present disclosure, and these simple modifications all belong to the protection scope of the present disclosure.

It should be noted that the various features described in the foregoing embodiments may be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the disclosure does not separately describe various possible combinations.

In addition, any combination of various embodiments of the present disclosure may be made, and the same should be considered as the disclosure of the present disclosure, as long as it does not depart from the spirit of the present disclosure.

Claims

1. A power turn-on system, comprising: the device comprises an IO interface, a wake-up detection device and a power supply of a high-voltage power supply domain, wherein the wake-up detection device is connected with the IO interface, and the power supply of the high-voltage power supply domain supplies power to the IO interface and the wake-up detection device;

2. The power turn-on system of claim 1, wherein the target event comprises a key being pressed; the IO configuration information comprises a type identifier, a resistance identifier and an output level of each IO interface, wherein the type identifier comprises an input interface identifier and an output interface identifier, and the resistance identifier comprises a pull-up resistance identifier and a pull-down resistance identifier;

3. The power supply turning on system of claim 2, wherein the wake-up condition comprises a change in a level of the input interface from a first level to a second level and/or from the second level to the first level, wherein the first level is different from the second level.

4. The power supply opening system according to any one of claims 1-3, wherein the wake-up detection device comprises an IO interface level detection module, a wake-up judgment module and a state conversion module which are connected in sequence;

5. The power turn-on system of claim 4, further comprising: a latch for storing the IO configuration information and the wake-up condition;

6. A power supply opening system according to any one of claims 1-3, characterized in that the IO configuration information and the wake-up condition are set by the system chip before entering the sleep state.

7. The power supply opening system according to any one of claims 1 to 3, wherein the target event includes a transmission signal of a serial interface, and the IO configuration information includes a type identifier indicating that the IO interface is an input interface and an initial level of the IO interface; the wake-up condition comprises that the level of the IO interface is changed from the initial level to a level opposite to the initial level;

8. A power supply turning-on method applied to the power supply turning-on system according to any one of claims 1 to 7, the method comprising:

judging whether the level change meets a preset awakening condition or not;

9. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 7.

10. An electronic device, comprising: a system chip, a power supply of a low-voltage power domain, and the power supply opening system according to any one of claims 1 to 7, wherein the power supply opening system is connected with the power supply of the low-voltage power domain, and the power supply of the low-voltage power domain is connected with the system chip;

the power supply starting system is used for starting the power supply of the low-voltage power supply domain when the system chip is switched from a dormant state to a working state, so that the low-voltage power supply domain is electrified to further wake up the system chip.