CN115174971B - Audio return method, chip system and display device - Google Patents

Audio return method, chip system and display device Download PDF

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Publication number
CN115174971B
CN115174971B CN202210632775.5A CN202210632775A CN115174971B CN 115174971 B CN115174971 B CN 115174971B CN 202210632775 A CN202210632775 A CN 202210632775A CN 115174971 B CN115174971 B CN 115174971B
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China
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data
bit
audio data
audio
error correction
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CN115174971A (en
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沈有琪
马跃
朱文清
杨青
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Qingdao Xinxin Microelectronics Technology Co Ltd
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Qingdao Xinxin Microelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41—Structure of client; Structure of client peripherals
    • H04N21/4104—Peripherals receiving signals from specially adapted client devices
    • G—PHYSICS
    • G10—MUSICAL INSTRUMENTS; ACOUSTICS
    • G10L—SPEECH ANALYSIS TECHNIQUES OR SPEECH SYNTHESIS; SPEECH RECOGNITION; SPEECH OR VOICE PROCESSING TECHNIQUES; SPEECH OR AUDIO CODING OR DECODING
    • G10L19/00—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis
    • G10L19/04—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis using predictive techniques
    • G10L19/16—Vocoder architecture
    • G10L19/173—Transcoding, i.e. converting between two coded representations avoiding cascaded coding-decoding
    • G—PHYSICS
    • G10—MUSICAL INSTRUMENTS; ACOUSTICS
    • G10L—SPEECH ANALYSIS TECHNIQUES OR SPEECH SYNTHESIS; SPEECH RECOGNITION; SPEECH OR VOICE PROCESSING TECHNIQUES; SPEECH OR AUDIO CODING OR DECODING
    • G10L19/00—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis
    • G10L19/04—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis using predictive techniques
    • G10L19/16—Vocoder architecture
    • G10L19/18—Vocoders using multiple modes
    • G10L19/24—Variable rate codecs, e.g. for generating different qualities using a scalable representation such as hierarchical encoding or layered encoding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/439—Processing of audio elementary streams
    • H04N21/4398—Processing of audio elementary streams involving reformatting operations of audio signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/47—End-user applications
    • H04N21/485—End-user interface for client configuration
    • H04N21/4852—End-user interface for client configuration for modifying audio parameters, e.g. switching between mono and stereo
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Human Computer Interaction (AREA)
  • Computational Linguistics (AREA)
  • Health & Medical Sciences (AREA)
  • Audiology, Speech & Language Pathology (AREA)
  • Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Quality & Reliability (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

The invention discloses an audio return method, a chip system and display equipment, wherein the method comprises the following steps: the transmitting end performs error correction coding on the received compressed audio data to generate first audio data; the transmitting end carries out double-phase mark coding on the first audio data and the received uncompressed audio data to generate second audio data with anti-interference capability; the sending end modulates the second audio data according to the preset duty ratio to generate target audio data, so that the duty ratio deviation caused by alternating current compensation in the audio feedback process can be avoided; the sending end packs the target audio data to generate a target audio data packet; the transmitting end transmits the target audio data packet to the receiving end, and the anti-interference coding and the duty ratio modulation are carried out in the processing process of the received audio data in the mode, so that the data error of the transmitted target audio data packet when the receiving end decodes is avoided, and the transmission efficiency and the stability of the audio backhaul are improved.

Description

Audio return method, chip system and display device
Technical Field
The present invention relates to the field of wireless communications technologies, and in particular, to an audio backhaul method, a chip system, and a display device.
Background
At present, high definition and ultra high definition televisions seek to build immersive video experience and surround sound effect home theatres for consumers, reproducing theatre-like experiences. The enhanced audio return channel (Enhanced Audio Return Channel, earcon) in the high definition multimedia interface (High Definition Multimedia Interface, HDMI) ensures downward compatibility of the audio device, is simple to use, is easy to carry, and has good audio performance. The eARC audio transmission uses a differential audio channel (Differential Mode Audio Channel, DMAC) that transmits audio clocks and audio streams using differential signals, and a common mode data channel (Common Mode Data Channel, CMDC) that exchanges control information related to the eARC audio transmission using common mode signals. Devices that support the eARC function should implement both DMAC and CMDC functions and support them to operate simultaneously. The differential signal used in eARC can transmit the full bandwidth of HDMI audio, 2-8 channel 24 bit uncompressed 192kHz audio, and compressed audio. The special control signal can also transmit audio and video synchronous information, so that the audio and video can be seamlessly cooperated in the home theater and kept consistent, but in the use process, transmission errors caused by reasons such as audio data byte deletion or byte errors can occur in the enhanced audio backhaul channel, so that the anti-interference capability of the audio backhaul function is poor, and therefore, how to improve the anti-interference capability of the audio backhaul channel is a problem to be solved urgently in the audio backhaul field.
Disclosure of Invention
The invention provides an audio return method, a chip system and display equipment, which are used for solving the problem of poor anti-interference capability of an audio return channel in the prior art.
In a first aspect, an embodiment of the present invention provides an audio backhaul method, including:
the transmitting end performs error correction coding on the received compressed audio data to generate first audio data;
the sending end carries out double-phase mark coding on the first audio data and the received uncompressed audio data to generate second audio data;
the sending end modulates the second audio data according to a preset duty ratio to generate target audio data;
the sending end packs the target audio data to generate a target audio data packet;
the sending end transmits the target audio data packet to the receiving end.
In one possible implementation manner, the transmitting end performs error correction encoding on the received compressed audio data to generate first audio data, and includes:
the transmitting end equally divides the compressed audio data into two sub-frame data;
the transmitting end inserts an idle bit, an effective flag bit, a user data bit and a channel state bit into each subframe data to respectively obtain first extended subframe data and second extended subframe data;
The transmitting end encodes each extended subframe data based on a binary linear cyclic code to obtain error correction data bits with preset bit width, and replaces the idle bits with the error correction data bits to respectively obtain first error correction subframe data and second error correction subframe data;
the transmitting end carries out data interleaving on even number bits of the first error correction subframe data and even number bits of the second error correction subframe data to respectively obtain first interleaving subframe data and second interleaving subframe data;
and the transmitting end inserts a leading bit and a parity check bit into each interleaving subframe data to obtain the first audio data.
In one possible implementation manner, the sending end performs bi-phase mark coding on the first audio data and the received uncompressed audio data to generate second audio data, which includes:
the transmitting end divides each data bit of the first audio data and the uncompressed audio data into a first sub-data bit and a second sub-data bit in turn according to clock frequency;
if the signal of the data bit is a first level, the transmitting end processes the first sub data bit and the second sub data bit so that the levels of the first sub data bit and the second sub data bit are opposite;
If the signal of the data bit is the second level, the transmitting end processes the first sub data bit and the second sub data bit so that the first sub data bit and the second sub data bit have the same level;
the sending end processes the first sub data bit and the second sub data bit of each data bit to obtain the second audio data;
wherein the clock frequency is twice the transmission frequency of the first audio data and the uncompressed audio data.
In one possible embodiment, the method further comprises:
the sending end performs error correction coding on pre-stored control data to generate a first control data packet;
the sending end transmits the first control data packet to the receiving end so as to control the sending end to transmit the target audio data to the receiving end.
In one possible embodiment, the method further comprises:
after receiving a second control data packet sent by the receiving end, the sending end carries out double-phase mark decoding on the second control data packet to generate a pre-transmission control data packet;
and the sending end performs error correction decoding on the pre-transmission control data packet to generate the pre-transmission control data, so that the sending end transmits the first control data packet to the receiving end.
In a possible implementation manner, before the sending end generates the pre-transmission control data, the method further includes:
the transmitting end performs error correction decoding on the pre-transmission control data packet to generate control data to be checked;
if the control data to be checked does not have the preset error code, the sending end performs parity check on the control data to be checked;
and if the control data to be checked has no parity error, determining that the control data to be checked is the pre-transmission control data, so that the sending end transmits the first control data packet to the receiving end.
In a possible implementation manner, the performing bi-phase mark decoding on the second control data packet to generate a pre-transmission control data packet includes:
if the signal levels of two adjacent data bits of the data in the second control data packet are opposite, the sending end merges the two adjacent data bits into a decoded data bit of a first level;
if the signal levels of two adjacent data bits of the data in the second control data packet are the same, the sending end merges the two adjacent data bits into a decoded data bit of a second level;
And the sending end combines a plurality of decoded data bits to generate the pre-transmission control data packet.
In a possible implementation manner, the transmitting end performs error correction decoding on the pre-transmission control data packet to generate the pre-transmission control data, and includes:
the sending end carries out data interleaving on even bits of two adjacent data in the pre-transmission control data packet to obtain first interleaving data and second interleaving data;
the transmitting end deletes error correction data bits in the first interleaved data and the second interleaved data to obtain first error correction data and second error correction data;
and after deleting the effective flag bit, the user data bit and the channel state bit of the first error correction data and the second error correction data, the transmitting end merges the obtained data to generate the pre-transmission control data.
In a second aspect, an embodiment of the present invention provides an audio backhaul device, including:
the first generation module is used for performing error correction coding on the received compressed audio data to generate first audio data;
the second generation module is used for carrying out biphase mark coding on the first audio data and the received uncompressed audio data to generate second audio data;
The third generation module is used for modulating the second audio data according to a preset duty ratio to generate target audio data;
the packaging module is used for packaging the target audio data to generate a target audio data packet;
and the transmission module is used for transmitting the target audio data packet to a receiving end.
In a third aspect, an embodiment of the present invention provides a chip system, including: a processor and a memory coupled, wherein the memory includes program instructions that, when executed by the processor, cause the system-on-chip to perform the method of any of the first aspects.
In a fourth aspect, embodiments of the present invention provide a display device comprising a chip system as described in the second aspect.
In a fifth aspect, an embodiment of the present invention provides a computer storage medium storing a computer program comprising program instructions which, when executed by a computer, cause the computer to perform the method according to any one of the first aspects.
The invention has the following beneficial effects:
the invention discloses an audio return method, a chip system and display equipment, wherein the method comprises the following steps: the transmitting end performs error correction coding on the received compressed audio data to generate first audio data; the transmitting end carries out double-phase mark coding on the first audio data and the received uncompressed audio data to generate second audio data with anti-interference capability; the sending end modulates the second audio data according to the preset duty ratio to generate target audio data, so that the duty ratio deviation caused by alternating current compensation in the audio feedback process can be avoided; the sending end packs the target audio data to generate a target audio data packet; the sending end transmits the target audio data packet to the receiving end, and the anti-interference coding and the duty ratio modulation are carried out in the processing process of the received audio data in the mode, so that the data error of the sent target audio data packet when the receiving end decodes the target audio data packet is avoided.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it will be apparent that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1a is a schematic diagram of an eARC application scenario in the related art;
FIG. 1b is a schematic diagram of another eARC application scenario in the related art;
fig. 2 is a schematic structural diagram of a transmitting end in the related art;
fig. 3 is a flow chart of an audio feedback method according to an embodiment of the present invention;
fig. 4 is a schematic flow chart of a method for discovering a transmitting end according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram of a COMMA sequence according to an embodiment of the present invention;
fig. 6 is a flow chart of a method for discovering a receiving end according to an embodiment of the present invention;
fig. 7 is a schematic flow chart of a read-write function of a sending end according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a flow chart of error correction coding according to an embodiment of the present invention;
Fig. 9 is an equally divided schematic diagram of compressed audio data according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of extended subframe data according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram of error correction subframe data according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of interleaving subframe data according to an embodiment of the present invention;
fig. 13 is a schematic structural diagram of first audio data according to an embodiment of the present invention;
fig. 14 is a flow chart of a dual-phase mark encoding method according to an embodiment of the present invention;
FIG. 15a is a timing diagram of a dual-phase mark encoding according to an embodiment of the present invention;
FIG. 15b is a timing diagram of another dual-phase mark encoding according to an embodiment of the present invention;
fig. 16 is a schematic flow chart of a bi-phase mark decoding according to an embodiment of the present invention;
FIG. 17 is a schematic diagram of a flow chart of error correction decoding according to an embodiment of the present invention;
fig. 18 is a schematic structural diagram of a pre-transmission control packet according to an embodiment of the present invention;
fig. 19 is a flowchart of an embodiment of an audio feedback method according to the present invention;
FIG. 20 is a schematic diagram of a response timing diagram according to an embodiment of the present invention;
Fig. 21a is a schematic diagram of an application scenario of delay adjustment according to an embodiment of the present invention;
FIG. 21b is a schematic diagram of a delay adjustment method according to an embodiment of the present invention;
fig. 22 is a schematic structural diagram of an audio feedback device according to an embodiment of the present invention;
FIG. 23 is a schematic diagram of a chip system according to an embodiment of the present invention;
fig. 24 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Currently, enhanced audio backhaul channel (Enhanced Audio Return Channel, earcon) technology supports all home theater formats under the high definition multimedia interface (High Definition Multimedia Interface, HDMI) standard and can provide the full bandwidth required (maximum audio bandwidth of 37 Mbit/s). In addition, the eARC has a special data channel, allows connected devices to exchange supported audio format information, and discovers and pairs and controls, so that the devices do not need to discover and pair through an HDMI control protocol, and synchronous state information such as audio and video is transmitted through the control channel, so that the consistency of the audio and video signals is ensured. Because the eARC has the advantages of the foregoing audio bandwidth, compatibility, convenience, and the like, the eARC is widely used for audio transmission between a television or a display and a power amplifier device, as shown in fig. 1a, which is a schematic diagram of an eARC application scenario in the related art, where the scenario includes a transmitting end 101 and a receiving end 102, in practical application, the transmitting end 101 may be a television or a computer, the receiving end 102 may be a power amplifier device, and the transmitting end 101 and the receiving end 102 may be connected by an HDMI cable, represented by thick lines in the drawing, and in addition, as shown in fig. 1b, which is a schematic diagram of another eARC application scenario in the related art, the HDMI source 103 includes: the game system 1031 and the set-top box 1032 transmit an Audio/Video stream (a/V) to the HDMI receiver 104 in the transmitting terminal 101, and the HDMI extractor 105 extracts Video information to the display panel 106 for display, and the extracted Audio information transmits a high bit rate Audio signal from the transmitting terminal 101 to the receiving terminal 102 through the earcon module 107 using an HDMI cable supporting ethernet.
As shown in fig. 2, which is a schematic structural diagram of a transmitting end in the related art, the transmitting end 101 includes a differential audio module 201, a common data module 202 and an analog circuit processing module 203, the transmitting end 101 inputs an audio data stream, a clock and reset signal, a hot plug (Hot Plug Detected, HPD) signal and a system bus signal, and the differential audio module 201 processes the input audio data stream and then transmits the processed audio data stream to the receiving end 102 through the analog circuit processing module 203; the common-mode data module 202 transmits the control information related to the eARC audio transmission to the receiving end 102 through the analog circuit processing module 203, and meanwhile receives the control information related to the eARC audio transmission sent by the receiving end 102 through the analog circuit processing module 203; the analog circuit processing module 203 transmits audio data and completes the control data exchange through the EARCN and EARCP differential signal pairs.
It should be noted that, according to the specific function of the above-mentioned transmitting end module, the transmission of the audio data is unidirectional, and the transmission of the control data is bidirectional, and the present invention distinguishes the transmitting end 101 and the receiving end 102 according to the transmission direction of the audio data.
Based on the above problems, the embodiments of the present invention provide an audio backhaul method, a chip system, and a device, which are used to solve the problem in the prior art that the anti-interference capability of an audio backhaul channel is poor.
The audio playback method provided by the exemplary embodiments of the present application will be described below with reference to the accompanying drawings in conjunction with the application scenarios described above, and it should be noted that the application scenarios described above are only shown for the convenience of understanding the spirit and principles of the present application, and the embodiments of the present application are not limited in this respect.
Fig. 3 is a schematic flow chart of an audio feedback method according to an embodiment of the present application, where the method includes:
in step 301, the transmitting end performs error correction encoding on the received compressed audio data to generate first audio data.
In step 302, the transmitting end performs bi-phase mark encoding on the first audio data and the received uncompressed audio data, so as to generate second audio data.
In step 303, the transmitting end modulates the second audio data according to the preset duty ratio to generate the target audio data.
Step 304, the transmitting end packs the target audio data to generate a target audio data packet.
In step 305, the sender transmits the target audio data packet to the receiver.
The application discloses an audio frequency feedback method, which comprises the following steps: the transmitting end performs error correction coding on the received compressed audio data to generate first audio data; the transmitting end carries out double-phase mark coding on the first audio data and the received uncompressed audio data to generate second audio data with anti-interference capability; the sending end modulates the second audio data according to the preset duty ratio to generate target audio data, so that the duty ratio deviation caused by alternating current compensation in the audio feedback process can be avoided; the sending end packs the target audio data to generate a target audio data packet; the transmitting end transmits the target audio data packet to the receiving end, and the anti-interference coding and the duty ratio modulation are carried out in the processing process of the received audio data in the mode, so that the data error of the transmitted target audio data packet when the receiving end decodes is avoided, and the transmission efficiency and the stability of the audio backhaul are improved.
The following describes the audio feedback method in detail:
as shown in fig. 4, a flow chart of a method for discovering a transmitting end according to an embodiment of the present invention is shown, where the method includes:
in step 401, when a preset condition is reached, the transmitting end monitors a heartbeat packet time window COMMA sequence.
When the initial HPD signal is a low level signal, the transmitting end should keep the HPD signal at a low level for at least 100 ms; when a preset condition is reached, that is, when the HPD is changed from a low level signal to a high level signal, or when a heartbeat packet is lost, a transmitting end starts to monitor a COMMA sequence, as shown in fig. 5, which is a schematic structural diagram of the COMMA sequence provided by the embodiment of the present invention, where the COMMA sequence includes a coded sequence COMMA ON and an uncoded sequence COMMA OFF, where the sequence occupation time of COMMA ON may be set to 10 milliseconds, and the sequence occupation time of COMMA coma OFF may be set to 10 milliseconds.
Step 402, when the number of COMMA sequences monitored by the transmitting end is greater than or equal to a preset value, the transmitting end transmits a heartbeat packet to the receiving end within a preset period of monitoring a heartbeat packet time window and sets a backhaul status bit to be valid.
In a possible embodiment, the preset value may be set to 3, and after the number of times of COMMA sequences detected by the transmitting end is greater than or equal to 3, the transmitting end sends a heartbeat packet to the receiving end within 45-55 ms of the time window of monitoring the heartbeat packet, and sets the backhaul status bit to be earc_valid=1.
In step 403, after the sender correctly receives the correct response command (Answer Correct Key, ACK) from the receiver, the sender discovers the receiver and enters the transmission state.
It should be noted that, after receiving the valid status bit, the receiving end 102 sends a correct response command to the sending end 101; in addition, after the transmitting end enters the transmission state, the common data module 202 is effective to transmit control data and heartbeat packets, and the differential audio module 201 is effective to transmit audio data or ineffective to transmit audio data, and after the transmitting end 101 finds the receiving end 102, the transmitting end 101 may enter an idle state by pulling down the HPD signal at the transmitting end 101, so as to disconnect the connection between the transmitting end 101 and the receiving end 102.
Fig. 6 is a schematic flow chart of a method for discovering a receiving end according to an embodiment of the present invention, where the method includes:
step 601, when a preset condition is reached, the receiving end sends a COMMA sequence to the sending end.
When the initial HPD signal is a low level signal and the predetermined condition is reached, that is, when the HPD signal is converted from a low level signal to a high level signal, the receiving end 102 transmits a COMMA sequence to the transmitting end 101.
Step 602, the receiving end monitors whether the heartbeat packet and the backhaul status bit sent by the sending end are valid, if yes, step 603 is executed, and if not, step 604 is executed.
In step 603, the receiving end stops sending the COMMA sequence and responds to the sending end to transmit the correct command in response to the heartbeat packet.
It should be noted that, after the receiving end responds to the heartbeat packet to transmit the correct command to the transmitting end, the transmitting end and the receiving end can perform data transmission.
In step 604, the receiving end continues to send the COMMA sequence to the sending end.
It should be noted that, after the receiving end 102 has sent the COMMA sequence, after the time of detecting that the valid signal of the backhaul state bit exceeds the preset time, the receiving end 102 enters the idle state, and in addition, if the HPD signal is converted from the high level signal to the low level signal, the receiving end 102 enters the idle state.
The audio backhaul protocol in the embodiment of the present invention defines two transmission types, namely, reading and writing of the audio backhaul function, and is different from the reading and writing method of the two-wire serial bus (Inter-Integrated Circuit, I2C), in which the transmission packet correct response bit ACK in the I2C reading and writing process is replaced by a transmission packet correct response command < ACK >. The sender 101 may respond to each received packet with an initiate next packet transmission command < CONT >, an end of transmission command < STOP >, or a retransmit command < RETRY >. When the receiving end detects an uncorrectable ECC error in a data packet received when initiating the next packet transmission state, it should respond to a transmission end command < STOP > or a retransmission command < RETRY >. The receiving end responds to each received command or data packet with a < ACK > or transmission packet error response command (Not Answer Correct Key, NACK), and responds to the non-supported device name with a < NACK >. During the time window, a receiving end that is not ready to receive data or is transmitting data will respond with a < NACK >. The receiving end 102 will enter the idle state after the response < NACK >, and at the same time, when the transmitting end 101 detects that the response time has timed out, the transmitting end 101 will enter the idle state.
Specifically, as shown in fig. 7, a flow chart of a read-write function of a sending end provided in an embodiment of the present invention includes:
in step 701, the transmitting end transmits a read-write command.
In step 702, the sender receives the < ACK > responded by the receiver and sends the device name.
In step 703, the sender receives the < ACK > responded by the receiver, and the sender sends the offset address.
Step 704, the sender receives the < ACK > responded by the receiver, if the transmission needs to be continued, step 705 is executed, if the stop is needed, step 706 is executed, and if the retransmission is needed, step 707 is executed.
Step 705, the transmitting end transmits < CONT >, and step 704 is performed.
In step 706, the sender sends < STOP >, and then receives the < ACK > responded by the receiver.
In step 707, the transmitting end sends < RETRY >, and then receives the < ACK > responded by the receiving end.
In a possible embodiment, referring to fig. 7, the transmitting end 101 initiates a read transmission process, sets the device name to 0x74, and the offset address to 0xD0, and obtains the information of the status register of the receiving end 102 after the reading is completed; the transmitting end 101 initiates a write-once transmission process, sets the equipment name as 0x74, and the offset address as 0xD1, and transmits the information of the state register of the transmitting end 101 to the receiving end 102 in the write process; the transmitting end 101 in the transmission state should send a heartbeat packet once within 45-55 ms of each heartbeat packet time window, and if the transmission of the heartbeat packet is not completed during the heartbeat packet time window, the heartbeat packet is lost. If the transmission of the heartbeat packet is completed in the heartbeat packet time window, the normal operation of the signal return channel is indicated, and meanwhile, the state information of the eARC is exchanged in the transmission process.
As shown in fig. 8, a flow chart of error correction coding provided in an embodiment of the present invention includes:
in step 801, the transmitting end equally divides the compressed audio data into two sub-frame data.
Specifically, as shown in fig. 9, an example of an aliquoting schematic diagram of compressed audio data provided in an embodiment of the present invention is 16-bit IEC61937 compressed audio transmission protocol standard compressed audio data, where the compressed data is aliquoted into first subframe data A0 and second subframe data B0.
Step 802, the transmitting end inserts an idle bit, a valid flag bit, a user data bit and a channel status bit in each subframe data to obtain a first extended subframe data and a second extended subframe data respectively.
Specifically, as shown in fig. 10, a schematic diagram of an extended subframe Data structure provided in an embodiment of the present invention is shown, and referring to fig. 9, a transmitting end 101 inserts 5 bits of idle bits Zeros, 1 bit of Valid Flag bits (Valid Flag, V), 1 bit of User Data bits (User Data, U) and 1 bit of Channel Status bits (Channel Status, C) into a first subframe Data A0 and a second subframe Data B0, and after extension, obtains 24 bits of first extended subframe Data A1 and 24 bits of second extended subframe Data B1, respectively.
In step 803, the transmitting end encodes each extended subframe data based on a binary linear cyclic code (Bose Chaudhuri Hocquenghem Code, BCH) to obtain error correction data bits with a preset bit width, and replaces idle bits with the error correction data bits to obtain first error correction subframe data and second error correction subframe data respectively.
Specifically, as shown in fig. 11, referring to fig. 10, a transmitting end 101 encodes each extended subframe data based on a binary linear cyclic code to obtain an error correction data bit syncdrome with 8 bits wide, and replaces idle bits Zeros with the error correction data bit syncdrome to obtain first error correction subframe data A2 and second error correction subframe data B2 respectively.
It should be noted that the binary linear cyclic code is a linear block code in a finite field, has the capability of preventing random errors, and is generally used for anti-interference coding in the communication and storage fields, so that the invention can adopt BCH to code each 24-bit data to obtain a corresponding 8-bit error correction data bit syncrome code, and finally obtain 32-bit first error correction subframe data A2 and second error correction subframe data B2, and can combine with cyclic redundancy check codes (Cycle Redundancy Check, CRC) to check, and determine whether transmission is correct or not by the last parity check bit of the data generated by the cyclic redundancy check codes.
In step 804, the transmitting end performs data interleaving on the even bits of the first error correction subframe data and the even bits of the second error correction subframe data to obtain first interleaved subframe data and second interleaved subframe data respectively.
Specifically, as shown in fig. 12, a schematic structure diagram of an interleaved subframe data provided in the embodiment of the present invention, in combination with fig. 11, even bits of the first error correction subframe data A2 and the second error correction subframe data B2 may be subjected to data interleaving, so as to further increase reliability of communication, that is, 0 bit, 2 bit, 4 bit … … bit, 26 bit data of the first error correction subframe data A2 and the second error correction subframe data B2 are exchanged, so as to obtain first interleaved subframe data A3 and second interleaved subframe data B3 respectively;
similarly, the odd bits of the first error correction subframe data A2 and the second error correction subframe data B2 may be interleaved, so as to further increase the reliability of communication, i.e., the 1-bit, 3-bit, 5-bit … … -bit and 27-bit data of the first error correction subframe data A2 and the second error correction subframe data B2 are exchanged, so as to obtain the first interleaved subframe data A3 and the second interleaved subframe data B3 respectively.
In step 805, the transmitting end inserts a Preamble and a Parity (P) into each interleaved subframe data, to obtain first audio data.
Specifically, as shown in fig. 13, which is a schematic structural diagram of first audio data provided in the embodiment of the present invention, in combination with fig. 12, the transmitting end 101 inserts a 4-bit Preamble and a 1-bit parity bit P into each interleaved subframe data, so as to obtain two 32-bit IEC60958-1 first audio data that conform to the IEC60958-1 audio transmission protocol.
Fig. 14 is a schematic flow chart of a bi-phase mark encoding method according to an embodiment of the present invention, where the method includes:
in step 1401, the transmitting end divides each data bit of the first audio data and the uncompressed audio data into a first sub data bit and a second sub data bit according to the clock frequency.
It should be noted that, the bi-phase mark code (Biphase Mark Coding, BMC) is a phase modulation data processing method, which is a data processing method of mixing a clock and data together for transmission, as shown in fig. 15a, and is a timing diagram of the bi-phase mark code according to an embodiment of the present invention, which can split each data bit in the received data into a first sub-data bit C1 and a second sub-data bit D1 with a clock frequency twice as high as the data transmission frequency as a reference.
Step 1402, if the signal of the data bit is the first level, the transmitting end processes the first sub data bit and the second sub data bit, so that the levels of the first sub data bit and the second sub data bit are opposite; if the signal of the data bit is the second level, the transmitting end processes the first sub data bit and the second sub data bit so that the level of the first sub data bit is the same as that of the second sub data bit, and the second audio data is obtained after the processing;
specifically, in the bi-phase modulation encoding process, when the data bit is 1, the signals of the first sub data bit C1 and the second sub data bit D1 are hopped to become 10 or 01, and when the data bit is 0, the first sub data bit C1 and the second sub data bit D1 are not hopped to become 11 or 00, and in addition, the potential of the first sub data bit C1 is opposite to the signal of the sub data bit of the previous bit.
The common data module 202 uses BMC encoding defined in IEC60958-1, as shown in fig. 15b, which is a timing diagram of another dual-phase mark encoding provided in an embodiment of the present invention, the time of each bit in the encoding process of the common data module 202 is 0.95 us-1.05 us, taking the time of each bit as an example, when the data bit of the data transmission is 1, the common data module turns over at the moment of 0.475us, when the data bit of the data transmission is 0, the level remains unchanged within 0.95us, and in addition, the level also turns over between the two data bits.
As shown in fig. 16, a flow chart of dual-phase mark decoding provided by an embodiment of the present invention is shown, and the method includes:
in step 1601, if signal levels of two adjacent data bits of the data in the second control data packet are opposite, the common data module merges the two adjacent data bits into a decoded data bit of the first level.
In step 1602, if the signal levels of two adjacent data bits of the data in the second control packet are the same, the common data module merges the two adjacent data bits into a decoded data bit of the second level.
In step 1603, the common mode data module combines the plurality of decoded data bits to generate a pre-transmission control data packet.
As shown in fig. 17, a flow chart of error correction decoding provided by an embodiment of the present invention is shown, and the method includes:
in step 1701, the common data module performs data interleaving on even bits or odd bits of two adjacent data in the pre-transmission control data packet to obtain first interleaved data and second interleaved data.
In step 1702, the common data module deletes the error correction data bits in the first interleaved data and the second interleaved data, so as to obtain first error correction data and second error correction data.
And 1703, after deleting the valid flag bit, the user data bit and the channel state bit of the first error correction data and the second error correction data, the common data module combines the obtained data to generate pre-transmission control data.
It should be noted that, as shown in fig. 18, a schematic structural diagram of a pre-transmission control data packet according to an embodiment of the present invention is provided, where the pre-transmission control data packet includes: a Preamble of 6 bits, a Sync of 4 bits, a Command or Data bit of 1 bit (C/D), a reserved bit of 1 bit (R), a Payload of 8 bits, a Syndrome of 5 bits, and a parity bit P of 1 bit, wherein 1 in the Command or Data bit C/D represents the Command and 0 represents the Data; the reserved bit R is set to 0; the Payload represents a command or data; error correction data bits Syndrome for protecting data of C/D, R and Payload should be calculated using BCH (15, 10) encoding generated by polynomial G (x) =xζ5+xζ4+xζ2+1; parity bit P is a 1-bit parity value calculated from C/D, R, payload and the error correction data bit Syndrome. For example, when the number of the C/D, R, payload and error correction data bits Syndrome is even, P is 0; when the number of the C/D, R, payload and error correction data bits Syndrome is odd, P is 1.
As shown in fig. 19, a flowchart of an embodiment of an audio feedback method according to the present invention is shown, where the method includes:
Step 1901, the sender discovers the receiver, and performs steps 1902, 1907, and 1908.
It should be noted that, the process of the transmitting end to discover the receiving end is triggered by the HPD signal on the HDMI cable, the receiving end receives the signal and starts the discovery process, and after the discovery process is completed, normal communication can be performed between the transmitting end and the receiving end.
In step 1902, the differential audio module performs error correction encoding on the received compressed audio data to generate first audio data, and performs step 1903.
It should be noted that, since the compressed audio data may lose more data content than the uncompressed audio data due to bit-missing errors, the compressed audio data is more sensitive to transmission errors than the uncompressed audio data, for example, the compressed audio data may be error correction coded according to the 16-bit IEC61937 compressed audio transmission protocol standard to ensure robustness of the data link.
In step 1903, the differential audio module packs the first audio data and the uncompressed data according to a preset audio transmission protocol standard, and performs step 1904.
In one possible embodiment, taking the above-described error corrected IEC61937 compressed audio transmission protocol standard compressed audio data as an example, the received first audio data and uncompressed audio data codes may be packetized using the IEC60958-1 audio transmission protocol standard.
In step 1904, the differential audio module performs bi-phase mark encoding on the first audio data and the received uncompressed audio data, generates second audio data, and performs step 1905.
In step 1905, the transmitting end modulates the second audio data according to the preset duty ratio to generate target audio data, and executes step 1906.
In one possible embodiment, taking the above BMC-encoded second audio data packet as an example, the differential audio module may perform falling edge modulation (Falling Edge Modulation, FEM) on the received second audio data packet based on a preset duty cycle, modulate a level signal of one bit of data into high and low level signals of the preset duty cycle when the bit of data is 1, and modulate a level signal of one bit of data into high and low level signals of the preset duty cycle when the bit of data is 0.
It should be noted that, because there is ac compensation in the audio feedback process, there is an error in sampling, so the FEM method is required to correct the duty ratio of each bit of data, and further reduce the error.
In one possible embodiment, as shown in fig. 15a, the FEM mode may be modulated according to the bi-phase mark data, and is modulated into high and low level signals with a duty ratio of 3:2 when the data is 1, and is modulated into high and low level signals with a duty ratio of 2:3 when the data is 0.
In step 1906, the differential audio module packages the target audio data and sends the target audio data packet to the receiving end.
Specifically, the target audio data packet sent by the differential audio module generates differential signal pairs EARCN and EARCP through the analog circuit processing module, and sends an audio analog signal to the receiving end.
In step 1907, the common mode data module performs error correction encoding on the pre-stored control data, generates a first control data packet, and transmits the first control data packet to the receiving end, so as to control the transmitting end to transmit the target audio data to the receiving end.
In a possible implementation manner, the common data module receives the packaging request of the transmitting end 101, encodes the pre-stored control data according to the ECC encoding manner, packages the encoded data, generates a first control data packet, i.e. a heartbeat packet, and transmits the heartbeat packet to the receiving end 102.
In step 1908, after receiving the second control data packet sent by the receiving end, the common data module performs bi-phase mark decoding on the second control data packet to generate a pre-transmission control data packet, and step 1909 is performed.
In step 1909, the common data module performs error correction decoding on the pre-transmission control data packet to generate control data to be checked, and step 1910 is performed.
In step 1910, if the common data module determines that the control data to be checked does not have the preset error code, the parity check is performed on the control data to be checked, and step 1911 is executed.
It should be noted that, the preset error code refers to an error which is still not changeable and seriously affects the control process and is not negligible after the error correction decoding, and for a decoding error which does not affect the control process and is negligible, the present invention may configure a register so as to continue to perform parity check on data with decoding error to generate target control data, for example, configure the register to ignore_ecc_error=1, and the common data module continues to perform parity check on data meeting the requirement of register configuration.
In step 1911, if the common data module determines that the control data to be checked has no parity error, the control data to be checked is determined to be pre-transmission control data, so that the sending end transmits the first control data packet to the receiving end.
It should be noted that, for the negligible parity error that does not affect the control process, the present invention may configure the register to generate the target control data according to the data with the negligible parity error, for example, configure the register with ignore_parity_error=1, and the common data module generates the target control data according to the data meeting the requirement of the register configuration.
At step 1912, the common mode data module enters a target state based on the target control data, executing step 1907.
It should be noted that, the target control data is used for state skipping of the common data module, that is, if the common data module generates the target control data, normal state skipping can be performed to enter the target state, so as to ensure normal connection of the audio backhaul channel.
In one possible embodiment, the common mode data module enters a waiting period of the transmitting end 101 and a response period of the receiving end 102 after generating the target control data and maintaining one clock period.
Specifically, the sending end 101 waits for the response of the receiving end 102 in a waiting period, and the receiving end 102 responds to the sending end 101 in a response period, as shown in fig. 20, which is a response time sequence diagram provided in the embodiment of the present invention, the common module receives a timer signal, the waiting period is 7us, the response period is 27us, when the timer counts 7us, the sending end 101 ends the waiting period to enter a target state, when the timer counts 27us, the receiving end 102 ends the response period, and accordingly, when the receiving end 102 sends control data to the sending end 101, the waiting period of the receiving end 102 and the response period of the sending end 101 will not be repeated.
It should be noted that, for avoiding the problem of asynchronous video and audio, the audio delay needs to be matched with the video delay, as shown in fig. 21a, which is a schematic view of an application scenario of delay adjustment provided in an embodiment of the present invention, when the HDMI source 103 transmits audio and video to the HDMI sink 104 and separates the audio and video by the HDMI extractor 105, the audio is sent to the sink 102, the video signal is displayed by the display panel 106, and a 140 ms delay occurs on the screen due to the video processing process. Embodiments of the present invention write 140 milliseconds to the sender register 21011. Meanwhile, the receiving end 102 updates its audio delay and information in the receiving end register 21012, and then the television/display reads the receiving end register information to verify whether the television/display needs to further adjust the delay, thereby adjusting the audio or video delay accordingly, as shown in fig. 21b, which is a schematic diagram of a delay adjustment method according to an embodiment of the present invention, and the method includes:
in step 2101, the receiving end updates the audio delay information and the receiving end register information.
In step 2102, the sender reads the receiver register information to determine the delay to be adjusted and the duration to be adjusted.
In step 2103, the transmitting end adjusts the transmission speed of the audio data according to the time length required to be adjusted.
Based on the same inventive concept, the present invention further provides an audio feedback device, as shown in fig. 22, which is a schematic structural diagram of the audio feedback device provided by the embodiment of the present invention, where the device includes a first generating module 2201, a second generating module 2202, a third generating module 2203, a packaging module 2204, and a transmitting module 2205:
a first generating module 2201, configured to perform error correction encoding on the received compressed audio data to generate first audio data;
a second generating module 2202, configured to perform bi-phase mark encoding on the first audio data and the received uncompressed audio data, and generate second audio data;
a third generating module 2203, configured to modulate the second audio data according to a preset duty cycle, to generate target audio data;
the packaging module 2204 is configured to package the target audio data to generate a target audio data packet;
the transmission module 2205 is configured to transmit the target audio data packet to the receiving end.
In a possible embodiment, the apparatus further comprises a common mode data module 202, in particular for:
Equally dividing the compressed audio data into two sub-frame data;
inserting an idle bit, a valid flag bit, a user data bit and a channel state bit into each subframe data to respectively obtain first extended subframe data and second extended subframe data;
encoding each extended subframe data based on a binary linear cyclic code to obtain error correction data bits with preset bit width, and replacing the idle bits with the error correction data bits to respectively obtain first error correction subframe data and second error correction subframe data;
carrying out data interleaving on even number bits of the first error correction subframe data and even number bits of the second error correction subframe data to respectively obtain first interleaving subframe data and second interleaving subframe data;
and inserting a leading bit and a parity check bit into each interleaving subframe data to obtain the first audio data.
In one possible embodiment, the common mode data module 202 is specifically configured to:
dividing each data bit of the first audio data and the uncompressed audio data into a first sub data bit and a second sub data bit in turn according to clock frequency;
if the signal of the data bit is at a first level, processing the first sub data bit and the second sub data bit to enable the first sub data bit and the second sub data bit to be opposite in level;
If the signal of the data bit is at the second level, processing the first sub data bit and the second sub data bit so that the first sub data bit and the second sub data bit have the same level;
processing the first sub data bit and the second sub data bit of each data bit to obtain the second audio data;
wherein the clock frequency is twice the transmission frequency of the first audio data and the uncompressed audio data.
In one possible embodiment, the common mode data module 202 is further configured to:
performing error correction coding on pre-stored control data to generate a first control data packet;
and transmitting the first control data packet to the receiving end so as to control the transmitting end to transmit the target audio data to the receiving end.
In one possible embodiment, the common mode data module 202 is further configured to:
after receiving a second control data packet sent by the receiving end, performing biphase mark decoding on the second control data packet to generate a pre-transmission control data packet;
and performing error correction decoding on the pre-transmission control data packet to generate the pre-transmission control data, so that the sending end transmits the first control data packet to the receiving end.
Prior to generating the pre-transmission control data, in one possible embodiment, the common data module 202 is further configured to:
performing error correction decoding on the pre-transmission control data packet to generate control data to be checked;
if the control data to be checked does not have the preset error code, parity check is carried out on the control data to be checked;
and if the control data to be checked has no parity error, determining that the control data to be checked is the pre-transmission control data, so that the sending end transmits the first control data packet to the receiving end.
In one possible embodiment, the common mode data module 202 is specifically configured to:
if the signal levels of two adjacent data bits of the data in the second control data packet are opposite, merging the two adjacent data bits into a decoded data bit of a first level;
if the signal levels of two adjacent data bits of the data in the second control data packet are the same, the sending end merges the two adjacent data bits into a decoded data bit of a second level;
and combining a plurality of the decoded data bits to generate the pre-transmission control data packet.
In one possible embodiment, the common mode data module 202 is specifically configured to:
Carrying out data interleaving on even bits of two adjacent data in the pre-transmission control data packet to obtain first interleaving data and second interleaving data;
deleting error correction data bits in the first interleaved data and the second interleaved data to obtain first error correction data and second error correction data;
and deleting the effective zone bit, the user data bit and the channel state bit of the first error correction data and the second error correction data, and then merging the obtained data to generate the pre-transmission control data.
Based on the same inventive concept, the present invention also provides a chip system, as shown in fig. 23, which is a schematic structural diagram of a chip system provided in an embodiment of the present invention, where the chip system 230 includes: processor 2301 and memory 2302, processor 2301 and memory 2302 being coupled, wherein memory 2302 includes program instructions that, when executed by processor 2301, cause chip system 230 to perform the steps of: performing error correction coding on the received compressed audio data to generate first audio data;
performing biphase mark coding on the first audio data and the received uncompressed audio data to generate second audio data;
modulating the second audio data according to a preset duty ratio to generate target audio data;
Packaging the target audio data to generate a target audio data packet;
and transmitting the target audio data packet to a receiving end.
In one possible embodiment, the processor 2301 is specifically configured to:
equally dividing the compressed audio data into two sub-frame data;
inserting an idle bit, a valid flag bit, a user data bit and a channel state bit into each subframe data to respectively obtain first extended subframe data and second extended subframe data;
encoding each extended subframe data based on a binary linear cyclic code to obtain error correction data bits with preset bit width, and replacing the idle bits with the error correction data bits to respectively obtain first error correction subframe data and second error correction subframe data;
carrying out data interleaving on even number bits of the first error correction subframe data and even number bits of the second error correction subframe data to respectively obtain first interleaving subframe data and second interleaving subframe data;
and inserting a leading bit and a parity check bit into each interleaving subframe data to obtain the first audio data.
In one possible embodiment, the processor 2301 is specifically configured to:
dividing each data bit of the first audio data and the uncompressed audio data into a first sub data bit and a second sub data bit in turn according to clock frequency;
If the signal of the data bit is at a first level, processing the first sub data bit and the second sub data bit to enable the first sub data bit and the second sub data bit to be opposite in level;
if the signal of the data bit is at the second level, processing the first sub data bit and the second sub data bit so that the first sub data bit and the second sub data bit have the same level;
processing the first sub data bit and the second sub data bit of each data bit to obtain the second audio data;
wherein the clock frequency is twice the transmission frequency of the first audio data and the uncompressed audio data.
In one possible embodiment, the processor 2301 is further configured to:
performing error correction coding on pre-stored control data to generate a first control data packet;
and transmitting the first control data packet to the receiving end so as to control the transmitting end to transmit the target audio data to the receiving end.
In one possible embodiment, the processor 2301 is further configured to:
after receiving a second control data packet sent by the receiving end, performing biphase mark decoding on the second control data packet to generate a pre-transmission control data packet;
And performing error correction decoding on the pre-transmission control data packet to generate the pre-transmission control data, so that the sending end transmits the first control data packet to the receiving end.
Before generating the pre-transmission control data, in one possible embodiment, the processor 2301 is further configured to:
performing error correction decoding on the pre-transmission control data packet to generate control data to be checked;
if the control data to be checked does not have the preset error code, parity check is carried out on the control data to be checked;
and if the control data to be checked has no parity error, determining that the control data to be checked is the pre-transmission control data, so that the sending end transmits the first control data packet to the receiving end.
In one possible embodiment, the processor 2301 is specifically configured to:
if the signal levels of two adjacent data bits of the data in the second control data packet are opposite, merging the two adjacent data bits into a decoded data bit of a first level;
if the signal levels of two adjacent data bits of the data in the second control data packet are the same, the sending end merges the two adjacent data bits into a decoded data bit of a second level;
And combining a plurality of the decoded data bits to generate the pre-transmission control data packet.
In one possible embodiment, the processor 2301 is specifically configured to:
carrying out data interleaving on even bits of two adjacent data in the pre-transmission control data packet to obtain first interleaving data and second interleaving data;
deleting error correction data bits in the first interleaved data and the second interleaved data to obtain first error correction data and second error correction data;
and deleting the effective zone bit, the user data bit and the channel state bit of the first error correction data and the second error correction data, and then merging the obtained data to generate the pre-transmission control data.
Based on the same inventive concept, the present invention further provides a display device, which includes the above chip system, as shown in fig. 24, which is a schematic structural diagram of a display device according to an embodiment of the present invention, where the display device 240 specifically includes: a processor 2301, a memory 2302, a communication interface 2401 and a communication bus 2402.
The invention discloses an audio return method, a chip system and display equipment, wherein the method comprises the following steps: the transmitting end performs error correction coding on the received compressed audio data to generate first audio data; the transmitting end carries out double-phase mark coding on the first audio data and the received uncompressed audio data to generate second audio data with anti-interference capability; the sending end modulates the second audio data according to a preset duty ratio to generate target audio data, so that the duty ratio deviation caused by alternating current compensation in the audio feedback process can be avoided; the sending end packs the target audio data to generate a target audio data packet; the method comprises the steps that a sending end transmits a target audio data packet to a receiving end, anti-interference coding and modulation are carried out in the processing process of received audio data in the mode, so that data errors are avoided when the sent target audio data packet is decoded by the receiving end, and in addition, error correction coding is carried out on pre-stored control data by a control data sending end of audio feedback, so that a first control data packet is generated; the transmitting end transmits a first control data packet to the receiving end so as to control the transmitting end to transmit target audio data to the receiving end. After receiving the second control data packet sent by the receiving end, the sending end carries out double-phase mark decoding on the second control data packet to generate a pre-transmission control data packet; the transmitting end carries out error correction decoding on the pre-transmission control data packet to generate control data to be checked; if the control data to be checked does not have the preset error code, the sending end performs parity check on the control data to be checked; if the control data to be checked has no parity error, the sending end determines that the control data to be checked is pre-transmission control data, so that the sending end transmits the first control data packet to the receiving end. The control data is subjected to error correction decoding in the mode, decoding errors which do not affect control and errors of parity check are ignored, and the transmission efficiency and stability of the audio backhaul are further improved.
In an exemplary embodiment, the application also provides a computer-readable storage medium including instructions, such as memory 2302 including instructions, executable by processor 2301 of chip system 230 to perform the above-described audio feedback method. Alternatively, the computer readable storage medium may be a non-transitory computer readable storage medium, for example, a ROM, a Random Access Memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like.
In an exemplary embodiment, a computer program product is also provided, comprising a computer program which, when executed by the processor 2301, implements an audio feedback method as provided by the present application.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (10)

1. An audio feedback method, comprising:
the transmitting end performs error correction coding on the received compressed audio data to generate first audio data;
the sending end carries out double-phase mark coding on the first audio data and the received uncompressed audio data to generate second audio data;
the sending end modulates the second audio data according to a preset duty ratio to generate target audio data;
The sending end packs the target audio data to generate a target audio data packet;
the sending end transmits the target audio data packet to the receiving end.
2. The method of claim 1, wherein the transmitting end performs error correction encoding on the received compressed audio data to generate the first audio data, comprising:
the transmitting end equally divides the compressed audio data into two sub-frame data;
the transmitting end inserts an idle bit, an effective flag bit, a user data bit and a channel state bit into each subframe data to respectively obtain first extended subframe data and second extended subframe data;
the transmitting end encodes each extended subframe data based on a binary linear cyclic code to obtain error correction data bits with preset bit width, and replaces the idle bits with the error correction data bits to respectively obtain first error correction subframe data and second error correction subframe data;
the transmitting end carries out data interleaving on even number bits of the first error correction subframe data and even number bits of the second error correction subframe data to respectively obtain first interleaving subframe data and second interleaving subframe data;
and the transmitting end inserts a leading bit and a parity check bit into each interleaving subframe data to obtain the first audio data.
3. The method of claim 1, wherein the transmitting end performs bi-phase mark encoding on the first audio data and the received uncompressed audio data to generate second audio data, comprising:
the transmitting end divides each data bit of the first audio data and the uncompressed audio data into a first sub-data bit and a second sub-data bit in turn according to clock frequency;
if the signal of the data bit is a first level, the transmitting end processes the first sub data bit and the second sub data bit so that the levels of the first sub data bit and the second sub data bit are opposite;
if the signal of the data bit is the second level, the transmitting end processes the first sub data bit and the second sub data bit so that the first sub data bit and the second sub data bit have the same level;
the sending end processes the first sub data bit and the second sub data bit of each data bit to obtain the second audio data;
wherein the clock frequency is twice the transmission frequency of the first audio data and the uncompressed audio data.
4. The method of claim 1, wherein the method further comprises:
The sending end performs error correction coding on pre-stored control data to generate a first control data packet;
the sending end transmits the first control data packet to the receiving end so as to control the sending end to transmit the target audio data to the receiving end.
5. The method of claim 4, wherein the method further comprises:
after receiving a second control data packet sent by the receiving end, the sending end carries out double-phase mark decoding on the second control data packet to generate a pre-transmission control data packet;
and the sending end performs error correction decoding on the pre-transmission control data packet to generate the pre-transmission control data, so that the sending end transmits the first control data packet to the receiving end.
6. The method of claim 5, wherein before the sender generates the pre-transmission control data, further comprising:
the transmitting end performs error correction decoding on the pre-transmission control data packet to generate control data to be checked;
if the control data to be checked does not have the preset error code, the sending end performs parity check on the control data to be checked;
And if the control data to be checked has no parity error, determining that the control data to be checked is the pre-transmission control data, so that the sending end transmits the first control data packet to the receiving end.
7. The method of claim 5, wherein said bi-phase mark decoding said second control data packet to generate a pre-transmission control data packet comprises:
if the signal levels of two adjacent data bits of the data in the second control data packet are opposite, the sending end merges the two adjacent data bits into a decoded data bit of a first level;
if the signal levels of two adjacent data bits of the data in the second control data packet are the same, the sending end merges the two adjacent data bits into a decoded data bit of a second level;
and the sending end combines a plurality of decoded data bits to generate the pre-transmission control data packet.
8. The method of claim 5, wherein the transmitting end performs error correction decoding on the pre-transmission control data packet to generate the pre-transmission control data, comprising:
the sending end carries out data interleaving on even bits of two adjacent data in the pre-transmission control data packet to obtain first interleaving data and second interleaving data;
The transmitting end deletes error correction data bits in the first interleaved data and the second interleaved data to obtain first error correction data and second error correction data;
and after deleting the effective flag bit, the user data bit and the channel state bit of the first error correction data and the second error correction data, the transmitting end merges the obtained data to generate the pre-transmission control data.
9. A chip system, comprising: a processor and a memory coupled, wherein the memory includes program instructions that, when executed by the processor, cause the chip system to perform the method of any of claims 1-8.
10. A display device comprising the chip system of claim 9.
CN202210632775.5A 2022-06-06 2022-06-06 Audio return method, chip system and display device Active CN115174971B (en)

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008117524A1 (en) * 2007-03-26 2008-10-02 Panasonic Corporation Digital broadcast transmitting apparatus, digital broadcast receiving apparatus, and digital broadcast transmitting/receiving system
WO2016060447A2 (en) * 2014-10-14 2016-04-21 엘지전자(주) Device and method for transmitting and receiving data using hdmi
CN106105248A (en) * 2014-03-12 2016-11-09 Lg电子株式会社 For utilizing HDMI to send and receiving the apparatus and method of data
CN107613378A (en) * 2017-09-29 2018-01-19 湖南国科微电子股份有限公司 Audio return method, audio control chip and stereo set
CN109818979A (en) * 2019-03-20 2019-05-28 深圳创维数字技术有限公司 A kind of method, apparatus that realizing audio return, equipment and storage medium
CN110476434A (en) * 2017-04-04 2019-11-19 美国莱迪思半导体公司 Data are controlled by audio return channel transfer common mode
CN112185426A (en) * 2020-09-30 2021-01-05 青岛信芯微电子科技股份有限公司 Voice endpoint detection equipment and method
CN113784074A (en) * 2021-09-24 2021-12-10 广东博华超高清创新中心有限公司 Method for improving intercommunication interconnection of enhanced audio return channel

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11039202B2 (en) * 2019-05-08 2021-06-15 Artilux, Inc. HDMI apparatus using optical communication

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008117524A1 (en) * 2007-03-26 2008-10-02 Panasonic Corporation Digital broadcast transmitting apparatus, digital broadcast receiving apparatus, and digital broadcast transmitting/receiving system
CN106105248A (en) * 2014-03-12 2016-11-09 Lg电子株式会社 For utilizing HDMI to send and receiving the apparatus and method of data
WO2016060447A2 (en) * 2014-10-14 2016-04-21 엘지전자(주) Device and method for transmitting and receiving data using hdmi
CN110476434A (en) * 2017-04-04 2019-11-19 美国莱迪思半导体公司 Data are controlled by audio return channel transfer common mode
CN107613378A (en) * 2017-09-29 2018-01-19 湖南国科微电子股份有限公司 Audio return method, audio control chip and stereo set
CN109818979A (en) * 2019-03-20 2019-05-28 深圳创维数字技术有限公司 A kind of method, apparatus that realizing audio return, equipment and storage medium
CN112185426A (en) * 2020-09-30 2021-01-05 青岛信芯微电子科技股份有限公司 Voice endpoint detection equipment and method
CN113784074A (en) * 2021-09-24 2021-12-10 广东博华超高清创新中心有限公司 Method for improving intercommunication interconnection of enhanced audio return channel

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