CN115174326A - Burst detection and coherent demodulation device and method for high-speed frequency hopping MSK signal - Google Patents
Burst detection and coherent demodulation device and method for high-speed frequency hopping MSK signal Download PDFInfo
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Abstract
The invention discloses a burst detection and coherent demodulation device and a method for a high-speed frequency hopping MSK signal, wherein the device comprises a frequency hopping signal arrival detection module, a frequency offset and initial phase estimation module, a gain adjustment module, a phase-locked loop and bit synchronization module, a bit recovery module and an RAM; the RAM is respectively connected with the frequency hopping signal arrival detection module, the frequency offset and initial phase estimation module, the phase-locked loop and the bit synchronization module, and the phase-locked loop and the bit synchronization module are also respectively connected with the gain adjustment module and the bit recovery module; the input end of the frequency hopping signal arrival detection module is connected with the DDC module. The invention has good noise and frequency deviation resistance. A phase difference correction method based on DFT interpolation is adopted for the frequency deviation and initial phase estimation of the received signals, and accurate estimation of the frequency deviation and the initial phase can be achieved. The conventional costas loop is improved, so that the MSK signal phase is locked to 0, pi/2, pi and-pi/2 points, phase jump can be effectively reduced, the signal demodulation stability is improved, and the error rate is reduced.
Description
Technical Field
The invention relates to a burst detection and coherent demodulation device and method for high-speed (hop rate is more than 500 hops/second) frequency hopping MSK signals in non-cooperative communication, which are mainly used in the field of communication countermeasure and aim at real-time reconnaissance and interpretation of unknown wireless signals of enemies to acquire information.
Background
The MSK is used as a constant envelope digital modulation technology, has higher frequency band utilization rate and lower requirements on the dynamic range of a power device, so that the MSK signal is widely used in frequency hopping communication.
For the detection of the frequency hopping signal, there are mainly an energy detection method, a correlation detection method, and the like. The energy detection double-window sliding method is widely applied and has small calculated amount, but has the problems that the signal starting position cannot be accurately judged, the anti-noise energy is poor and the like. The research on the synchronization technology in the chapter-ball and CPM burst transmission system [ D ]. Chengdu: 2016, university of electronic technology, adopts a synchronization head waveform cross-correlation method to detect the frame synchronization position, and the principle is that when the frame synchronization heads are aligned, a correlation peak occurs.
MSK signal demodulation is divided into coherent demodulation and noncoherent demodulation, wherein for demodulation of high-speed frequency hopping MSK, the problem of long locking time exists when coherent demodulation is realized by a phase-locked loop, and the phase-locked loop cannot be directly applied to MSK frequency hopping demodulation, so noncoherent demodulation is mostly adopted, for example, in the document, "high-text agile. Differential 1bit incoherent demodulation is adopted in Nanjing university of Richardship, 2012 >.
Therefore, the prior art has defects in high-speed frequency hopping MSK signal demodulation, cannot be applied in engineering, and needs a new signal processing algorithm to realize.
Study of synchronization technology in octopus-CPM burst transmission system [ D ]. Achievements: 2016, the electronics science and technology university adopts a synchronous head waveform cross-correlation method to detect the frame synchronization position, in order to meet the detection accuracy in frequency offset, 5 paths of local modulated sequences with frequency offset are preset, 5 paths of local sequences are simultaneously related to a received signal, and finally, one path of the local modulated sequences with the maximum frequency offset is selected as a detection result.
The MSK signal and the OQPSK signal have higher similarity, and fig. 1 is a forty-first research institute of china electronic technology group corporation, a non-data-aided OQPSK signal closed-loop carrier synchronization method: a costas phase-locked loop principle block diagram adopted by China 201410531403.9, P, 2014-10-10 is subjected to bit synchronization after DDC and then sent to a square spectrum estimation module, a phase discrimination module and a frequency discrimination module. The document adopts square spectrum estimation to perform frequency rough estimation, the phase-locked loop comprises a phase detector and a frequency detector, and the error output is the sum of the phase detector and the frequency detector.
In the aspect of MSK signal detection, research on synchronization technology in the Octopus CPM burst transmission system [ D ] becomes: the frame synchronization detection aspect of 2016, university of electronic technology, has a weak point of sensitivity to frequency offset, and when the frequency offset is large, a correlation peak is completely submerged, because when the frequency offset exists, a local sequence and a receiving sequence cannot be completely aligned, and the frequency offset causes that the result after correlation is not a direct current quantity, but a complex sinusoidal signal.
In the aspect of MSK signal demodulation, a forty-first research institute of Chinese electronic technology group company provides a non-data-aided OQPSK signal closed-loop carrier synchronization method, which comprises the following steps: the Costas loop phase detector of China 201410531403.9[ P ].2014-10-10 ] does not exclude the influence of a critical point on phase detection, and is easy to cause phase oscillation, and the Costas phase detection method is finally locked to the points of pi/4, 3 pi/4, -3 pi/4 and-pi/4, and cannot meet the requirements of locking the phase to 0, pi/2, pi and-pi/2.
Dian bridge. Research and realization of channelized reception of frequency hopping signals and parameter estimation thereof [ M ]. Nanjing: nanjing university of science, 2016:15-20, a channelized receiver is adopted to detect an intermediate frequency signal in real time, so that the channelized receiver can greatly save FPGA resources, but once fs and a decimation multiple D are determined, a channel bandwidth is also determined, and the channelized receiver also has a blind zone, that is, a part of frequency bands between two adjacent channels are transition zones of a filter, and cannot receive the signal. If an aliasing design is used, there is overlap of adjacent channels. The demodulation mode of the scheme adopts 1bit differential demodulation, and the 1bit differential demodulation is insensitive to frequency offset and phase, but has the problem of high error rate.
Lee is a multi-core DSP design method for frequency hopping signal demodulation [ J ] electronic design engineering, 1 month in 2020: 158-162 adopts the frequency point of the real-time detection frequency hopping signal, and the demodulation adopts the multi-core DSP to realize 1bit differential demodulation, and the problem of high incoherent demodulation error rate also exists.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a novel anti-noise and anti-frequency offset circuit which has good anti-noise and anti-frequency offset capabilities; by adopting the phase difference correction method based on DFT interpolation, the burst detection and coherent demodulation device of the high-speed frequency hopping MSK signal can realize the accurate estimation of the frequency offset and the initial phase, and provides a corresponding burst detection and coherent demodulation method.
The purpose of the invention is realized by the following technical scheme: a burst detection and coherent demodulation device of a high-speed frequency hopping MSK signal comprises a frequency hopping signal arrival detection module, a frequency offset and initial phase estimation module, a gain adjustment module, a phase-locked loop and bit synchronization module, a bit recovery module and an RAM; the RAM is respectively connected with the frequency hopping signal arrival detection module, the frequency offset and initial phase estimation module, the phase-locked loop and the bit synchronization module, and the phase-locked loop and the bit synchronization module are also respectively connected with the gain adjustment module and the bit recovery module; and the input end of the frequency hopping signal arrival detection module is connected with the DDC module.
Further, the frequency hopping signal arrival detection module is configured to perform baseband modulation on the UW sequence to obtain a new IQ sequence; carrying out sliding correlation operation on the new IQ sequence and a baseband IQ sequence output by the DDC module, generating a correlation peak when the two sequences are in sliding alignment, wherein the position of the correlation peak is the starting position of a frequency hopping signal, and continuously storing a section of length of IQ sequence from the starting position of the frequency hopping signal into an RAM (random access memory) to obtain the IQ sequence of the frequency hopping signal;
a frequency offset and initial phase estimation module: reading one-jump IQ sequence from RAM, and performing demodulation operation to obtain complex sine sequence IQ de IQ is interpolated by DFT de Frequency estimation and initial phase estimation are carried out to obtain a sum of delta f
A sum of Δ f
Writing inRAM；
A gain adjustment module: calculating the average power of IQ data of each hop in the RAM, and dynamically adjusting a gain factor by using the average power;
phase-locked loop and bit synchronization module: fetching a one-hop IQ sequence in RAM, and Δ f and
the IQ sequence is multiplied by a gain factor and then sent to a phase-locked loop and a bit synchronization module, and the sum is calculated by delta f
As the frequency deviation and initial phase of the phase-locked loop, performing phase locking by adopting a modified costas phase discrimination method, and performing bit synchronization by using a gardner algorithm;
a bit recovery module: and respectively carrying out differential operation on the I and Q sequences output by the phase-locked loop and the bit synchronization module, carrying out differential encoding after combining to restore original information, comparing the restored information with the original UW sequence, counting the number of UW error bits, if the number of the error bits exceeds a set threshold, indicating that the frequency hopping detection is false alarm, discarding the demodulation data, otherwise, outputting the demodulation data.
Furthermore, two identical modules are adopted for phase-locked loop and bit synchronization, and the two modules are crossed to perform data processing; each path of module comprises a bit synchronization initialization unit, a bit synchronization unit, a phase discriminator, a loop filter, a phase generation unit, a DDS (direct digital synthesizer) and an initial phase initialization unit; the bit synchronization initialization unit reads data from the RAM, the bit synchronization unit is respectively connected with the bit synchronization initialization unit, the DDS, the phase discriminator and the bit recovery module, the loop filter is respectively connected with the phase discriminator and the phase generation unit, the phase generation unit is respectively connected with the DDS and the initial phase initialization unit, and the DDS and the initial phase initialization unit are respectively connected with the RAM.
Another object of the present invention is to provide a burst detection and coherent demodulation method for high-speed frequency hopping MSK signals, comprising the following steps:
s1, carrying out frequency hopping signal arrival detection, specifically comprising the following steps: if the length of the UW sequence is 64 bits and the sampling rate is 4 times of the information rate, thenIQ obtained by performing baseband modulation on UW sequence uw The sequence length is 256; then to IQ according to the following formula uw The sequence and baseband signal IQ are cross-correlated:
wherein k =1,2,3, \ 8230;, 256,
representing IQ uw Sequence ith value, conj () represents the conjugate;
then, modulo the corre (k) to obtain a result which is marked as abs _ corre (k);
window sliding calculation is performed on abs _ corre (k) using a window size of 256: dividing the middle value of the abs _ core (k) sliding window by the average value in the window to obtain div (k); div (k) is compared with a preset threshold th, if the value exceeds th, the arrival of a frequency hopping signal is detected, k corresponding to the maximum value of abs _ corre (k) is the starting position of the frequency hopping signal, and a one-hop IQ sequence is continuously saved from the starting position of the frequency hopping signal as the frequency hopping signal and is stored in the RAM;
s2, carrying out frequency offset and initial phase estimation, wherein the specific implementation method comprises the following steps:
s21, taking out the one-hop IQ sequence from the RAM, and calculating a demodulation sequence according to the following formula:
IQ (i) refers to the ith value of the IQ sequence;
s22, mixing
Is divided into a set of data, denoted IQ de1 ；
Divided into another set of data, denoted IQ de2 ；
S23, respectively performing DFT on the two groups of data, and recording the result as DFT1 and DFT2;
s24, solving the position corresponding to the maximum of any one group of modes in DFT1 and DFT2 as j;
s25, calculating phase angles of j positions of the first group and the second group
And
a range of values (-pi, pi); and calculating the phase angle difference:
s26, making delta = delta phi +2 pi k, and converting delta into a range of (-pi, pi);
s27, dividing the delta by 2 pi to obtain normalized delta, wherein the range is [ -0.5,0.5];
s28, calculating frequency deviation delta f = (k-delta) × fs/N, wherein fs is a sampling rate, and N is a DFT conversion point number;
s29, calculating an initial phase angle
S3, phase-locked loop and bit synchronization operation, wherein the specific method comprises the following steps:
s31, reading the initial phase angle from the RAM
And frequency deviation delta f, and initializing a phase generation module as an initial phase of the DDS to complete initial phase correction and frequency correction;
s32, initializing a first sampling point of the IQ sequence as an optimal sampling point by bit synchronization, performing one-time bit synchronization on every two code elements by adopting a gardner algorithm, outputting 3 IQ values, and sending the IQ values to a phase discriminator;
s33, the phase discriminator performs phase discrimination by respectively adopting a modified costas phase discrimination method according to the 3 IQ values, then takes the average value of the 3 phases as the phase discrimination output, obtains the phase correction quantity after the output passes through a second-order loop filter of an integral link and a proportional link, and feeds the phase correction quantity back to a phase generator to control a DDS (direct digital synthesizer) so as to complete the phase locking function;
the concrete realization method of the modified costas phase discrimination method comprises the following steps: respectively taking the phases of the I and Q sequences as a horizontal axis and a vertical axis, and taking the phase identical point as an origin to establish a two-dimensional coordinate system; dividing a region with the slope of +/-0.2 around a straight line with the slope of +/-0.5 into a non-phase discrimination region, and then carrying out phase discrimination by using a costas phase discrimination method;
s34, after the DDS completes the phase locking function, the bit synchronization module outputs synchronous IQ data to be sent to the bit recovery module;
s4, bit recovery is carried out: eliminating zero crossing points of the IQ data obtained by the last module to obtain IQ data without redundant information; respectively judging the paths I and Q as 0 and 1, and respectively carrying out XOR of front and rear bits on the paths I and Q, and then combining the paths; carrying out differential encoding on the combined data to recover original information; and then comparing the recovered information with the original UW sequence, counting the number of UW error bits, if the number of the error bits exceeds a set threshold, indicating that the frequency hopping detection is false alarm, discarding the demodulation data, otherwise, outputting the demodulation data.
The invention has the beneficial effects that:
1. the correlation detection algorithm used by the invention carries out convolution operation four-term multiplication accumulation on the baseband IQ sequence and a new IQ sequence obtained after the UW sequence baseband modulation, the accumulation result is subjected to modulo calculation, a correlation peak appears when the two sequences are in sliding alignment, the arrival of a burst signal is detected, and the point with the maximum correlation peak corresponds to the starting point of a burst frame. The algorithm is applied to burst detection, has good anti-noise and anti-frequency deviation capabilities, the frequency deviation can reach 50% of the code element rate, and compared with common correlation detection (two-term multiplication and accumulation), the anti-frequency deviation capability is weaker (less than 10% of the code element rate), and the anti-frequency deviation capability is obviously improved.
2. The phase difference correction method based on DFT interpolation is adopted for the frequency offset and initial phase estimation of the received signal, so that the frequency offset and initial phase can be accurately estimated, and the frequency estimation error is within +/-100 Hz (under the ideal noiseless condition, the frequency estimation is error-free). Accurate frequency estimates help to lock onto the signal quickly during coherent demodulation.
3. The conventional costas loop is improved, the MSK signal phase is locked to 0, pi/2, pi and-pi/2 points, and no phase estimation is carried out on points near pi/4, 3 pi/4, -3 pi/4 and-pi/4, so that the phase jump can be effectively reduced, the demodulation stability is improved, and the error rate is reduced.
4. The invention completes the burst detection and coherent demodulation of the frequency hopping signal under the condition of unknown frequency hopping sequence, solves the problem that the blind reception coherent demodulation of the frequency hopping signal is difficult to synchronize, improves the error code performance, and is beneficial to obtaining the enemy situation report information under the low signal-to-noise ratio.
Drawings
FIG. 1 illustrates a conventional phase-locked loop implementation;
FIG. 2 is a schematic diagram of a burst detection and coherent demodulation apparatus for high-speed frequency-hopping MSK signals according to the present invention;
FIG. 3 is a schematic diagram of a phase-locked loop and a bit synchronization module;
FIG. 4 is a schematic view of a window sliding calculation;
FIG. 5 is a schematic phase discrimination diagram;
FIG. 6 is a constellation diagram after locking;
fig. 7 is a graph of the error rate.
Detailed Description
The technical scheme of the invention is further explained by combining the attached drawings.
As shown in fig. 2, a burst detection and coherent demodulation apparatus for high-speed frequency hopping MSK signals includes a frequency hopping signal arrival detection module, a frequency offset and initial phase estimation module, a gain adjustment module, a phase-locked loop and bit synchronization module, a bit recovery module, and an RAM; the RAM is respectively connected with the frequency hopping signal arrival detection module, the frequency offset and initial phase estimation module, the phase-locked loop and the bit synchronization module, and the phase-locked loop and the bit synchronization module are also respectively connected with the gain adjustment module and the bit recovery module; and the input end of the frequency hopping signal arrival detection module is connected with the DDC module. The frequency hopping signal arrival detection module has N detection channels, and the N detection channels correspondingly detect N different frequency points, such as N =16, 32, and the like; each detection channel is respectively connected with different frequency point processing units of a DDC (digital down conversion) module, and the input of the DDC module is an intermediate frequency signal.
The frequency hopping signal arrival detection module is used for carrying out baseband modulation on the UW sequence to obtain a new IQ sequence; carrying out sliding correlation operation on the new IQ sequence and a baseband IQ sequence output by the DDC module, wherein a correlation peak appears when the two sequences are in sliding alignment, the position of the correlation peak is the starting position of a frequency hopping signal, and IQ sequences with a length are continuously stored in an RAM from the starting position of the frequency hopping signal to obtain an IQ sequence of the frequency hopping signal;
a frequency offset and initial phase estimation module: reading one-jump IQ sequence from RAM, and performing demodulation operation to obtain complex sine sequence IQ de IQ is interpolated by DFT de Frequency estimation and initial phase estimation are carried out to obtain the sum of delta f
A sum of Δ f
Writing into a RAM;
a gain adjustment module: calculating the average power of IQ data of each hop in the RAM, and dynamically adjusting a gain factor by using the average power;
phase-locked loop and bit synchronization module: fetching one-hop IQ sequence in RAM, and Δ f and
multiplying the IQ sequence by a gain factor and sending the result to a phase-locked loop and a bit synchronization module by using the sum of deltaf
As the frequency deviation and initial phase of the phase-locked loop, performing phase locking by adopting a modified costas phase discrimination method, and performing bit synchronization by using a gardner algorithm;
a bit recovery module: and respectively carrying out differential operation on the I and Q sequences output by the phase-locked loop and the bit synchronization module, carrying out differential encoding after combining to restore original information, comparing the restored information with the original UW sequence, counting the number of UW error bits, if the number of the error bits exceeds a set threshold, indicating that the frequency hopping detection is false alarm, discarding the demodulation data, otherwise, outputting the demodulation data.
The phase-locked loop and the bit synchronization adopt two paths of same modules, and the two paths of modules are crossed to perform data processing; as shown in fig. 3, each path of module includes a bit synchronization initialization unit, a bit synchronization unit, a phase discriminator, a loop filter, a phase generation unit, a DDS, and an initial phase initialization unit; the bit synchronization initialization unit reads data from the RAM, the bit synchronization unit is respectively connected with the bit synchronization initialization unit, the DDS, the phase discriminator and the bit recovery module, the loop filter is respectively connected with the phase discriminator and the phase generation unit, the phase generation unit is respectively connected with the DDS and the initial phase initialization unit, and the DDS and the initial phase initialization unit are respectively connected with the RAM.
A burst detection and coherent demodulation method of high-speed frequency hopping MSK signals comprises the following steps:
s1, carrying out frequency hopping signal arrival detection, specifically comprising the following steps: if the length of the UW sequence is 64 bits and the sampling rate is 4 times the information rate (the code rate of the transmission signal), the IQ obtained by baseband modulation of the UW sequence uw The sequence length is 256; then to IQ according to the following formula uw And performing cross-correlation calculation on the sequence and a baseband signal IQ:
wherein k =1,2,3, \ 8230;, 256,
representing IQ uw Sequence ith value, conj () represents the conjugate;
then, modulo the corre (k) to obtain a result as a correlation value, and marking the result as abs _ corre (k);
the abs _ corre (k) is window-sliding calculated using a window of 256 size, as shown in fig. 4: dividing the middle value of the abs _ corre (k) sliding window by the average value in the window to obtain div (k); div (k) is compared with a preset threshold th, if the value exceeds th, the arrival of a frequency hopping signal is detected, k corresponding to the maximum value of abs _ corre (k) is the starting position of the frequency hopping signal, and a hop of IQ sequence is continuously stored from the starting position of the frequency hopping signal as the frequency hopping signal and is stored in the RAM;
s2, carrying out frequency offset and initial phase estimation, wherein the specific implementation method comprises the following steps:
s21, taking out the one-hop IQ sequence from the RAM, and calculating a demodulation sequence according to the following formula:
IQ (i) refers to the ith value of the IQ sequence;
s22, mixing
Divided into a set of data, denoted IQ de1 ；
Divided into another set of data, denoted IQ de2 ；
S23, respectively performing DFT on the two groups of data, and recording the result as DFT1 and DFT2;
s24, solving the position corresponding to the maximum of any one group of modes in DFT1 and DFT2 as j;
s25, calculating phase angles of j positions of the first group and the second group
And
a range of values (-pi, pi); and calculating the phase angle difference:
s26, making delta = delta phi +2 pi k, and converting delta into a range of (-pi, pi);
s27, dividing the delta by 2 pi to obtain normalized delta, wherein the range is [ -0.5,0.5];
s28, calculating frequency deviation delta f = (k-delta) × fs/N, wherein fs is a sampling rate, and N is a DFT conversion point number;
S29、calculating an initial phase angle
S3, phase-locked loop and bit synchronization operation, wherein the specific method comprises the following steps:
s31, reading the initial phase angle from the RAM
And frequency deviation delta f, and initializing a phase generation module to serve as an initial phase of the DDS, completing initial phase correction and frequency correction, and sending the corrected IQ to a bit synchronization module;
s32, initializing a first sampling point of the IQ sequence as an optimal sampling point by bit synchronization, performing one-time bit synchronization on every two code elements by adopting a gardner algorithm, outputting 3 IQ values, and sending the IQ values to a phase discriminator;
s33, the phase discriminator performs phase discrimination by respectively adopting a modified costas phase discrimination method according to the 3 IQ values, then takes the average value of the 3 phases as the phase discrimination output, obtains the phase correction quantity after the output passes through a second-order loop filter of an integral link and a proportional link, and feeds the phase correction quantity back to a phase generator to control a DDS (direct digital synthesizer) so as to complete the phase locking function;
the concrete realization method of the modified costas phase discrimination method comprises the following steps: respectively taking the phases of the I and Q sequences as a horizontal axis and a vertical axis, and taking the phase identical point as an origin to establish a two-dimensional coordinate system; dividing a region with the slope deviation of +/-0.2 around a straight line with the slope of +/-0.5 into a phase-discrimination region, namely a region between two boundary lines in the graph 5, and then performing phase discrimination by using a costas phase discrimination method; the black solid point in the figure is an ideal locking point, when the IQ point falls in a plus region, which indicates that the phase shifts clockwise, a positive value is output to a loop filter, the DDS phase is increased step by step, and the phase is corrected to minus; similarly, when the IQ point falls within the "-" region, indicating that the phase is shifted counterclockwise, a negative value is output to the loop filter, and the DDS phase step decreases to correct the phase toward "+"; when IQ falls in a non-phase discrimination area far away from an ideal point, the fact that the sample is greatly influenced by noise and does not participate in phase discrimination is shown, and the anti-noise level is improved through the operation. The actual measurement shows that the slope of the boundary is about 0.7, and the effect is most obvious.
S34, after the DDS completes the phase-locking function, the bit synchronization module outputs synchronous IQ data (shown as an IQ constellation after phase-locking, as shown in fig. 6) to the bit recovery module;
s4, carrying out bit recovery: eliminating zero crossing points of the IQ data obtained by the last module to obtain IQ data without redundant information; respectively judging the paths I and Q as 0 and 1, and respectively carrying out XOR of front and rear bits on the paths I and Q, and then combining the paths; carrying out differential encoding on the combined data to recover original information; and then comparing the recovered information with the original UW sequence, counting the number of UW error bits, if the number of the error bits exceeds a set threshold, indicating that the frequency hopping detection is false alarm, discarding the demodulation data, otherwise, outputting the demodulation data.
The method of the invention can obtain better error code performance under lower signal-to-noise ratio, and is far superior to the MSK incoherent demodulation method under high-speed frequency hopping, and the actually measured performance parameters are as follows:
the phase-locked loop enters a lock threshold: e b /N 0 ＝8dB；
Error rate:
when E is b /N 0 ＝8dB，BER＝1.5e-3；
When E is b /N 0 ＝9dB，BER＝3.1e-4；
When E is b /N 0 ＝10dB，BER＝5.2e-5；
When E is b /N 0 ＝11dB，BER＝4.0e-6；
The graph of the error rate is shown in fig. 7.
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
Claims (4)
1. A burst detection and coherent demodulation device of a high-speed frequency hopping MSK signal is characterized by comprising a frequency hopping signal arrival detection module, a frequency offset and initial phase estimation module, a gain adjustment module, a phase-locked loop and bit synchronization module, a bit recovery module and an RAM; the RAM is respectively connected with the frequency hopping signal arrival detection module, the frequency offset and initial phase estimation module, the phase-locked loop and the bit synchronization module, and the phase-locked loop and the bit synchronization module are also respectively connected with the gain adjustment module and the bit recovery module; and the input end of the frequency hopping signal arrival detection module is connected with the DDC module.
2. The burst detection and coherent demodulation apparatus of a high-speed frequency-hopping MSK signal according to claim 1, wherein the frequency-hopping signal arrival detection module is configured to perform baseband modulation on the UW sequence to obtain a new IQ sequence; carrying out sliding correlation operation on the new IQ sequence and a baseband IQ sequence output by the DDC module, generating a correlation peak when the two sequences are in sliding alignment, wherein the position of the correlation peak is the starting position of a frequency hopping signal, and continuously storing IQ sequences with a certain length from the starting position of the frequency hopping signal into an RAM (random access memory) to obtain an IQ sequence of the frequency hopping signal;
a frequency offset and initial phase estimation module: reading one-jump IQ sequence from RAM, and performing demodulation operation to obtain complex sine sequence IQ de IQ is interpolated by DFT de Frequency estimation and initial phase estimation are carried out to obtain the sum of delta f
A sum of Δ f
Writing into a RAM;
a gain adjustment module: calculating the average power of IQ data of each hop in the RAM, and dynamically adjusting a gain factor by using the average power;
phase-locked loop and bit synchronization module: fetching a one-hop IQ sequence in RAM, and Δ f and
the IQ sequence is multiplied by a gain factor and then sent to a phase-locked loop and a bit synchronization module, and the sum is calculated by delta f
As the frequency deviation and initial phase of the phase-locked loop, performing phase locking by adopting a modified costas phase discrimination method, and performing bit synchronization by using a gardner algorithm;
a bit recovery module: and respectively carrying out differential operation on the I and Q sequences output by the phase-locked loop and the bit synchronization module, carrying out differential coding after combining to restore original information, comparing the restored information with the original UW sequence, counting the number of UW error bits, if the number of the error bits exceeds a set threshold, indicating that the frequency hopping detection is false alarm, discarding the demodulation data, otherwise, outputting the demodulation data.
3. The burst detection and coherent demodulation apparatus for high-speed frequency-hopping MSK signals according to claim 1, wherein the phase-locked loop and the bit synchronization employ two identical modules, and the two modules are interleaved for data processing; each path of module comprises a bit synchronization initialization unit, a bit synchronization unit, a phase discriminator, a loop filter, a phase generation unit, a DDS (direct digital synthesizer) and an initial phase initialization unit; the bit synchronization initialization unit reads data from the RAM, the bit synchronization unit is respectively connected with the bit synchronization initialization unit, the DDS, the phase discriminator and the bit recovery module, the loop filter is respectively connected with the phase discriminator and the phase generation unit, the phase generation unit is respectively connected with the DDS and the initial phase initialization unit, and the DDS and the initial phase initialization unit are respectively connected with the RAM.
4. A method for burst detection and coherent demodulation of a high-speed frequency hopping MSK signal according to any one of claims 1 to 3, comprising the steps of:
s1, carrying out frequency hopping signal arrival detection, specifically comprising the following steps: if the length of the UW sequence is 64 bits and the sampling rate is 4 times of the information rate, IQ obtained by performing baseband modulation on the UW sequence uw The sequence length is: 64 × 4=256; then to IQ according to the following formula uw The sequence and baseband signal IQ are cross-correlated:
wherein k =1,2,3, \8230;, 256,
representing IQ uw Sequence ith value, conj () represents the conjugate;
then, modulo the corre (k) to obtain a result which is marked as abs _ corre (k);
window sliding calculation is performed on abs _ corre (k) using a window of 256 size: dividing the middle value of the abs _ corre (k) sliding window by the average value in the window to obtain div (k); div (k) is compared with a preset threshold th, if the value exceeds th, the arrival of a frequency hopping signal is detected, k corresponding to the maximum value of abs _ corre (k) is the starting position of the frequency hopping signal, and a hop of IQ sequence is continuously stored from the starting position of the frequency hopping signal as the frequency hopping signal and is stored in the RAM;
s2, carrying out frequency offset and initial phase estimation, wherein the specific implementation method comprises the following steps:
s21, taking out the one-hop IQ sequence from the RAM, and calculating a demodulation sequence according to the following formula:
IQ (i) refers to the ith value of the IQ sequence;
s22, mixing
Is divided into a set of data, denoted IQ de1 ；
Divided into another set of data, denoted IQ de2 ；
S23, respectively performing DFT on the two groups of data, and recording the result as DFT1 and DFT2;
s24, solving the position corresponding to any one group of the mode maximums of the DFT1 and the DFT2 and recording as j;
s25, calculating phase angles of j positions of the first group and the second group
And
a range of values (-pi, pi); and calculating the phase angle difference:
s26, making delta = delta phi +2 pi k, and converting delta into a range of (-pi, pi);
s27, dividing the delta by 2 pi to obtain normalized delta, wherein the range is [ -0.5,0.5];
s28, calculating frequency deviation delta f = (k-delta) × fs/N, wherein fs is a sampling rate, and N is a DFT conversion point number;
s29, calculating an initial phase angle
S3, phase-locked loop and bit synchronization operation, wherein the specific method comprises the following steps:
s31, reading the initial phase angle from the RAM
And frequency deviation delta f, and initializing a phase generation module as an initial phase of the DDS to complete initial phase correction and frequency correction;
s32, initializing a first sampling point of the IQ sequence as an optimal sampling point by bit synchronization, performing one-time bit synchronization on every two code elements by adopting a gardner algorithm, outputting 3 IQ values, and sending the IQ values to a phase discriminator;
s33, the phase discriminator performs phase discrimination by respectively adopting a modified costas phase discrimination method according to the 3 IQ values, then takes the average value of the 3 phases as the phase discrimination output, obtains the phase correction quantity after the output passes through a second-order loop filter of an integral link and a proportional link, and feeds the phase correction quantity back to a phase generator to control a DDS (direct digital synthesizer) so as to complete the phase locking function;
the concrete realization method of the modified costas phase discrimination method comprises the following steps: respectively taking the phases of the I and Q sequences as a horizontal axis and a vertical axis, and taking the phase identical point as an origin to establish a two-dimensional coordinate system; dividing a region with the slope of +/-0.2 around a straight line with the slope of +/-0.5 into a phase-discrimination region, and then carrying out phase discrimination by using a costas phase discrimination method;
s34, after the DDS completes the phase locking function, the bit synchronization module outputs synchronous IQ data and sends the synchronous IQ data to the bit recovery module;
s4, carrying out bit recovery: eliminating zero crossing points of the IQ data obtained by the last module to obtain IQ data without redundant information; respectively judging the paths I and Q as 0 and 1, and respectively carrying out XOR of front and rear bits on the paths I and Q, and then combining the paths; carrying out differential encoding on the combined data to recover original information; and then comparing the recovered information with the original UW sequence, counting the number of error bits of the UW, if the number of the error bits exceeds a set threshold, indicating that the frequency hopping detection is false alarm, discarding the demodulation data, otherwise, outputting the demodulation data.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116055271A (en) * | 2023-01-13 | 2023-05-02 | 重庆大学 | Burst signal detection method of double sliding windows under specific waveform structure |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070025476A1 (en) * | 2005-07-28 | 2007-02-01 | Itt Manufacturing Enterprises, Inc. | Fast digital carrier frequency error estimation algorithm using synchronization sequence |
| WO2010142168A1 (en) * | 2009-06-09 | 2010-12-16 | 中兴通讯股份有限公司 | Ofdm signal demodulation method and device thereof |
| CN103078818A (en) * | 2013-01-06 | 2013-05-01 | 中国电子科技集团公司第十研究所 | Method for improving incoherent detection performance of MSK (minimum shift keying) signals |
| CN105721375A (en) * | 2016-03-28 | 2016-06-29 | 电子科技大学 | Low signal-to-noise ratio short preamble burst signal demodulation system and method |
| CN106856463A (en) * | 2017-01-20 | 2017-06-16 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | MSK/GMSK coherent demodulation processing systems |
| CN107359941A (en) * | 2017-08-02 | 2017-11-17 | 哈尔滨工业大学深圳研究生院 | A kind of method that optical communication system frequency deviation cycle slip is monitored and corrected in real time |
| CN108429712A (en) * | 2018-03-12 | 2018-08-21 | 中国人民解放军国防科技大学 | OFDM-based wireless communication time-frequency synchronization method |
| CN108494714A (en) * | 2018-03-22 | 2018-09-04 | 桂林电子科技大学 | A method of quickly overcoming the GMSK coherent demodulations of Doppler frequency shift |
| CN110300079A (en) * | 2019-07-19 | 2019-10-01 | 北京理工大学 | A kind of msk signal coherent demodulation method and system |
| CN113489664A (en) * | 2021-09-06 | 2021-10-08 | 杭州万高科技股份有限公司 | Wireless frequency shift keying communication frequency offset compensation circuit and method |
-
2022
- 2022-06-16 CN CN202210678485.4A patent/CN115174326B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070025476A1 (en) * | 2005-07-28 | 2007-02-01 | Itt Manufacturing Enterprises, Inc. | Fast digital carrier frequency error estimation algorithm using synchronization sequence |
| WO2010142168A1 (en) * | 2009-06-09 | 2010-12-16 | 中兴通讯股份有限公司 | Ofdm signal demodulation method and device thereof |
| CN103078818A (en) * | 2013-01-06 | 2013-05-01 | 中国电子科技集团公司第十研究所 | Method for improving incoherent detection performance of MSK (minimum shift keying) signals |
| CN105721375A (en) * | 2016-03-28 | 2016-06-29 | 电子科技大学 | Low signal-to-noise ratio short preamble burst signal demodulation system and method |
| CN106856463A (en) * | 2017-01-20 | 2017-06-16 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | MSK/GMSK coherent demodulation processing systems |
| CN107359941A (en) * | 2017-08-02 | 2017-11-17 | 哈尔滨工业大学深圳研究生院 | A kind of method that optical communication system frequency deviation cycle slip is monitored and corrected in real time |
| CN108429712A (en) * | 2018-03-12 | 2018-08-21 | 中国人民解放军国防科技大学 | OFDM-based wireless communication time-frequency synchronization method |
| CN108494714A (en) * | 2018-03-22 | 2018-09-04 | 桂林电子科技大学 | A method of quickly overcoming the GMSK coherent demodulations of Doppler frequency shift |
| CN110300079A (en) * | 2019-07-19 | 2019-10-01 | 北京理工大学 | A kind of msk signal coherent demodulation method and system |
| CN113489664A (en) * | 2021-09-06 | 2021-10-08 | 杭州万高科技股份有限公司 | Wireless frequency shift keying communication frequency offset compensation circuit and method |
Non-Patent Citations (1)
| Title |
|---|
| 贾哲;张欣轶;: "微波通信中连续相位调制的非相干检测算法", 电波科学学报, no. 03 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116055271A (en) * | 2023-01-13 | 2023-05-02 | 重庆大学 | Burst signal detection method of double sliding windows under specific waveform structure |
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Denomination of invention: Burst detection and coherent demodulation device and method for high-speed frequency hopping MSK signals Granted publication date: 20230922 Pledgee: Chengdu Rural Commercial Bank Co.,Ltd. Qingyang Branch Pledgor: Chengdu Century Science Park Electronic Co.,Ltd. Registration number: Y2024980002947 |