CN115171764A - Anti-fuse array architecture and memory - Google Patents

Anti-fuse array architecture and memory Download PDF

Info

Publication number
CN115171764A
CN115171764A CN202210664729.3A CN202210664729A CN115171764A CN 115171764 A CN115171764 A CN 115171764A CN 202210664729 A CN202210664729 A CN 202210664729A CN 115171764 A CN115171764 A CN 115171764A
Authority
CN
China
Prior art keywords
signal
antifuse
sub
selection
selection unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210664729.3A
Other languages
Chinese (zh)
Inventor
陈啸宸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to CN202210664729.3A priority Critical patent/CN115171764A/en
Publication of CN115171764A publication Critical patent/CN115171764A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing

Abstract

The disclosed embodiment relates to the field of semiconductor circuit design, in particular to an antifuse array architecture and a memory, wherein the antifuse array architecture comprises: a plurality of antifuse memory arrays, wherein different antifuse memory arrays are driven based on different clock signals; the first control module is coupled with the plurality of antifuse memory arrays and configured to generate a sub-clock signal based on the initial clock signal and the plurality of selection signals, wherein the sub-clock signal is used for driving a corresponding antifuse memory array. The embodiment of the disclosure designs a new anti-fuse array architecture to introduce more anti-fuse memory cells, and the modification of the logic circuit in the anti-fuse circuit is small, so that the anti-fuse array architecture is suitable for DRAM chips with increasingly increased integration level.

Description

Anti-fuse array architecture and memory
Technical Field
The present disclosure relates to the field of semiconductor circuit design, and more particularly, to an antifuse array architecture and a memory.
Background
The anti-fuse memory unit is composed of a switch transistor and a fuse transistor, the anti-fuse memory unit comprises two states, wherein one state is an unblown state in a normal state, the other state is a blown state after the fuse transistor is broken down, and the anti-fuse memory unit forms stored information through different states.
For an antifuse Memory cell in a Dynamic Random Access Memory (DRAM), information stored in the antifuse Memory cell has three main uses: (1) for DRAM rank patching; (2) for DRAM row repair; (3) DFT (Design for testing) test for chips.
As the integration level of DRAM chips increases, the demands for DRAM column repair, DRAM row repair, and DFT testing of the chips are also increasing, so that the current demand for the number of antifuse memory cells in DRAM chips is also increasing.
At present, in order to increase the number of the anti-fuse memory cells, the number of the anti-fuse memory cells in the anti-fuse memory array is generally directly increased, but the increased number of the anti-fuse memory cells in this way needs great modification on logic circuits in the anti-fuse circuit, and is not suitable for DRAM chips with increasingly increased integration level.
Disclosure of Invention
The embodiment of the disclosure provides an antifuse array architecture and a memory, and designs a new antifuse array architecture to introduce more antifuse memory arrays and antifuse memory cells, and the change of a logic circuit in an antifuse circuit is small, so that the antifuse array architecture and the memory are suitable for DRAM chips with increasingly increased integration.
An embodiment of the present disclosure provides an antifuse array architecture, including: a plurality of antifuse memory arrays, wherein different antifuse memory arrays are driven based on different clock signals; the first control module is coupled with the plurality of anti-fuse memory arrays and is configured to generate a sub-clock signal based on the initial clock signal and a plurality of selection signals, and the sub-clock signal is used for driving a corresponding one of the anti-fuse memory arrays.
Selectively providing a sub-clock signal to the antifuse memory array by increasing the number of the antifuse memory array to drive the antifuse memory array; a plurality of antifuse memory arrays are introduced, the number of antifuse memory cells is increased, the antifuse memory cells are realized only by controlling transmission of sub clock signals required by the antifuse memory arrays, and the antifuse memory array is suitable for DRAM chips with the increasing integration level.
In addition, the first control module includes: the signal selection units of each stage respectively receive a selection signal; the second output end of each stage of signal selection unit is used for outputting a sub-clock signal according to the selection signal, the clock signal input end of the first stage of signal selection unit receives an initial clock signal, and the first output end and the second output end of the last stage of signal selection unit are used for outputting the sub-clock signal; the first control module generates N +1 sub-clock signals (a first sub-clock signal to an N +1 sub-clock signal) according to N selection signals (the first selection signal to the nth selection signal), each sub-clock signal is used for conducting a corresponding anti-fuse memory array, and as the N +1 sub-clock signals are respectively used for controlling whether the programming of the N +1 anti-fuse memory array is started or not, only one of the N +1 sub-clock signals is transmitted to the corresponding anti-fuse memory array at the same time, thereby realizing the programming control of a plurality of anti-fuse arrays, realizing the introduction of a large batch of anti-fuse memory units, only needing to control the transmission of the sub-clock signals required by different anti-fuse memory arrays, and being suitable for DRAM chips with increasingly increased integration.
In addition, each selection signal comprises a first sub-selection signal and a second sub-selection signal which are opposite in phase to each other; a signal selection unit comprising: the first selection subunit, an input end is used for receiving the first sub-selection signal, another input end is used as the clock signal input end of the signal selection unit, and the output end is used as the first output end of the signal selection unit; a second selection subunit, one input end of which is used for receiving the second sub-selection signal, the other input end of which is used as the clock signal input end of the signal selection unit, and the output end of which is used as the second output end of the signal selection unit; the first sub-selection signal and the second sub-selection signal are mutually opposite signals, namely, only one of the first sub-selection signal and the second sub-selection signal is an effective signal, namely, only one of the first selection sub-unit and the second selection sub-unit in the same signal selection unit is gated at the same moment, so that the selection and the transmission of the clock signal are realized.
In addition, the first selection subunit comprises a first nand gate, one input end of the first nand gate receives the first sub-selection signal, the other input end of the first nand gate is used as a clock signal input end of the signal selection unit, and the output end of the first nand gate is used as a first output end of the clock of the signal selection unit; the second selection subunit comprises a second nand gate, one input end of the second nand gate receives the second selection signal, the other input end of the second nand gate is used as the clock signal input end of the signal selection unit, and the output end of the second nand gate is used as the second output end of the clock of the signal selection unit.
In addition, each antifuse memory array includes a second control unit configured to generate an internal enable signal based on a program enable signal, a positioning signal, and a sub-clock signal; the programming enable signal is used for starting programming of the anti-fuse memory array, the positioning signal is used for positioning the position of the target anti-fuse memory cell in the anti-fuse memory array, and the internal enable signal is used for enabling the anti-fuse memory array to start programming.
In addition, the internal enable signal includes: a repair package enable signal for enabling the repair package to provide a user self-programmed function; an external command enable signal for enabling an external pin to input a command signal to the antifuse memory array; a logic circuit enable signal for enabling the internal logic circuit of the antifuse memory array; a location check enable signal for enabling the location matching check circuit.
In addition, the number of the antifuse memory arrays is one less than the number of the signal selection units; so that each generated sub-clock signal can selectively drive a corresponding anti-fuse memory array.
In addition, the number of antifuse memory arrays is 3, and the number of signal selection units is 2.
The embodiment of the disclosure also provides a memory, wherein the antifuse memory array in the memory is arranged based on the antifuse array architecture provided by the embodiment; by designing a new anti-fuse array structure, more anti-fuse memory arrays and anti-fuse memory cells are introduced, and the change of a logic circuit in an anti-fuse circuit is small, so that the anti-fuse circuit is suitable for DRAM chips with the increasingly increased integration level.
In addition, the memory includes a first pin for receiving the first sub-selection signal and a second pin for receiving the second sub-selection signal.
Drawings
One or more embodiments are illustrated by corresponding figures in the drawings, which are not to be construed as limiting the embodiments, unless expressly stated otherwise, the drawings are not to scale; in order to more clearly illustrate the embodiments of the present disclosure or technical solutions in the conventional art, the drawings required to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without inventive efforts.
Fig. 1 is a schematic structural diagram of an antifuse array architecture according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a first control module according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a signal selection unit according to an embodiment of the disclosure;
fig. 4 is a schematic structural diagram of a signal selection unit according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a second control module according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of an antifuse memory array in a memory according to another embodiment of the present disclosure.
Detailed Description
As known from the background art, for an antifuse Memory cell in a Dynamic Random Access Memory (DRAM), information stored in the antifuse Memory cell has three main purposes: (1) for DRAM rank patching; (2) for DRAM row repair; (3) DFT (Design for testability) test for chips; as the integration level of DRAM chips increases, the demands for DRAM column repair, DRAM row repair, and chip DFT testing are also increasing, so that the demand for the number of antifuse memory cells in DRAM chips is also increasing at present; at present, in order to increase the number of the anti-fuse memory cells, the number of the anti-fuse memory cells in the anti-fuse memory array is generally directly increased, but the increased number of the anti-fuse memory cells in this way needs great modification on logic circuits in the anti-fuse circuit, and is not suitable for DRAM chips with increasingly increased integration level.
An embodiment of the disclosure provides an antifuse array architecture, which is suitable for DRAM chips with increasingly increased integration levels by designing a new antifuse array architecture to introduce more antifuse memory arrays and antifuse memory cells, and with less modification to logic circuits in an antifuse circuit.
It will be appreciated by those of ordinary skill in the art that in various embodiments of the disclosure, numerous technical details are set forth in order to provide a better understanding of the disclosure. However, the claimed subject matter of the present disclosure can be practiced without these specific details and with various changes and modifications based on the following examples. The following embodiments are divided for convenience of description, and should not constitute any limitation to the specific implementation manner of the present disclosure, and the embodiments may be combined with each other and referred to each other without contradiction.
Fig. 1 is a schematic structural diagram of an antifuse array architecture provided in this embodiment, fig. 2 is a schematic structural diagram of a first control module provided in this embodiment, fig. 3 is a schematic structural diagram of a signal selection unit provided in this embodiment, fig. 4 is a schematic structural diagram of a signal selection unit provided in this embodiment, and fig. 5 is a schematic structural diagram of a second control module provided in this embodiment, and the following detailed description is provided for the antifuse array architecture provided in this embodiment with reference to the drawings, and is as follows:
referring to fig. 1, an antifuse array architecture, comprising:
a plurality of antifuse memory arrays 100, wherein different antifuse memory arrays are driven based on different clock signals.
The first control module 101, coupled to the plurality of antifuse memory arrays 100, is configured to generate a sub-clock signal based on an initial clock signal and a plurality of selection signals, the sub-clock signal being used to drive a corresponding one of the antifuse memory arrays.
It should be noted that the above-mentioned "coupling" may be set as a direct connection or an indirect connection in a specific application, and this embodiment does not constitute a limitation that the first control module 101 is directly connected to the plurality of antifuse memory arrays 100 or the first control module 101 is indirectly connected to the plurality of antifuse memory arrays 100.
In the embodiment, the number of the anti-fuse memory arrays is increased, and the sub-clock signals are selectively provided for the anti-fuse memory arrays so as to drive the anti-fuse memory arrays; the introduction of a plurality of anti-fuse memory arrays increases the number of anti-fuse memory cells, only needs to be realized by controlling the transmission of the sub-clock signals required by the anti-fuse memory arrays, and is suitable for DRAM chips with increasing integration level.
Referring to fig. 1 in conjunction with fig. 2, a first control module 100 includes: the cascade signal selection units are cascaded, and each stage of signal selection unit receives a selection signal respectively.
Specifically, each level of signal selection unit is used for transmitting a signal received by a clock signal input end to a clock signal input end of a next level of signal selection unit through a first output end according to a selection signal, a second output end of each level of signal selection unit is used for outputting a sub-clock signal according to the selection signal, a clock signal input end of the first level of signal selection unit receives an initial clock signal, and a first output end and a second output end of the last level of signal selection unit are used for outputting the sub-clock signal.
It should be noted that the above mentioned "cascade connection" means that a plurality of signal selection units are respectively used as a first-stage signal selection unit, a second-stage signal selection unit … … N-1-stage signal selection unit and an nth-stage signal selection unit, and the first-stage signal selection unit, the second-stage signal selection unit … … N-1-stage signal selection unit and the nth-stage signal selection unit are sequentially connected.
In an example, referring to fig. 2, a clock signal input terminal of the first-stage signal selection unit 201 is configured to receive an initial clock signal, and a first output terminal is connected to a clock signal input terminal of the second-stage signal selection unit 202; the first-stage signal selection unit 201 is configured to select, based on a first selection signal, to output a first sub-clock signal, which is a clock signal of an antifuse memory array for driving the corresponding antifuse memory array, or to transfer the clock signal to the second-stage signal selection unit 202; a first output end of the second-stage signal selection unit 202 is connected with a clock signal input end of the third-stage signal selection unit 203; the second-stage signal selection unit 202 is configured to select to output a second sub-clock signal based on a second selection signal, or to transfer the clock signal to the third-stage signal selection unit 203, the second sub-clock signal being a clock signal of an antifuse memory array for driving the corresponding antifuse memory array; a first output end of the third-stage signal selection unit 203 is connected with a signal input end of a fourth-stage signal selection unit (not shown); a first output terminal of the N-1 th-stage signal selection unit (not shown) is connected to a signal input terminal of the nth-stage signal selection unit 20N; the nth stage signal selection unit 20N is configured to selectively output the nth sub-clock signal or the (N + 1) th sub-clock signal based on the nth selection signal, where the nth sub-clock signal and the (N + 1) th sub-clock signal are respectively used as clock signals of an antifuse memory array for driving the corresponding antifuse memory array.
In summary, the first control module 100 generates N +1 sub-clock signals (the first sub-clock signal to the N +1 th sub-clock signal) according to the N selection signals (the first selection signal to the nth selection signal), each sub-clock signal is used to drive a corresponding antifuse memory array, the N +1 sub-clock signals are respectively used to control whether the N +1 antifuse memory array is programmed or not, and only one of the N +1 sub-clock signals is transmitted to the corresponding antifuse memory array at the same time, so as to implement programming control over a plurality of antifuse arrays, and is applicable to DRAM chips with increasingly increased integration levels only by controlling transmission of the sub-clock signals required by the antifuse memory array.
Based on the above discussion, in some embodiments, the number of antifuse memory arrays is one less than the number of signal selection units, so that each generated sub-clock signal can selectively drive the corresponding antifuse memory array.
Specifically, in some embodiments, the number of antifuse memory arrays is 3, and the number of signal selection units is 2.
For the selection signals of the signal selection unit, specifically referring to fig. 3, each of the selection signals includes a first sub-selection signal and a second sub-selection signal that are opposite-phase signals to each other, and the signal selection unit includes: a first selection unit 301, one input end of which is used for receiving the first sub-selection signal, the other input end of which is a clock signal input end of the signal selection unit, and the output end of which is a first output end of the signal selection unit; a second selection unit 302, having an input end for receiving the second sub-selection signal, another input end being a clock signal input end of the signal selection unit, and an output end being a second output end of the signal selection unit.
The first sub-selection signal and the second sub-selection signal are mutually inverse signals, and only one of the first selection subunit and the second selection subunit in the same signal selection unit is gated at the same moment, so that the selection and the transmission of the clock signal are realized.
In some embodiments, referring to fig. 4, the first selection sub-unit includes a first nand gate 311, one input terminal of the first nand gate 311 receives the first sub-selection signal, another input terminal of the first nand gate 311 serves as a clock signal input terminal of the signal selection unit, and an output terminal of the first nand gate 311 serves as a first output terminal of the signal selection unit; the second selection unit comprises a second nand gate 312, one input end of the second nand gate 312 receives the second sub-selection signal, the other input end of the second nand gate 312 serves as a book signal input end of the signal selection unit, and an output end of the second nand gate 312 serves as a second output end of the signal selection unit.
Specifically, when the first sub-selection signal of one of the signal selection units is at a high level, the second sub-selection signal is at a low level, at this time, the output end of the first nand gate of the signal selection unit outputs a word clock signal to the corresponding antifuse memory array, the output end of the second nand gate outputs only one high-level signal, the first sub-selection signals of the other signal selection units are at a low level, and the second sub-selection signal is at a high level, that is, the first selection sub-selection unit receiving the first sub-selection signal at the low level does not output a clock signal, and the second nand gate receiving the second sub-selection signal at the high level outputs the received clock signal or outputs a low-level signal to the next stage, so that the clock signal output by the second selection sub-unit of the previous stage can be transmitted to the next-stage signal selection unit, thereby selecting the sub-clock signals.
Based on the above principle, in other embodiments, the first selection unit and the second selection unit may also be implemented based on an and gate, and specifically, the first selection subunit includes a first and gate, one input terminal of the first and gate receives the first sub-selection signal, the other input terminal of the first and gate serves as a clock signal input terminal of the signal selection unit, and an output terminal of the first and gate serves as a first output terminal of the signal selection unit; the second selection unit comprises a second AND gate, one input end of the second AND gate receives the second sub-selection signal, the other input end of the second AND gate is used as a book signal input end of the signal selection unit, and the output end of the second AND gate is used as a second output end of the signal selection unit.
In some embodiments, referring to fig. 5, in the antifuse array architecture, each antifuse memory array further includes a second control unit configured to generate an internal enable signal based on a program enable signal for enabling programming of the antifuse memory array, a location signal for locating a location of a target antifuse memory cell in the antifuse memory array, and a sub-clock signal, the internal enable signal for enabling the antifuse memory array to start programming.
In some embodiments, the internal enable signal comprises: a repair package enable signal for enabling the repair package to provide a user self-programmed function; an external command enable signal for enabling an external pin to input a command signal to the antifuse memory array; a logic circuit enable signal for enabling the internal logic circuit of the antifuse memory array; a location check enable signal for enabling the location matching check circuit.
The embodiment selectively provides the sub-clock signal to the anti-fuse memory array by increasing the number of the anti-fuse memory arrays so as to drive the anti-fuse memory array; a plurality of antifuse memory arrays are introduced, the number of antifuse memory cells is increased, the antifuse memory cells are realized only by controlling transmission of sub clock signals required by the antifuse memory arrays, and the antifuse memory array is suitable for DRAM chips with the increasing integration level.
In practical applications, one logical unit may be one physical unit, may be a part of one physical unit, and may also be implemented by a combination of multiple physical units. In addition, in order to highlight the innovative part of the present disclosure, a unit that is not so closely related to solving the technical problem proposed by the present disclosure is not introduced in the present embodiment, but this does not indicate that there is no other unit in the present embodiment.
It should be noted that the features disclosed in the anti-fuse array architecture provided in the above embodiments can be combined arbitrarily without conflict, and a new anti-fuse array architecture embodiment can be obtained.
In another embodiment of the present disclosure, a memory is provided, in which an antifuse memory array is arranged based on the antifuse array architecture provided in the above embodiments, a new antifuse array architecture is designed to introduce more antifuse memory arrays and antifuse memory cells, and the modification of a logic circuit in an antifuse circuit is small, so that the memory is suitable for DRAM chips with increasingly increased integration.
Fig. 6 is a schematic structural diagram of an antifuse memory array in the memory provided in this embodiment, and the memory provided in this embodiment is described in detail below with reference to the accompanying drawings, specifically as follows:
the memory may be a memory unit or device based on a semiconductor device or component. For example, the memory device may be a volatile memory such as a dynamic random access memory DRAM, a synchronous dynamic random access memory SDRAM, a double data rate synchronous dynamic random access memory DDR SDRAM, a low power double data rate synchronous dynamic random access memory LPDDR SDRAM, a graphics double data rate synchronous dynamic random access memory GDDR SDRAM, a double data rate type double synchronous dynamic random access memory DDR2SDRAM, a double data rate type triple synchronous dynamic random access memory DDR3SDRAM, a double data rate fourth generation synchronous dynamic random access memory DDR4SDRAM, a thyristor random access memory TRAM, or the like; or may be a non-volatile memory such as a phase change random access memory PRAM, a magnetic random access memory MRAM, a resistive random access memory RRAM, or the like.
It should be noted that, in the present embodiment, the number of the antifuse memory arrays is 3, and the number of the signal selection units is 2, which are taken as an example for specific description, and the present embodiment is not limited thereto, and in other embodiments, the number of the antifuse memory arrays may be expanded to N +1, and the number of the signal selection units may be expanded to N.
Specifically, the memory includes a first pin for receiving a first sub-selection signal and a second pin for receiving a second sub-selection signal.
The first pin and the second pin may be a BA0 pin and a BA0_ N pin, or an a17 pin and an a17 pin may be connected to an inverter.
Specifically, referring to fig. 6, the memory receives an initial clock signal based on the ACTB pin and the CSB pin, and the initial clock signal is transmitted to the first-stage signal selection unit; the first-stage signal selection unit is used for receiving an initial clock signal, receiving a first sub-selection signal based on a BA0 pin and receiving a second sub-selection signal based on a BA0_ N pin, outputting an intermediate clock signal CLK _ LC based on the first sub-selection signal or outputting a first sub-clock signal CLK _ R based on the second sub-selection signal, wherein the first sub-clock signal CLK _ R is a clock signal for turning on the first antifuse memory array; the second-stage signal selection unit is used for receiving the intermediate clock signal CLK _ LC, receiving a first sub-selection signal based on the A17 pin, receiving a second sub-selection signal based on the A17 pin, outputting a second sub-clock signal CLK _ L based on the first sub-selection signal, and outputting a third sub-clock signal CLK _ C based on the second sub-selection signal, wherein the second sub-clock signal CLK _ L is a clock signal for turning on the second antifuse memory array, and the third sub-clock signal CLK _ C is a clock signal for turning on the third antifuse memory array.
Because the first sub-clock signal CLK _ R, the second sub-clock signal CLK _ L and the third sub-clock signal CLK _ C are respectively used for controlling whether the first anti-fuse memory array, the second anti-fuse memory array and the third anti-fuse memory array are programmed or not, only one of the three signals is effective at the same time, namely only one clock signal is transmitted to the corresponding anti-fuse memory array at the same time, thereby realizing the programming of a plurality of anti-fuse arrays, realizing the introduction of a large number of anti-fuse memory units, realizing the programming only by controlling the transmission of the sub-clock signals required by the anti-fuse memory arrays, and being suitable for DRAM chips with the increasing integration level.
In some embodiments, each antifuse memory array further comprises a second control unit configured to generate an internal enable signal based on a program enable signal for enabling programming of the antifuse memory array, a location signal for locating a location of a target antifuse memory cell in the antifuse memory array, and a sub-clock signal for enabling the antifuse memory array to start programming.
Specifically, the antifuse memory array generates signal internal enable signals that control various logic within the antifuse circuit based on corresponding sub-clock signals in combination with the address signal and the program enable signal.
In some embodiments, the internal enable signal comprises: a repair package enable signal for enabling the repair package to mention a function programmed by a user; an external command enable signal for enabling an external pin to input a command signal to the antifuse memory array; a logic circuit enable signal for enabling the internal logic circuit of the antifuse memory array; a location check enable signal for enabling the location matching check circuit.
The embodiment selectively provides the sub-clock signal to the anti-fuse memory array by increasing the number of the anti-fuse memory arrays so as to drive the anti-fuse memory arrays; a plurality of antifuse memory arrays are introduced, the number of antifuse memory cells is increased, the antifuse memory cells are realized only by controlling transmission of sub clock signals required by the antifuse memory arrays, and the antifuse memory array is suitable for DRAM chips with the increasing integration level.
It should be noted that the features disclosed in the memories provided in the above embodiments can be combined arbitrarily without conflict, and a new memory embodiment can be obtained.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific embodiments for carrying out the present disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure in practice.

Claims (10)

1. An antifuse array architecture, comprising:
a plurality of antifuse memory arrays, wherein different antifuse memory arrays are driven based on different clock signals;
the first control module is coupled with a plurality of the antifuse memory arrays and is configured to generate a sub-clock signal based on an initial clock signal and a plurality of selection signals, and the sub-clock signal is used for driving a corresponding one of the antifuse memory arrays.
2. The antifuse array architecture of claim 1, wherein the first control module comprises: a plurality of cascaded signal selection units, each of the signal selection units receiving one of the selection signals;
the signal selection unit of each stage is used for transmitting a signal received by a clock signal input end to a clock signal input end of the signal selection unit of the next stage through a first output end according to the selection signal, a second output end of the signal selection unit of each stage is used for outputting the sub-clock signal according to the selection signal, the clock signal input end of the signal selection unit of the first stage receives the initial clock signal, and the first output end and the second output end of the signal selection unit of the last stage are used for outputting the sub-clock signal.
3. The antifuse array architecture of claim 2, wherein each of the select signals comprises a first sub-select signal and a second sub-select signal that are inverted with respect to each other;
the signal selection unit includes:
a first selection subunit, one input end of which is used for receiving the first sub-selection signal, the other input end of which is used as a clock signal input end of the signal selection unit, and the output end of which is used as a first output end of the signal selection unit;
and one input end of the second selection subunit is used for receiving the second sub-selection signal, the other input end of the second selection subunit is used as a clock signal input end of the signal selection unit, and the output end of the second selection subunit is used as a second output end of the signal selection unit.
4. The antifuse array architecture of claim 3, comprising:
the first selection subunit comprises a first nand gate, one input end of the first nand gate receives the first sub-selection signal, the other input end of the first nand gate is used as a clock signal input end of the signal selection unit, and an output end of the first nand gate is used as a first output end of the signal selection unit;
the second selection subunit includes a second nand gate, one input end of the second nand gate receives the second sub-selection signal, the other input end of the second nand gate is used as the clock signal input end of the signal selection unit, and the output end of the second nand gate is used as the second output end of the signal selection unit.
5. The antifuse array architecture of any one of claims 1 to 4, wherein each of the antifuse memory arrays comprises a second control unit configured to generate an internal enable signal based on a program enable signal, a positioning signal, and the sub-clock signal;
the programming enabling signal is used for starting programming of the antifuse memory array, the positioning signal is used for positioning the position of a target antifuse memory cell in the antifuse memory array, and the internal enabling signal is used for enabling the antifuse memory array to start programming.
6. The antifuse array architecture of claim 5, wherein the internal enable signal comprises:
a repair pack enabling signal for enabling the repair pack to provide a function programmed by a user;
an external command enable signal for enabling an external pin to input a command signal to the antifuse memory array;
a logic circuit enable signal for enabling the internal logic circuit of the antifuse memory array;
a location check enable signal for enabling the location matching check circuit.
7. The antifuse array architecture of claim 2, wherein the number of antifuse memory arrays is one less than the number of signal selection units.
8. The antifuse array architecture of claim 7, comprising: the number of the antifuse memory arrays is 3, and the number of the signal selection units is 2.
9. A memory wherein an antifuse memory array is arranged based on the antifuse array architecture of any one of claims 1 to 8.
10. The memory of claim 9, wherein the memory comprises a first pin and a second pin, the first pin configured to receive a first sub-select signal, the second pin configured to receive a second sub-select signal.
CN202210664729.3A 2022-06-13 2022-06-13 Anti-fuse array architecture and memory Pending CN115171764A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210664729.3A CN115171764A (en) 2022-06-13 2022-06-13 Anti-fuse array architecture and memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210664729.3A CN115171764A (en) 2022-06-13 2022-06-13 Anti-fuse array architecture and memory

Publications (1)

Publication Number Publication Date
CN115171764A true CN115171764A (en) 2022-10-11

Family

ID=83484698

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210664729.3A Pending CN115171764A (en) 2022-06-13 2022-06-13 Anti-fuse array architecture and memory

Country Status (1)

Country Link
CN (1) CN115171764A (en)

Similar Documents

Publication Publication Date Title
US5537354A (en) Semiconductor memory device and method of forming the same
US6876228B2 (en) Field programmable gate array
US8284602B2 (en) Pipe latch circuit of multi-bit prefetch-type semiconductor memory device with improved structure
JP3280214B2 (en) Predictive read method for serial access memory and memory therefor
US11127440B2 (en) Pseudo static random access memory and method for operating pseudo static random access memory
EP0051920B1 (en) Memory arrangement with means for interfacing a central processing unit
KR930018594A (en) Semiconductor memory
US11037609B2 (en) Semiconductor devices
US8437209B2 (en) Integrated circuit
KR102295975B1 (en) SRAM Architectures for Reduced Leakage
US7616519B2 (en) Semiconductor integrated circuit device
US7710804B2 (en) Auto precharge circuit sharing a write auto precharge signal generating unit
US20150262635A1 (en) Latch circuit and semiconductor device including the same
US6489832B1 (en) Chip information output circuit
US10726889B2 (en) Semiconductor devices
US6452847B2 (en) Testable nonvolatile semiconductor device
US20090109767A1 (en) Semiconductor memory device having biderectional buffer
US10964364B2 (en) Semiconductor device and semiconductor system including the same
JPH0421956B2 (en)
CN115171764A (en) Anti-fuse array architecture and memory
CN115223609A (en) Memory clock driver, memory device and operating method thereof
US7978547B2 (en) Data I/O control signal generating circuit in a semiconductor memory apparatus
US20150380104A1 (en) Latch circuit and semiconductor device including the same
US7161214B2 (en) Reduced gate delay multiplexed interface and output buffer circuit for integrated circuit devices incorporating random access memory arrays
WO2023231166A1 (en) Fuse circuit and fuse array signal transmission method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination