CN115134311B

CN115134311B - RapidIO endpoint controller and endpoint equipment

Info

Publication number: CN115134311B
Application number: CN202211061443.2A
Authority: CN
Inventors: 朱珂; 王盼; 姜海斌; 徐庆阳; 钟丹; 吴佳骏; 李丹丹; 陈德沅
Original assignee: Jingxin Microelectronics Technology Tianjin Co Ltd
Current assignee: Jingxin Microelectronics Technology Tianjin Co Ltd
Priority date: 2022-09-01
Filing date: 2022-09-01
Publication date: 2022-11-15
Anticipated expiration: 2042-09-01
Also published as: CN115134311A

Abstract

The invention provides an RapidIO end point controller and end point equipment, which can realize the message forwarding between a bus conversion bridge and an RapidIO protocol controller by adding an exchange forwarding module, a routing module and a queue module between the RapidIO protocol controller and the bus conversion bridge, namely realize the data intercommunication between the end point equipment by adopting the end point controller integrated with the exchange forwarding module, the routing module and the queue module under the condition of not introducing an exchange chip into the end point equipment. The economic cost and the management cost can be reduced and the product size of the end point equipment can be reduced because a switching chip is not required to be introduced.

Description

RapidIO endpoint controller and endpoint equipment

Technical Field

The disclosure relates to the technical field of data path testing, in particular to a RapidIO endpoint controller and endpoint equipment.

Background

The RapidIO bus is an interconnection system architecture with high performance, low pin count and based on data packet exchange, is mainly applied to interconnection in an embedded system, supports interconnection communication between a chip and between boards, and can be used as a back board (Backplane) of embedded equipment for connection.

RapidIO endpoint devices generally refer to terminal devices at the edge of a RapidIO network, and may be interconnected with other endpoint devices in the RapidIO network, as shown in fig. 1 and fig. 2. In fig. 1, the RapidIO switch network is generally composed of RapidIO switch chips. In the simplified RapidIO network, as shown in fig. 2, the endpoint devices may also be directly interconnected with the endpoint devices, that is, a switching chip is not disposed between the endpoint devices, but a direct interconnection mode is adopted.

As can be seen from fig. 1 and fig. 2, the RapidIO switch device required by the switching network is omitted in fig. 1, but the endpoint devices cannot communicate with each other, such as the lower CPU endpoint device, DSP endpoint device and NPU endpoint device in fig. 2. If the interconnection and intercommunication among the end point devices are to be realized, a RapidIO switch chip is added to realize that the end point devices are all connected to the switch chip and are intercommunicated through the switch chip, namely as shown in fig. 1. However, the solution shown in fig. 1 requires the addition of RapidIO switch or chip, increases the economic cost of chip purchase and the management cost caused by integrating the switch chip into the endpoint device, and also increases the volume of the endpoint device caused by the addition of the switch chip.

Disclosure of Invention

The present disclosure provides a RapidIO endpoint controller and an endpoint device.

In a first aspect, the present disclosure provides a RapidIO endpoint controller comprising: the system comprises a bus conversion bridge, a first routing module, a first queue module, an exchange forwarding module and at least one RapidIO protocol control module, wherein the bus conversion bridge, the first routing module, the first queue module, the exchange forwarding module and the at least one RapidIO protocol control module are in communication connection with the exchange forwarding module respectively, the RapidIO protocol control module comprises a second queue module, a second routing module and a RapidIO protocol controller, the second queue module is in communication connection with the exchange forwarding module respectively, and the RapidIO protocol control module comprises: the bus conversion bridge is configured to realize conversion between a RapidIO protocol data packet format and a bus protocol data packet format; the exchange forwarding module, the first routing module, the first queue module, each second queue module and the corresponding second routing module are configured to implement message forwarding between the bus conversion bridge and each RapidIO protocol controller; and each RapidIO protocol controller is configured to realize a physical layer function, a transmission layer function and a part of logic layer function in RapidIO protocol specification, and two ends of each RapidIO protocol controller are respectively in communication connection with a corresponding second routing module and an external RapidIO network.

In some optional embodiments, the bus translation bridge is an AXI bus translation bridge.

In some alternative embodiments, wherein: each second routing module is configured to analyze a destination device identifier in a message sent by a corresponding RapidIO protocol controller, and obtain a corresponding destination switching port identifier according to the destination device identifier query; each second queue module is configured to store the messages to be forwarded received from the corresponding second routing module in a classified manner according to the corresponding destination port identifier; the switching and forwarding module is configured to forward the to-be-forwarded messages stored in the first queue module and each of the second queue modules and to be forwarded to each port to the corresponding port.

<xnotran> , Crossbar . </xnotran>

In some optional embodiments, the first routing module is configured to parse a destination device identifier in a packet from the bus translation bridge, and obtain a corresponding destination switch port identifier according to a query of the destination device identifier; the first queue module is configured to store the messages to be forwarded received from the bus conversion bridge in a classified manner according to corresponding destination port identifiers; the switching and forwarding module is configured to forward the to-be-forwarded messages stored in the first queue module and each of the second queue modules and to be forwarded to each port to the corresponding port.

In some optional embodiments, the RapidIO endpoint controller communicates with an external RapidIO network using a SERDES serializer/deserializer.

In a second aspect, the present disclosure provides a RapidIO endpoint device comprising: a processing unit, a network on chip and a RapidIO endpoint controller as described in any implementation manner of the first aspect, wherein: the processing unit is in communication connection with the network on chip, and the network on chip is in communication connection with the RapidIO endpoint controller; and the processing unit accesses an external RapidIO network through the network on chip and the RapidIO endpoint controller.

In some optional embodiments, the on-chip network is an AXI bus network.

In some optional embodiments, the processing unit comprises at least one of: digital signal processing unit, central processing unit, network processing unit and artificial intelligence accelerating unit.

In some optional embodiments, said RapidIO endpoint devices comprise at least one RapidIO interface, each said RapidIO interface being communicatively connected directly to other said RapidIO endpoint devices in an external RapidIO network via SERDES.

By adding the exchange forwarding module, the routing module and the queue module between the RapidIO protocol controller of the endpoint controller and the bus conversion bridge, the RapidIO endpoint controller and the endpoint equipment can realize message forwarding between the bus conversion bridge and the RapidIO protocol controller, namely realize data intercommunication between the endpoint equipment by adopting the endpoint controller integrated with the exchange forwarding module, the routing module and the queue module under the condition that an exchange chip is not introduced into the endpoint equipment. The economic cost and the management cost can be reduced and the product size of the end point equipment can be reduced because a switching chip is not required to be introduced.

Drawings

Other features, objects and advantages of the disclosure will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

fig. 1 and fig. 2 are schematic structural diagrams of an embodiment of a RapidIO endpoint device in the prior art, respectively;

FIG. 3 is a schematic diagram of one embodiment of a RapidIO endpoint controller according to the present disclosure;

fig. 4 is a schematic structural diagram of one embodiment of a RapidIO endpoint device according to the present disclosure.

Detailed Description

The present disclosure is described in further detail below with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the related invention are shown in the drawings.

It should be noted that, in the present disclosure, the embodiments and features of the embodiments may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Referring to fig. 3 and 4, fig. 3 is a schematic structural diagram of an embodiment 30 of a RapidIO endpoint controller according to the present disclosure, and fig. 4 is a schematic structural diagram of an embodiment 1 of a RapidIO endpoint device according to the present disclosure.

The RapidIO endpoint device 1 as shown in fig. 4 may include: a processing unit 10, a network on chip 20 and a RapidIO endpoint controller 30. Wherein:

the processing unit 10 is communicatively coupled to a network-on-chip 20, and the network-on-chip 20 is communicatively coupled to a RapidIO endpoint controller 30. The processing unit 10 accesses the external RapidIO network via the network on chip 20 and the RapidIO endpoint controller 30. For example, access endpoint device 2 in an external RapidIO network.

Here, the processing unit 10 may be a unit that implements various arithmetic processing. Optionally, the processing unit 10 may comprise at least one of: a Digital Signal Processing (DSP) Unit, a Central Processing Unit (CPU), a Network Processing Unit (NPU), and an Artificial Intelligence (AI) acceleration Unit. In practice, the corresponding arithmetic processing unit can be selected according to the design requirement of the product. When the processing unit is a CPU, the corresponding endpoint form is a CPU endpoint; when the processing unit is a DSP unit, the corresponding endpoint form is a DSP endpoint; when the processing unit is an NPU, the corresponding endpoint is an NPU endpoint. It is to be understood that one or at least two processing units may be included in a certain endpoint.

The network on chip 20 may be various bus networks, and may specifically select a corresponding bus network according to a bus protocol adopted at a time. Alternatively, the network on chip 20 may be an AXI (Advanced eXtensible Interface) bus network.

The RapidIO endpoint controller 30 shown in fig. 3 and 4 specifically includes:

the bus conversion bridge 31, the first routing module 32, the first queue module 33, the switch forwarding module 34, and at least one RapidIO

protocol control module

351, 352, and 353 (3 are shown in fig. 3, which are only schematic representations and do not represent a limitation of the specific number in the present disclosure) are respectively connected to the switch forwarding module 34 in communication. The RapidIO

protocol control modules

351, 352 and 353 respectively comprise

second queue modules

3511, 3521 and 3531 which are sequentially connected in a communication mode, the

second routing modules

3512, 3522 and 3532 and the RapidIO

protocol controllers

3513, 3523 and 3533, and the

second queue modules

3511, 3521 and 3531 are respectively connected with the exchange forwarding module 34 in a communication mode.

The bus translation bridge 31 is configured to implement translation between the RapidIO protocol packet format and the bus protocol packet format so that the processing unit 10 within the endpoint device 1 can access an endpoint device in the RapidIO network (e.g., the endpoint device 2 shown in fig. 4) like accessing memory.

The switch forwarding module 34, the first routing module 32, the first queue module 33, and each second queue module (e.g., the

second queue modules

3511, 3521, 3531 shown in fig. 3 and 4) and the corresponding second routing module (e.g., the

second routing modules

3512, 3522, 3532 shown in fig. 3 and 4) are configured to implement message forwarding between the bus translation bridge 31 and each RapidIO protocol controller (e.g., the RapidIO

protocol controllers

3513, 3523, 3533 shown in fig. 3 and 4).

Each RapidIO protocol controller (

RapidIO protocol controllers

3513, 3523, 3533 shown in fig. 3 and 4) is configured to implement a physical layer function, a transport layer function and a part of a logic layer function in the RapidIO protocol specification, and both ends of each RapidIO protocol controller (

RapidIO protocol controllers

3513, 3523, 3533 shown in fig. 3 and 4) are respectively in communication connection with a corresponding second routing module (

second routing modules

3512, 3522, 3532 shown in fig. 3 and 4) and an external RapidIO network.

Bus translation bridge 31 may be any of a variety of bus translation bridges, and optionally bus translation bridge 31 may be an AXI bus translation bridge.

Each second routing module (e.g.,

second routing module

3512, 3522, 3532 shown in fig. 3 and 4) may be configured to parse a destination device identifier (e.g., destID field) in a packet sent by a corresponding RapidIO protocol controller (e.g.,

rapidIO protocol controller

3513, 3523, 3533 shown in fig. 3 and 4), and query for a corresponding destination switch port identifier according to the destination device identifier. In practice, the second routing module (e.g., the

second routing module

3512, 3522, 3532 shown in fig. 3 and 4) may store a routing table, and may obtain the destination switch port identifier corresponding to the destination device identifier by querying the routing table. How to implement the routing table function is not the inventive focus of the present disclosure, and the present disclosure does not specifically limit this.

The switch port identifier output by the first routing module and each second routing module is used to indicate the switch port of the switch forwarding module 34. For example, in fig. 4, the switch port connected to the CPU endpoint device 21 in the external RapidIO network is 341, the switch port connected to the DSP endpoint device 22 in the external RapidIO network is 342, the switch port connected to the NPU endpoint device in the external RapidIO network is 343, and the port connected to the bus transfer bridge in the RapidIO endpoint device 1 is 344.

Each second queue module (e.g.,

second queue modules

3511, 3521, 3531 shown in fig. 3 and 4) is configured to store the packets to be forwarded, which are received from the corresponding second routing module (e.g.,

second routing modules

3512, 3522, 3532 shown in fig. 3 and 4), in a sorted manner according to the destination port identifier.

The first routing module 32 is configured to parse the destination device identifier in the message from the bus translation bridge 31, and obtain a corresponding destination switch port identifier according to a query of the destination device identifier obtained through parsing. Accordingly, the first queue module 33 is configured to store the message to be forwarded received from the bus translation bridge 31 in a classified manner according to the corresponding destination port identifier.

And the switch forwarding module 34 may be configured to forward the packets to be forwarded to each port stored in the first queue module 33 and each second queue module (e.g., the

second queue modules

3511, 3521, 3531 shown in fig. 3 and 4) to a corresponding port of the switch forwarding module 34.

The First queue module 33 and each second queue module may adopt various implementations, for example, FIFO (First Input First Output) or a linked list may be adopted. The implementation manner of the queue module is not the focus of the disclosure, and the disclosure is not particularly limited.

The switch forwarding module 34 may employ various switch fabrics. Alternatively, the switching fabric of the switching forwarding module 34 may be a Crossbar (Crossbar) fabric.

Alternatively, the RapidIO endpoint controller 30 may employ SERDES (SERializer/DESerializer) communication with an external RapidIO network.

Optionally, the RapidIO endpoint device 1 may include at least one RapidIO interface, each RapidIO interface being directly communicatively connected to other RapidIO endpoint devices in the external RapidIO network via SERDES. Specifically, as shown in fig. 4, the RapidIO endpoint device 1 includes 3

RapidIO protocol controllers

3513, 3523 and 3533, and the

RapidIO protocol controllers

3513, 3523 and 3533 are respectively connected with the CPU endpoint 21, the DSP endpoint 22 and the NPU endpoint 23 in the external RapidIO network. Inside the RapidIO endpoint device 1, 3

RapidIO controllers

3513, 3523 and 3533 and the bus switch bridge 31 are connected to the

switch ports

341, 342, 343 and 344 of the forwarding switch module 34 through a routing module and a queue module, respectively. Through the forwarding switching module 34, arbitrary message forwarding can be performed between the 3 RapidIO protocol controllers and the bus conversion bridge. Corresponding to fig. 4, the CPU endpoint 21, the DSP endpoint 22 and the NPU endpoint 23 may be arbitrarily accessed, and may also be arbitrarily accessed with the CPU/DSP/AI/NPU processing unit 10 in the RapidIO endpoint device 1. In the actual application process, a specified number of RapidIO protocol controllers can be set, and the number of switching ports of the forwarding switching module 34 is set correspondingly.

Therefore, rapidIO end point equipment in the RapidIO network does not need to be provided with an exchange chip independently, the economic cost, the management cost and the product size increase brought by the exchange chip are reduced, and the interaction between the internal processing unit of the end point equipment and each end point in an external network and the interaction between each end point in the external network can be realized.

To clarify the data forwarding process, the following examples are given:

assuming that a CPU endpoint 21 externally connected to the RapidIO protocol controller 3513 sends a message to a DSP endpoint 22 externally connected to the RapidIO protocol controller 3523, the corresponding data forwarding process is as follows:

firstly, a packet sent by a CPU endpoint 21 arrives at a RapidIO protocol controller 3513 and is parsed into a RapidIO packet Package1;

secondly, the packet Package1 enters the second routing module 3512, and the second routing module 3512 queries the routing table by using the destination device identifier destID field in the packet Package1 to obtain the destination port identifier 342;

thirdly, the packet Package1 enters the second queue module 3511 and is stored in a queue corresponding to the destination port identifier 342 in a classified manner;

step four, when the packet Package1 in the queue where the packet Package1 is located is taken out by the switch forwarding module 34, the packet Package1 is forwarded to the port 342 through the switch forwarding module 34;

in the fifth step, the packet Package1 is sent from the port 342 of the switch forwarding module 34 to the DSP endpoint 22 via the RapidIO protocol controller 3523.

Suppose that the processing unit 10 in the RapidIO endpoint device 1 sends a message to the CPU endpoint 21 externally connected to the RapidIO protocol controller 3513, and the corresponding data forwarding process is as follows:

in a first step, the processing unit 10 initiates an access request (e.g., an AXI access request) through the bus translation bridge;

secondly, the bus conversion bridge converts an access request (for example, an AXI access request) into a RapidIO data packet Package2;

thirdly, the packet Package2 enters the first routing module 32, and the first routing module 32 uses the destID field in the packet Package2 to look up the routing table, so as to obtain a destination port identifier 341;

step four, the packet Package2 enters the first queue module 33 and is classified and stored in the queue corresponding to the destination port identifier 341;

step five, when the packet Package2 in the queue where the packet Package2 is located is taken out by the switch forwarding module 34, the packet Package2 is forwarded to the port 341 through the switch forwarding module 34;

sixth, the packet Package2 is sent from the port 341 of the switch forwarding module 34 to the CPU endpoint 21 through the RapidIO protocol controller 3513.

In the forwarding process, the access request (for example, an AXI access request) is converted into a RapidIO packet through the bus translation bridge, usually a table look-up form based on a bus address (for example, an AXI address) is adopted, an output result of the table look-up includes a destID of the RapidIO packet to be translated, and in this way, software can control a destination port identifier of the translated RapidIO packet. The specific implementation of the bus conversion bridge is not important to the present disclosure and will not be described in detail herein.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, functional units in the embodiments of the present disclosure may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a separate product, may also be stored in a computer-readable storage medium.

The foregoing description is only exemplary of the preferred embodiments of the disclosure and is illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the invention in the present disclosure is not limited to the specific combination of the above-mentioned features, but also encompasses other embodiments in which any combination of the above-mentioned features or their equivalents is made without departing from the spirit of the invention. For example, the above features and the technical features disclosed in the present disclosure (but not limited to) having similar functions are replaced with each other to form the technical solution.

Claims

1. A RapidIO endpoint controller comprising: the system comprises a bus conversion bridge, a first routing module, a first queue module, an exchange forwarding module and at least one RapidIO protocol control module, wherein the bus conversion bridge, the first routing module, the first queue module, the exchange forwarding module and the at least one RapidIO protocol control module are sequentially in communication connection, the RapidIO protocol control module is respectively in communication connection with the exchange forwarding module and comprises a second queue module, a second routing module and a RapidIO protocol controller which are sequentially in communication connection, and the second queue modules are respectively in communication connection with the exchange forwarding module, wherein:

the bus conversion bridge is configured to realize conversion between a RapidIO protocol data packet format and a bus protocol data packet format;

the exchange forwarding module, the first routing module, the first queue module, each second queue module and the corresponding second routing module are configured to implement message forwarding between the bus conversion bridge and each RapidIO protocol controller;

and each RapidIO protocol controller is configured to realize a physical layer function, a transmission layer function and a part of logic layer function in RapidIO protocol specification, and two ends of each RapidIO protocol controller are respectively in communication connection with a corresponding second routing module and an external RapidIO network.

2. A RapidIO endpoint controller according to claim 1 wherein the bus translation bridge is an AXI bus translation bridge.

3. The RapidIO endpoint controller of claim 1 wherein:

each second routing module is configured to analyze a destination device identifier in a message sent by a corresponding RapidIO protocol controller, and obtain a corresponding destination exchange port identifier according to the destination device identifier query;

each second queue module is configured to store the messages to be forwarded received from the corresponding second routing module in a classified manner according to the corresponding destination port identifier;

the switching and forwarding module is configured to forward the to-be-forwarded messages stored in the first queue module and each of the second queue modules and to be forwarded to each port to the corresponding port.

4. A RapidIO endpoint controller according to claim 3 wherein the switch fabric of the switch forwarding module is a Crossbar.

5. The RapidIO endpoint controller of claim 1 wherein:

the first routing module is configured to analyze a destination device identifier in a message from the bus conversion bridge and obtain a corresponding destination switching port identifier according to the destination device identifier query;

the first queue module is configured to store the messages to be forwarded received from the bus conversion bridge in a classified manner according to corresponding destination port identifiers;

6. A RapidIO endpoint controller according to claim 1 wherein the RapidIO endpoint controller employs SERDES serializer/deserializer to communicate with an external RapidIO network.

7. A RapidIO endpoint device comprising: a processing unit, a network on chip and a RapidIO endpoint controller as claimed in any one of claims 1 to 6 wherein:

the processing unit is in communication connection with the network on chip, and the network on chip is in communication connection with the RapidIO endpoint controller;

and the processing unit accesses an external RapidIO network through the network on chip and the RapidIO endpoint controller.

8. The RapidIO endpoint device of claim 7 wherein the on-chip network is an AXI bus network.

9. The RapidIO endpoint device of claim 7 wherein the processing unit comprises at least one of: the system comprises a digital signal processing unit, a central processing unit, a network processing unit and an artificial intelligence acceleration unit.

10. The RapidIO endpoint device of claim 7 wherein the RapidIO endpoint device comprises at least one RapidIO interface, each RapidIO interface communicatively connected directly to other RapidIO endpoint devices in an external RapidIO network via SERDES.