CN115086454B - Method, system and storage medium for self-adaptive galvanometer control signal interface - Google Patents
Method, system and storage medium for self-adaptive galvanometer control signal interface Download PDFInfo
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Abstract
The invention discloses a method, a system and a storage medium for a self-adaptive galvanometer control signal interface, wherein the method comprises the following steps: judging whether the clock signal changes or not, performing clock synchronization signal decoding and self-synchronization signal decoding switching through a clock failure mark, and analyzing a signal line code stream into byte data for complete receiving and recording through clock synchronization signal decoding; during the process of analyzing the signal line code stream by self-synchronizing signal decoding, carrying out bit rate transmission identification through signal listening, and completely receiving and recording byte data; and (4) analyzing the byte data to complete software protocol matching. The invention completes the important compatibility function, adaptively switches the decoding mode to decode the code stream data, can quickly identify different galvanometer protocols, realizes the self-adaptation of various galvanometer protocol interfaces on the basis of one set of software and hardware, meets the requirements of collocation and use of various products and reduces the operation cost.
Description
Technical Field
The invention relates to the field of electronic communication, in particular to a method, a system and a storage medium for a self-adaptive galvanometer control signal interface.
Background
Various galvanometer control interfaces exist in the market, and the galvanometer control interfaces have differences in hardware and software protocol data definition. In order to obtain wider product applications, control card manufacturers and galvanometer manufacturers have to design various control interfaces in a compatible manner.
If the compatibility design can not be realized on the basis of completely the same software and hardware, a plurality of mutually independent hardware versions are derived. The multi-version products with similar functions are very unfavorable for market promotion and user use, and the management difficulty of the whole manufacture, inventory and order can be increased.
Disclosure of Invention
In order to overcome the defects that a plurality of mutually independent hardware versions are derived to be very unfavorable for market promotion and user use and the management difficulty of the whole manufacture, inventory and order is increased in the compatible design of the control interface in the background technology, the invention aims to provide a method, a system and a storage medium for a self-adaptive galvanometer control signal interface.
In order to achieve the above object, a first aspect of the present invention provides a method for adaptively controlling a signal interface of a galvanometer, comprising the steps of:
s1, judging whether a clock signal changes according to the count value of a counter, and switching a clock synchronization signal decoding mode and a self-synchronization signal decoding mode through a clock failure mark, wherein the clock synchronization signal decoding analyzes a signal line code stream into byte data to be completely received and recorded; during the process of analyzing the code stream of the signal wire by decoding the self-synchronizing signal, carrying out bit rate transmission identification by signal listening, and completely receiving and recording byte data;
and S2, analyzing the byte data to complete software protocol matching.
In some possible embodiments, the determining whether the clock signal changes according to the count value of the counter, and the switching between the clock synchronization signal decoding mode and the self-synchronization signal decoding mode through the clock failure flag specifically includes: the clock failure mark is equivalent to a gating switch, when the clock signal changes, the counter normally works, the reading of the count value is consistent, the clock failure mark is about to be 0, and the signal line code stream is decoded and analyzed into byte data by the clock synchronization signal; when the clock signal is not changed, the counter stops working, the reading value of the count value is 0, the clock failure mark is about to be 1, and the code stream of the signal line is decoded and analyzed into byte data by the self-synchronizing signal.
In some possible embodiments, the signal listening comprises the steps of:
s11: continuously acquiring signal turnover time data;
s12: sorting the signal turnover time data in the storage time queue;
s13: selecting signal turnover time data in a storage time queue and averaging;
s24: removing illegal signal turnover time data in the storage time queue;
s15: screening and classifying the storage time queue to obtain a time array;
s16: calculating the time array to obtain a clock period, and obtaining the clock period according to the clock period
A bit rate;
s17: S13-S16 are a period of processing, and after the processing is finished, the storage is emptied
And time queue for next cycle.
In some possible embodiments, the continuously acquired signal inversion time data is specifically: the timer continuously monitors the signal jump through the data line and obtains the time interval of two jumps.
In some possible embodiments, the sorting the signal flip time data in the storage time queue specifically includes: and acquiring the time of new signal inversion, comparing the time with the time of the stored signal inversion in the storage time queue, and inserting the time of new signal inversion into a position when traversing to the position, wherein the time of new signal inversion is just greater than the time of signal inversion before the position in the queue and less than the time of signal inversion after the position in the queue.
In some possible embodiments, the averaging of the signal transition time data in the selected storage time queue specifically includes: and executing storage time queue processing in a convention period, and averaging the time data of signal inversion of the middle one third of the storage time queue.
In some possible embodiments, the removing of the illegal signal flip time data in the storage time queue specifically includes: and removing data in the storage time queue, wherein the data is less than one sixth of the time of the average signal inversion, and simultaneously removing data which is more than 2 times of the time of the average signal inversion.
In some possible embodiments, the step of screening and classifying the storage time queue to obtain a time array specifically includes: reading and comparing adjacent signal reversed time data according to the sequence from small to large, screening the queue, and judging that the signal reversed time data read at the current position is different from the next signal reversed time data by less than 20 percent, and the signal reversed time data is the same time array and is a clock period with the same length; if the time data of the next signal overturn is more than 20%, the time data of the next signal overturn is considered to be another time array which is a clock period with different lengths; then, the data of the same time array is screened and stored together to form a new time array.
In some possible embodiments, the calculating the time array to obtain a clock cycle, and obtaining the bit rate according to the clock cycle specifically includes: calculating a clock period: and respectively averaging the time arrays generated by screening to obtain an average value array a (n), and solving an absolute change value p = | a [ n ] -a [ n-1] | from adjacent average values to obtain a new array b (n-1), wherein the minimum value of the new array is the minimum clock period, and the bit rate is a frequency value obtained by dividing 1 second by the minimum clock period.
In some possible embodiments, the completing the software protocol matching by parsing the byte data specifically includes the following steps:
s21: positioning a data frame: searching a data frame mark in code stream data, and determining the position of a galvanometer control instruction, wherein the data frame mark is defined by the content of a galvanometer protocol;
s22: verifying the check domain: checking the content of the code stream data, and judging the legality of the code stream data format;
s23: analyzing the command: and after the code stream data format is determined to be legal, extracting the galvanometer control instruction and data according to the position of the galvanometer control instruction, and completing software protocol matching.
In some possible embodiments, if the verification fails in S22 or the control command extracted in S23 cannot be identified, the operation in S21 needs to be performed again, but the content of the galvanometer protocol is changed during the re-execution of S21.
In a second aspect of the present invention, a system for adaptive galvanometer control signal interfacing is provided, comprising:
a clock monitoring module: judging whether the clock signal changes according to the count value of the counter, and sending the signal line code stream to a clock synchronization signal transceiving module or a self-synchronization signal transceiving module through a clock failure mark:
the signal interception module: the bit rate is obtained by measuring the time interval of signal inversion on a signal line continuously, wherein the signal inversion refers to the process that the level is from low to high and then from high to low, or the level is from high to low and then from low to high;
clock synchronization signal transceiver module: receiving the signal line code stream, and analyzing the signal line code stream into byte data to perform complete receiving and recording; sending the byte data to a mode detection module;
the self-synchronizing signal transceiving module: receiving a signal line code stream, analyzing the signal line code stream into byte data, identifying the bit rate obtained by the signal monitoring module, and completely receiving and recording the byte data; sending the byte data to a mode detection module;
a mode detection module: and receiving byte data sent by the clock synchronization signal transceiving module and the self-synchronization signal transceiving module, and completing software protocol matching by analyzing the byte data.
In a third aspect of the present invention, a computer-readable storage medium is provided, on which a computer program is stored, which, when being executed by a processor, carries out the steps of a method of interfacing an adaptive mirror control signal as described above.
The invention has the beneficial effects that: the clock monitoring module is used for completing important compatibility functions, the clock synchronization signal decoding mode and the self-synchronization signal decoding mode are switched in a self-adaptive mode to decode code stream data, the bit transmission rate is determined through signal listening, and then different galvanometer protocols are rapidly identified when the protocol type is determined.
Drawings
FIG. 1 is a flowchart illustrating the operation of a system for interfacing a signal for adaptive galvanometer control according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating the steps of "signal listening" in a method for controlling a signal interface of an adaptive galvanometer according to an embodiment of the present invention;
fig. 3 is a flowchart of the step of "software protocol matching" in the method for adaptive galvanometer control signal interface according to the embodiment of the present invention.
Detailed Description
The following detailed description of the preferred embodiments of the present invention, taken in conjunction with the accompanying drawings, will make the advantages and features of the invention easier to understand by those skilled in the art, and thus will clearly and clearly define the scope of the invention.
The galvanometer protocol is transmitted by means of a data line, and although formats of different protocols are different, the galvanometer protocol is designed to be transmitted in a serial mode. The clock synchronization signal decoding mode and the self-synchronization signal decoding mode mainly realize that the level change sequence on the serial data line is interpreted as binary data or vice versa. Such a circuit for converting data and physical signals is generally called a physical layer driving circuit (abbreviated as PHY)
In the clock synchronization signal mode, the code stream (i.e., the continuous signal change on the serial data line) is in one-to-one correspondence with the original data bits. The self-synchronizing signal mode requires the code stream to transmit data and clock information at the same time, so that the code stream does not correspond to the original data one by one. Common self-synchronizing signal codes include NRZ, manchester code, differential Manchester code, 4B/5B, 8B/10B and the like.
Referring to fig. 1, the present embodiment provides a system of an adaptive galvanometer control signal interface, including:
hardware layer-clock monitoring module: judging whether the clock signal is present according to the count value of the counter
And if no change exists, the signal line code stream is sent to the clock synchronization signal transceiving module or the self-synchronization signal transceiving module through the clock failure mark.
Hardware layer-signal listening module: the bit rate is obtained by continuously measuring the time interval of signal inversion on the signal line, wherein the signal inversion refers to the process that the level is from low to high and then from high to low, or the level is from high to low and then from low to high.
Hardware layer-clock synchronization signal transceiver module: receiving the signal line code stream, and analyzing the signal line code stream into byte data to perform complete receiving and recording; the byte data is sent to a pattern detection module.
Hardware layer-self-synchronizing signal transceiver module: receiving a signal line code stream, analyzing the signal line code stream into byte data, identifying the bit rate obtained by the signal monitoring module, and completely receiving and recording the byte data; the byte data is sent to a pattern detection module.
Software layer-mode detection module: and receiving byte data sent by the clock synchronization signal transceiving module and the self-synchronization signal transceiving module, and completing software protocol matching by analyzing the byte data.
The working process is as follows: the counter counts the clock signals on the signal line continuously, the clock monitoring module judges whether the clock signals change or not according to the counting value of the counter, and the signal line code stream is sent to the clock synchronization signal transceiving module or the self-synchronization signal transceiving module according to the clock failure mark.
The clock synchronization signal is decoded as follows: the clock synchronization signal receiving and sending module receives the signal line code stream, analyzes the signal line code stream into byte data to be completely received and recorded, sends the byte data to the mode detection module, and the mode detection module receives the byte data sent by the clock synchronization signal receiving and sending module and analyzes the byte data to complete software protocol matching.
The self-synchronizing signal is decoded as follows: the signal monitoring module measures the time interval of signal turnover on a signal line continuously to obtain the bit rate, wherein the signal turnover refers to the process that the level is from low to high and then from high to low, or the level is from high to low and then from low to high, the self-synchronizing signal transceiving module receives the code stream of the signal line, and after the code stream is analyzed into byte data, the bit rate obtained by the signal monitoring module is identified, and then the byte data is completely received and recorded; and the byte data is sent to a mode detection module, the mode detection module receives the byte data sent from the synchronous signal transceiver module, and the software protocol matching is completed by analyzing the byte data.
The invention mainly solves the self-adaptive design of the control signal, so that the clock monitoring module completes the important compatibility function and distinguishes the clock synchronization signal decoding mode and the self-synchronization signal decoding mode.
Digital circuits agree that a change in the voltage of a line represents a bit, e.g., a low voltage represents a 0, a high voltage represents a 1, or vice versa. Thus, the binary data stored by the circuitry may correspond to the level of the line and be transferred to another circuitry via the level of the cable.
Such transmission is classified into parallel transmission and serial transmission. The parallel signals are transmitted using a plurality of data lines, each line representing 1bit. The serial signal is transmitted with 1 line, and the level is changed by a fixed time interval. The galvanometer belongs to a high-speed and high-precision motion control assembly, and therefore a serial data transmission mode is adopted.
However, the laser industry has a plurality of galvanometer protocol formats, the protocols of different companies are different, and the same company has protocol version difference. Such as XY-100 protocol, using a clock synchronization signal format. And SL2-100 uses the self-synchronizing signal format.
The coding methods of the clock synchronization signal and the self-synchronization signal are both used for solving the analysis problem of serial data transmission. The clock signal represents the time interval between the serial data change levels. Referring to fig. 1, the clock synchronization signal requires a dedicated line to transmit a clock signal, and the receiving circuit uses the rising or falling edge of the clock signal as a time reference for data level identification to ensure that the byte data can be correctly received. The self-synchronizing signal is not transmitted with a clock signal, only transmits a data signal, and deduces the interval time of the clock by analyzing the data signal. For example, common serial ports, USB, ethernet and PCIE are all self-synchronizing signal transmission modes.
The invention provides an embodiment, a method for controlling a signal interface by a self-adaptive galvanometer, which comprises the following steps:
the method comprises the following steps that S1, a counter continuously counts clock signals on a signal line, whether the clock signals change or not is judged according to the counting value of the counter, a clock synchronization signal decoding mode and a self-synchronization signal decoding mode are switched through a clock failure mark, the clock failure mark is equivalent to a gating switch, when the clock signals change, the counter normally works, the reading of the counting value is consistent, the clock failure mark is about to be 0, and the code stream of the signal line is decoded and analyzed into byte data by the clock synchronization signal; when the clock signal is not changed, the counter stops working, the reading value of the count value is 0, the clock failure mark is about to be 1, and the code stream of the signal line is decoded and analyzed into byte data by the self-synchronizing signal. The byte data in this embodiment specifically refers to a position control command of the galvanometer, and the position of the galvanometer is usually represented by a number of 16-24 bits, and the data includes format data bits necessary for implementing a protocol in addition to position information.
The clock synchronization signal decoding analyzes the signal line code stream into byte data to be completely received and recorded; during the process of analyzing the signal line code stream by the self-synchronizing signal decoding, carrying out bit rate transmission identification through signal listening, and completely receiving and recording byte data; signal sensing is mainly to measure the time interval of signal inversion, which is the process of level from low to high and then from high to low, or level from high to low and then from low to high. Because 1 clock cycle of the serial signal represents 1bit data, the minimum signal inversion time interval is 1 clock cycle, and the other signal inversion time intervals are integral multiple clock cycles.
Referring to fig. 2, the signal interception includes the following steps:
s11: continuously acquiring signal turnover time data: the timer continuously monitors the signal jump through the data line and obtains the time interval of two jumps. In the general MCU processor, the interruption is completed by the timing of the timer, and the DMA controller is triggered to read the value of the timing register of the timer to the memory storage area.
S12: sequencing the signal turnover time data in the storage time queue, specifically: and acquiring the new signal turning time, comparing the new signal turning time with the time of the stored signal turning in the storage time queue, and inserting the new signal turning time into a position when traversing to the position, wherein the new signal turning time is just larger than the signal turning time before the position in the queue and smaller than the signal turning time after the position in the queue, and finally the record in the storage time queue is monotonically decreased from small to large.
S13: selecting signal turnover time data in a storage time queue to average, specifically: and executing storage time queue processing in a predetermined period, and averaging the time data of signal inversion of the middle one third of the storage time queue. Since the number of consecutive "1" or "0" of the self-synchronizing signal does not exceed 7 (NRZ signal encoding standard), the average value is necessarily greater than 1 but less than 6 clock cycles, and according to the normal distribution or average distribution of probability, the average value is closer to 3.5 clock cycles.
S24: removing illegal signal turnover time data in the storage time queue, specifically: and removing data in the storage time queue, wherein the data is less than the time of one-sixth average signal inversion, and simultaneously removing data more than 2 times the time of average signal inversion.
S15: screening and classifying the storage time queue to obtain a time array, which specifically comprises the following steps: reading and comparing adjacent signal reversed time data according to the sequence from small to large, screening the queue, and judging that the signal reversed time data read at the current position is different from the next signal reversed time data by less than 20 percent, and the signal reversed time data is the same time array and is a clock period with the same length; if the time data of the next signal overturn is more than 20%, the time data of the next signal overturn is considered to be another time array which is a clock period with different lengths; then, the data of the same time array is screened and stored together to form a new time array, and after the screening is completed, the data of the time array is not larger than 6 ideally.
S16: calculating the time array to obtain a clock cycle, and obtaining the bit rate according to the clock cycle, wherein the method specifically comprises the following steps: calculating a clock period: and respectively averaging the time arrays generated by screening to obtain an average value array a (n), and solving an absolute change value p = | a [ n ] -a [ n-1] | from adjacent average values to obtain a new array b (n-1), wherein the minimum value of the new array is the minimum clock period, and the bit rate is a frequency value obtained by dividing 1 second by the minimum clock period.
S17: S13-S16 are a period of processing, and after the processing is finished, the storage is emptied
And time queue for next cycle.
S2, completing software protocol matching by analyzing byte data, and referring to the attached figure 3, specifically comprising the following steps:
s21: positioning a data frame: and searching a data frame mark in code stream data, and determining the position of a galvanometer control instruction, wherein the data frame mark is defined by the content of a galvanometer protocol, and the data frame mark is a specific bit value combination, such as 0xAAA, which is 8 continuous clock pulses.
S22: verifying the check domain: in order to avoid instruction errors caused by signal line interference, the content of code stream data is checked, and the legality of a code stream data format is judged; typical checking methods include parity checking and Cyclic Redundancy Check (CRC), the specific checking mode is defined by a galvanometer protocol, and taking CRC as an example, it is usually agreed that 16 or 32 bits of data in a data frame are CRC check values of a current frame. And sequentially performing CRC calculation on the data frame bytes, wherein the final result is consistent with the CRC value, and the data content is considered to be complete and consistent with the original data of the sending end.
S23: command parsing: and after the code stream data format is determined to be legal, extracting the galvanometer control instruction and data according to the position of the galvanometer control instruction, and completing software protocol matching.
If the check in S22 fails or the control command extracted in S23 cannot be recognized, the operation in S21 needs to be performed again, but during the re-execution of S21, the content of the galvanometer protocol is changed, and the data frame flag is changed to 0x5555 or 0xAA 55.
When the specific protocol format is not determined, all protocol analysis processes need to be tried, specifically to the data frame format, that is, the frame header format, the analysis command and the data content need to be compared, verification of the check field is performed, and the identification result of the protocol can be determined to be correct only by at least completing the verification of a plurality of continuous frames. Therefore, the received character data needs to be backed up, and when one protocol fails to be matched, the other protocol needs to be switched to be matched again. Frame authentication is also based on a data window shift method, rather than the traditional processing of failing or discarding.
The present embodiment further provides a computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, implements the steps of the above-mentioned method for interfacing an adaptive galvanometer control signal.
The above embodiments are merely illustrative of the technical concept and features of the present invention, and the present invention is not limited thereto, and any equivalent changes or modifications made according to the spirit of the present invention should be included in the scope of the present invention.
Claims (12)
1. A method for controlling a signal interface by an adaptive galvanometer is characterized by comprising the following steps:
s1, judging whether a clock signal changes according to the count value of a counter, and switching a clock synchronization signal decoding mode and a self-synchronization signal decoding mode through a clock failure mark, wherein the method specifically comprises the following steps: the clock failure mark is equivalent to a gating switch, when the clock signal changes, the counter normally works, the reading of the count value is consistent, the clock failure mark is about to be 0, and the signal line code stream is decoded and analyzed into byte data by the clock synchronization signal; when the clock signal is not changed, the counter stops working, the reading value of the count value is 0, the clock failure mark is about to be 1, and the code stream of the signal line is decoded and analyzed into byte data by the self-synchronizing signal;
the clock synchronization signal decoding analyzes the signal line code stream into byte data to be completely received and recorded; during the process of analyzing the signal line code stream by the self-synchronizing signal decoding, carrying out bit rate transmission identification through signal listening, and completely receiving and recording byte data;
and S2, analyzing the byte data to complete software protocol matching.
2. The method for interfacing an adaptive galvanometer control signal according to claim 1, wherein said signal listening comprises the steps of:
s11: continuously acquiring signal turning time data;
s12: sorting the signal turnover time data in the storage time queue;
s13: selecting signal turnover time data in a storage time queue and averaging the signal turnover time data;
s14: removing illegal signal turnover time data in the storage time queue;
s15: screening and classifying the storage time queues to obtain time arrays;
s16: calculating the time array to obtain a clock period, and obtaining the clock period according to the clock period
A bit rate;
s17: S13-S16 are a period of processing, and after the processing is finished, the storage is emptied
And time queue for next cycle.
3. The method according to claim 2, wherein the continuously acquiring signal inversion time data specifically comprises: the timer continuously monitors the signal jump through the data line and obtains the time interval of two jumps.
4. The method according to claim 2, wherein the sorting of the signal flip time data in the storage time queue is specifically: and acquiring the time of new signal inversion, comparing the time with the time of the stored signal inversion in the storage time queue, and inserting the time of new signal inversion into a position when traversing to the position, wherein the time of new signal inversion is just greater than the time of signal inversion before the position in the queue and less than the time of signal inversion after the position in the queue.
5. The method according to claim 2, wherein the averaging of the signal inversion time data in the selected storage time queue is specifically: and executing storage time queue processing in a predetermined period, and averaging the time data of signal inversion of the middle one third of the storage time queue.
6. The method according to claim 2, wherein the removing of the illegal signal flip time data in the storage time queue specifically comprises: and removing data in the storage time queue, wherein the data is less than one sixth of the time of the average signal inversion, and simultaneously removing data which is more than 2 times of the time of the average signal inversion.
7. The method for interfacing a self-adaptive galvanometer control signal according to claim 2, wherein the step of screening and classifying the queue of stored time to obtain the time array is specifically as follows: reading and comparing adjacent signal reversed time data according to the sequence from small to large, screening the queue, and judging that the signal reversed time data read at the current position is different from the next signal reversed time data by less than 20 percent, and the signal reversed time data is the same time array and is a clock period with the same length; if the time data of the next signal overturn is more than 20%, the time data of the next signal overturn is considered to be another time array which is a clock period with different lengths; then, the data of the same time array is screened and stored together to form a new time array.
8. The method according to claim 2, wherein the time array is calculated to obtain a clock cycle, and the bit rate obtained from the clock cycle is specifically: calculating a clock period: and respectively averaging the time arrays generated by screening to obtain an average value array a (n), and solving an absolute change value p = | a [ n ] -a [ n-1] | from adjacent average values to obtain a new array b (n-1), wherein the minimum value of the new array is the minimum clock period, and the bit rate is a frequency value obtained by dividing 1 second by the minimum clock period.
9. The method of claim 1, wherein the step of performing software protocol matching by parsing byte data comprises the steps of:
s21: positioning a data frame: searching a data frame mark in code stream data, and determining the position of a galvanometer control instruction, wherein the data frame mark is defined by the content of a galvanometer protocol;
s22: verifying the check domain: checking the content of the code stream data, and judging the legality of the code stream data format;
s23: command parsing: and after the code stream data format is determined to be legal, extracting the galvanometer control instruction and data according to the position of the galvanometer control instruction, and completing software protocol matching.
10. The method as claimed in claim 9, wherein if the calibration fails in S22 or the control command extracted in S23 is not recognized, the operation of S21 is required to be performed again, but the content of the galvanometer protocol is changed during the re-execution of S21.
11. A system for an adaptive galvanometer control signal interface, comprising:
a clock monitoring module: judging whether the clock signal changes according to the count value of the counter, and sending the signal line code stream to a clock synchronization signal transceiver module or a self-synchronization signal transceiver module through a clock failure mark, wherein the method specifically comprises the following steps: the clock failure mark is equivalent to a gating switch, when the clock signal changes, the counter normally works, the reading of the count value is consistent, the clock failure mark is about to be 0, and the signal line code stream is decoded and analyzed into byte data by the clock synchronization signal; when the clock signal is not changed, the counter stops working, the reading value of the count value is 0, the clock failure flag is about to be 1, and the code stream of the signal line is decoded and analyzed into byte data by the self-synchronizing signal;
the signal interception module: measuring the time interval of signal turnover on a signal wire continuously to obtain the bit rate, wherein the signal turnover refers to the process that the level is from low to high and then from high to low, or the level is from high to low and then from low to high;
clock synchronization signal transceiver module: receiving the signal line code stream, and analyzing the signal line code stream into byte data to perform complete receiving and recording; sending the byte data to a mode detection module;
the self-synchronizing signal transceiving module: receiving a signal line code stream, analyzing the signal line code stream into byte data, identifying the bit rate obtained by the signal monitoring module, and completely receiving and recording the byte data; sending the byte data to a mode detection module;
a mode detection module: and receiving byte data sent by the clock synchronization signal transceiving module and the self-synchronization signal transceiving module, and analyzing the byte data to complete software protocol matching.
12. A computer readable storage medium having stored thereon a computer program which, when being executed by a processor, carries out the steps of a method of interfacing an adaptive mirror control signal according to any one of claims 1 to 10.
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