CN115083498A - Memory device, operation method and configuration method thereof and memory system - Google Patents

Abstract

The embodiment of the present disclosure provides a memory device, an operating method, a configuration method and a memory system thereof, wherein the memory device comprises a configuration block; the configuration block comprises a configuration page and an additional page; the operation method comprises the following steps: reading the configuration information in the configuration page and reading the additional page; if the additional page is read to have the correction information, operating the memory device based on the configuration information and the correction information; wherein the correction information is used for correcting error information in the configuration information.

Description

Memory device, operating method and configuration method thereof, and memory system

Technical Field

The disclosed embodiments relate to the field of memory device operation, and relate to, but are not limited to, a memory device, an operating method, a configuration method, and a memory system thereof.

Background

In the process of factory configuration of the memory device, if configuration errors occur, all data in a configuration block need to be read, the whole configuration block needs to be erased, then the data needing to be modified is modified, and other data can be reprogrammed and written without being modified. This process is a complex process involving a large amount of data, both data that needs to be modified and data that does not need to be modified, and is prone to other errors during read-rewrite. And the read data also needs to be stored by the storage block, and if the residual storage space of the NAND is smaller than that of the configuration block, the above process cannot be performed even.

Disclosure of Invention

In view of the above, embodiments of the present disclosure provide a memory device, an operating method, a configuration method and a memory system thereof.

In a first aspect, embodiments of the present disclosure provide a method of operating a memory device, the memory device including a configuration block; the configuration block comprises a configuration page and an additional page; the method comprises the following steps:

reading the configuration information in the configuration page and reading the additional page;

if the additional page is read to have the correction information, operating the memory device based on the configuration information and the correction information; wherein the correction information is used for correcting error information in the configuration information.

In some embodiments, the method further comprises:

loading the configuration information to control circuitry of the memory device after reading the configuration information;

if the correction information is read, loading the correction information to the control circuit;

the step of operating the memory device based on the configuration information and the correction information comprises:

operating the memory device through the control circuit loaded with the configuration information and the correction information.

In some embodiments, the step of loading the configuration information to the control circuitry of the memory device comprises:

storing the configuration information into a plurality of registers of the control circuit; wherein the configuration information stored in at least one of the registers is the error information;

the loading of the correction information to the control circuitry comprises:

storing the correction information into the register storing the error information to update the error information.

In some embodiments, the step of operating the memory device by the control circuit loaded with the configuration information and the correction information comprises:

generating, with the control circuit, a control signal to operate the memory device according to the configuration information and the correction information stored in the register;

operating the memory device by the control signal.

In some embodiments, the method further comprises:

if the correction information is not read in the additional page, operating the memory device based on the configuration information.

In some embodiments, the method further comprises:

loading the configuration information to control circuitry of the memory device after reading the configuration information;

the step of operating the memory device based on the configuration information comprises:

operating, by a control circuit loaded with the configuration information, the memory device.

In some embodiments, the loading the configuration information to the control circuitry of the memory device comprises:

storing the configuration information into a plurality of registers of the control circuit;

the step of operating the memory device by the control circuit loaded with the configuration information comprises:

generating, with the control circuit, a control signal to operate the memory device according to the configuration information stored in the register;

operating the memory device by the control signal.

In some embodiments, the reading the configuration information in the configuration page and the reading the additional page comprises:

and responding to a power-on reset command, reading the configuration information in the configuration page and reading the additional page.

In a second aspect, embodiments of the present disclosure provide a method for configuring a memory device, the memory device including a configuration block; the configuration block comprises a configuration page and an additional page; the method comprises the following steps:

writing configuration information into the configuration page;

and if the configuration information contains error information, writing correction information of the error information into the additional page.

In a third aspect, embodiments of the present disclosure provide a memory device, including:

a memory cell array constituted by a plurality of memory blocks; at least one configuration block is included in the plurality of memory blocks, the configuration block including a configuration page and an additional page; the configuration page stores configuration information of the memory device; the additional page stores correction information of error information in the configuration information;

a control circuit; the control circuit is configured to operate the memory device based on the configuration information and the correction information.

In a fourth aspect, embodiments of the present disclosure provide a memory system, including:

a memory device configured to perform the method of any of the above embodiments; and

a memory controller coupled to the memory device and configured to control the memory device.

The disclosed embodiments provide a very simple way to re-trim a configuration block. The error information in the configuration page is modified by configuring the target modification data on the additional page of the configuration block, so that the whole configuration block does not need to be erased and reprogrammed, the setting of the target parameter is updated, the operation of modifying the configuration error is reduced, and the configuration efficiency before delivery is improved.

Drawings

Fig. 1 is a schematic diagram of an exemplary system provided by an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a memory card according to an embodiment of the disclosure;

fig. 3 is a schematic structural diagram of a Solid State Disk (SSD) according to an embodiment of the disclosure;

FIG. 4 is a schematic diagram of a memory device including a memory cell array and peripheral circuits according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a memory device including a memory cell array and peripheral circuits according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of another memory device including a memory cell array and peripheral circuits according to an embodiment of the present disclosure;

FIG. 7 is a flow chart of a method of operating a memory device according to an embodiment of the present disclosure;

FIG. 8 is a flow chart of yet another method of operating a memory device according to an embodiment of the present disclosure;

FIG. 9 is a flow chart of yet another method of operating a memory device according to an embodiment of the present disclosure;

FIG. 10 is a flow chart of yet another method of operating a memory device provided by an embodiment of the present disclosure;

FIG. 11 is a flow chart of yet another method of operating a memory device according to an embodiment of the present disclosure;

FIG. 12 is a flow chart of yet another method of operating a memory device provided by an embodiment of the present disclosure;

FIG. 13 is a flow chart of yet another method of operating a memory device according to an embodiment of the present disclosure;

FIG. 14 is a flow chart of yet another method of operating a memory device according to an embodiment of the present disclosure;

FIG. 15 is a flow chart of yet another method for configuring a memory device according to an embodiment of the present disclosure;

fig. 16 is a schematic diagram of another memory device according to an embodiment of the disclosure.

Detailed Description

To facilitate an understanding of the present disclosure, the present disclosure will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein in the description of the disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

As shown in fig. 1, an exemplary system 10 is shown in an embodiment of the present disclosure, and the exemplary system 10 may include a host 100 and a memory system 400. Exemplary systems 10 may include, but are not limited to, mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, Virtual Reality (VR) devices, Augmented Reality (AR) devices, or any other suitable electronic device having memory apparatus 300 therein; the host 100 may be a processor (e.g., a Central Processing Unit (CPU)) or a system on chip (SoC) (e.g., an Application Processor (AP)) of an electronic device.

In the disclosed embodiment, the host 100 may be configured to transmit data to the memory system 400 or receive data from the memory system 400. Here, the memory system 400 may include a memory controller 200 and one or more memory devices 300. The Memory device 300 may include, but is not limited to, a NAND Flash Memory (NAND Flash Memory), a Vertical NAND Flash Memory (Vertical NAND Flash Memory), a NOR Flash Memory (NOR Flash Memory), a Dynamic Random Access Memory (DRAM), a Ferroelectric Random Access Memory (FRAM), a Magnetic Random Access Memory (MRAM), a Phase Change Random Access Memory (PCRAM), a Resistive Random Access Memory (RRAM), a Nano Random Access Memory (NRAM), and the like.

In the disclosed embodiment, the memory controller 200 may be coupled to the memory device 300 and the host 100, and used to control the memory device 300. Illustratively, a storage controller may be designed for operation in a low duty cycle environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, and the like. In some embodiments, the storage controller may also be designed for operation in high duty cycle environments, such as SSD or embedded multimedia card (eMMC), and the SSD or eMMC may also be used as data storage and enterprise storage arrays for mobile devices, such as smart phones, tablet computers, laptop computers, and the like. Further, the storage controller may manage data in the memory device and communicate with the host. The memory controller may be configured to control operations such as memory device read, erase, and program; may also be configured to manage various functions with respect to data stored or to be stored in the memory device, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, and the like; may also be configured to handle Error Correction Codes (ECC) with respect to data read from or written into the memory device. In addition, the memory controller may also perform any other suitable function, such as formatting the memory device or communicating with an external device (e.g., host 100 in FIG. 1) according to a particular communication protocol. Illustratively, the storage controller may communicate with the external device via at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system small interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and so forth.

In the disclosed embodiments, the memory controller 200 and the one or more memory devices 300 may be integrated into various types of memory devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 10 may be implemented and packaged into different types of terminal electronics. As shown in fig. 2, the memory controller 200 and the single memory device 300 may be integrated into the memory card 40. The memory card 40 may include a PC card (PCMCIA), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, and the like. The memory card 40 may also include a memory card connector 42 that couples the memory card 40 with a host (e.g., host 100 in FIG. 1). In another embodiment as shown in fig. 3, the memory controller 200 and the plurality of memory devices 300 may be integrated into the SSD 50. The SSD50 may also include an SSD connector 52 that couples the SSD50 with a host (e.g., host 100 in FIG. 1). In some embodiments, the storage capacity and/or operating speed of SSD50 is greater than the storage capacity and/or operating speed of memory card 40.

As shown in fig. 4, each NAND memory string 308 may include a Source Select Gate (SSG) transistor 310 at its Source end and a Drain Select Gate (DSG) transistor 312 at its Drain end. The SSG transistors 310 and the DSG transistors 312 may be configured to activate selected NAND memory strings 308 (columns of the array) during read and program operations. In some implementations, for example, the SSG transistors 310 of the NAND memory strings 308 in the same block 304 are coupled to ground through the same Source Line (SL) 314 (e.g., common SL). According to some embodiments, the DSG transistor 312 of each NAND memory string 308 is coupled to a respective bit line 316, enabling data to be read from or written to the respective bit line 316 via an output bus. In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., above the threshold voltage of the DSG transistor 312) or deselect voltage (e.g., 0V) to the gate of the respective DSG transistor 312 via one or more DSG lines 313 and/or by applying a select voltage (e.g., above the threshold voltage of the SSG transistor 310) or deselect voltage (e.g., 0V) to the gate of the respective SSG transistor 310 via one or more SSG lines 315. As shown in FIG. 4, the NAND memory strings 308 may be organized into a plurality of blocks 304, each block 304 may have a common source line 314 therein. In some embodiments, each block 304 is the basic unit of data for an erase operation, i.e., all memory cells 306 on the same block 304 are erased at the same time. The memory cells 306 of adjacent NAND memory strings 308 may be coupled by a word line 318, with the word line 318 selecting which row of memory cells 306 is affected by the read and program operations. In some embodiments, each word line 318 is coupled to a page 320 of memory cells 306, page 320 being the fundamental data unit for the programming operation. The size in bits of one page 320 may relate to the number of NAND memory strings 308 coupled by a word line 318 in one block 304. Each word line 318 may include a plurality of control gates (gate electrodes) at each memory cell 306 in a respective page 320 and a gate line coupled to the control gates.

In some embodiments, configuration information may be embedded at certain locations of the memory cell array 301. For example, configuration information may be stored on one or more of the memory blocks 304, such as may be stored on a configuration block. Each memory block 304 may also include a plurality of pages 320, and a configuration block may utilize one or more pages 320 to store configuration information or any other suitable place to access during a Power On Reset (POR) initialization process.

Peripheral circuitry 302 may be coupled to memory cell array 301 through bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. Each memory cell in the memory cell array 301 may be a floating gate type memory cell including a floating gate transistor or a charge trap type memory cell including a charge trap transistor.

Peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory cell array 301 by applying and sensing voltage signals and/or current signals to and from each target memory cell 306 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. The peripheral circuit 302 may include various types of peripheral circuits formed using MOS (Metal Oxide Semiconductor) technology and/or CMOS (Complementary Metal Oxide Semiconductor) technology, and the like. For example, fig. 5 shows some exemplary peripheral circuits 302, including page buffers/sense amplifiers 404, column decoders/bit line drivers 406, I/O circuits 407, row decoders/word line drivers 408, voltage generators 410, control logic 412, registers 414, interfaces 416, and a data bus 418. It should be understood that additional peripheral circuitry not shown in fig. 4 may also be included.

The page buffer/sense amplifier 404 may be configured to read and program (i.e., write) data from and to the memory cell array 301 according to a control signal from the control logic unit 412. In some embodiments, the page buffer/sense amplifier 404 may store a page of program data (i.e., write data) to be programmed into one page 320 of the memory cell array 301. In other embodiments, page buffer/sense amplifiers 404 may also perform program verify operations to ensure that data has been properly programmed into memory cells 306 coupled to the selected word line 318. In still other embodiments, page buffer/sense amplifier 404 may also sense a low power signal from bit line 316 representing a data bit stored in memory cell 306 in a read operation and amplify a small voltage swing to an identifiable logic level.

The column decoder/bit line driver 406 may be configured to be controlled by the control logic unit 412 and select one or more NAND memory strings 308 by applying the bit line voltages generated by the voltage generator 410. I/O circuitry 407 may be coupled to page buffer/sense amplifiers 404 and/or column decoder/bit line drivers 406 and configured to direct (route) data inputs from data bus 418 to desired memory cell regions (e.g., banks) of memory cell array 301 and to direct (route) data outputs from the desired memory cell regions to data bus 418.

The row decoder/word line driver 408 may be configured to be controlled by the control logic unit 412 and to select a memory block 304 of the memory cell array 301 and a word line 318 of the selected memory block 304. The row decoder/word line driver 408 may also be configured to drive the selected word line 318 using the word line voltage generated by the voltage generator 410. The voltage generator 410 may be configured to be controlled by the control logic unit 412 and generate word line voltages (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, and a verify voltage) to be supplied to the memory cell array 301.

Registers 414 may be coupled to control logic unit 412 and include status registers, command registers, and address registers to store status information, command operation codes, and command addresses for controlling the operation of each peripheral circuit. For example, register 414 may store the contents and addresses of the relevant configuration information, e.g., the configuration information in the configuration block may be loaded into the register during the POR initialization process, so that subsequent memory devices may be configured according to the configuration information stored by the register. The register 414 may be a RAM (Random Access Memory). Interface 416 may be coupled to control logic 412 and act as a control buffer to buffer and forward control commands received from the host to control logic 412 and to buffer and forward status information received from control logic 412 to the host. The interface 416 may also be coupled to the I/O circuitry 407 via a data bus 418 and act as a data I/O interface and data buffer, buffering write data received from the host and forwarding it to the I/O circuitry 407, and buffering read data from the I/O circuitry 407 and forwarding it to the host. For example, interface 416 may include a data I/O417 coupled to a data bus 418.

In the embodiment of the present disclosure, the memory Cell may be a Single Level Cell (SLC) having two possible memory states and thus may store one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In other embodiments, each memory Cell is a Multi-Level Cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per Cell, three bits per Cell (also referred to as Triple Level Cell, TLC)), or four bits per Cell (also referred to as Quad Level Cell, QLC). Each MLC may be programmed to assume a range of possible nominal stored values. For example, if each MLC stores two bits of data, the MLC may be programmed to assume one of three possible programming levels from the erased state by writing one of three possible nominal storage values to the memory cell. Wherein the fourth nominal storage value may be used for the erased state.

In the embodiment of the present disclosure, as shown in fig. 6, the memory cell array 301 includes a plurality of memory blocks 304, and each memory block 304 includes a plurality of memory cells. The storage block 304 includes at least a configuration block 330, and may also include other blocks 331, such as: data blocks, even dedicated test blocks, and backup blocks, etc., where the blocks may be physically separated from each other. Alternatively, the memory device may include different functional areas such as a system area, a data area, a test area, and a reserved area, and the configuration block 330 may be located in the system area of the memory device so that blocks different from their attributes may be physically separated from each other.

The peripheral circuit of the memory device includes: control logic 412, registers 414 that may store configuration information for the configuration blocks, and firmware 500 that may store instructions to facilitate the POR initialization process.

The configuration block is used to store key information of the NAND, such as parameters about column repair, parameters about bad blocks, parameters about Trim, and contents about eREM (an embedded firmware repair mechanism), etc. Wherein the Trim parameter comprises a set of operating parameters for the NAND die: such as voltage, current, temperature compensation, power, etc. The Trim parameter can be classified at least as: static Trim (Static modification Parameter) and Parameter Trim (modification Parameter). While the Static Trim may directly modify some parameters on the control circuitry (e.g., the peripheral circuitry described above), the Parameter Trim may first have firmware read, which refers to a software program or set of instructions programmed on a non-volatile memory, such as a ROM device (e.g., EPROM, EEPROM, etc.). The firmware may be stored in a memory block, may be loaded in a control circuit of the memory device before the memory device is shipped from a factory, may be located in a memory controller, and implements various operations and functions of the memory device by executing code instructions in the firmware.

After the firmware reads the Parameter Trim, some parameters on the control circuit are modified correspondingly.

The eREM may be in the form of a software program of a set of instructions programmed on a memory cell array of a memory device. For example, the eREM may be embedded on the memory cell array (e.g., stored in a configuration block or in a particular form) so that the contents of the eREM may be discovered during the POR initialization process. The memory cell array may form the main storage medium of the memory device. The POR initialization process may be performed by executing firmware by a data processing device, which may be in peripheral circuitry of the memory device. During the POR initialization process, the data processing device may access the memory cell array, load and execute the firmware repair instructions of eREM to repair the firmware. During the execution of the POR initialization procedure, the data processing device can access the memory cell array according to the firmware program and write the contents of the configuration block into the control circuit.

Firmware repair instructions are embedded in the memory unit and executed by the control logic unit at an early stage of the initialization process to repair various forms of firmware bugs. For example, eREM may be enabled prior to register initialization, internal ZQ calibration, and/or temperature sensor initialization. In this way, firmware bugs may be repaired after eREM is performed to reduce the stringent requirements imposed on the firmware.

In a test flow before leaving a factory, storing the key information of the NAND into a configuration block, then, when leaving the factory for use, initiating configuration on the NAND chip through a POR command (FFh), loading the key information of the NAND in the configuration block into a corresponding register (for example, an RAM, an SRAM and the like) in a peripheral circuit in the configuration process, and after the loading is finished, performing various operations on the memory device.

If the wrong data is configured into the configuration block, the wrong parameter settings may cause the device to fail in operation or interfere with or even damage the device during use. In some embodiments, this problem may be solved by employing a method of deleting and reprogramming configuration blocks during pre-factory testing. For example, at least one data on a page of the memory cell array that may have been configured with unsuitable parameters during a pre-factory test procedure may need to be modified. The normal modification process is that firstly, all data in the configuration block is read out; the entire configuration block is then erased because the erasure of NAND is in blocks; the data that needs to be modified is then modified, while other data can be reprogrammed to be written without modification. This process is a complex process involving a large amount of data, both data that needs to be modified and data that does not need to be modified, and is prone to other errors during read-rewrite. And the read data also needs to be stored by the storage block, and if the residual storage space of the NAND is smaller than that of the configuration block, the above process cannot be performed even.

In view of this, the disclosed embodiments provide a method of operating a memory device, the memory device including a configuration block; the configuration block comprises a configuration page and an additional page; as shown in fig. 7, the method includes:

step S101, reading the configuration information in the configuration page and reading the additional page;

step S102, if the additional page is read to have the correction information, operating the memory device based on the configuration information and the correction information; wherein the correction information is used for correcting error information in the configuration information.

The configuration block in the memory device of the embodiments of the present disclosure contains not only the configuration page but also additional pages. The configuration page may be one page or a plurality of pages, and the additional page may be one page or a plurality of pages. The configuration page may be used to store key information for the NAND and the additional pages may be used to store correction information. The correction information may include information other than the error information determined according to a predetermined requirement or a debugging process, such as correction information for Trim parameters and correction information for eREM parameters. The configuration page and the additional page may be located in the same configuration block, and it is understood that the configuration page and the additional page are easier to read in the same configuration block than the configuration page and the additional page in different configuration blocks.

The correction information present in the additional page may include a target correction address and data of the target correction, and the correction information may be used to modify error information of a specified address in the configuration information. The error information is an error found in the debugging process after the configuration information is configured, or information found to be unsuitable for use based on new requirements, for example, information of unsuitable Trim parameters or information of non-optimal Trim parameters set in the pre-factory configuration process.

It should be noted that the operation method herein is a method of using the memory device, and the configuration and debugging process thereof is completed. It can be understood that the configuration information of the configuration block in the embodiment of the present disclosure includes the error information, the error information is always stored in the configuration block, and the additional page is independent of the configuration page, so that during the use of the memory device, the configuration information needs to be read first, then the correction information needs to be read, and the error information needs to be covered by the correction information and then used. Thus, the corrected correct configuration information can be used during the use process.

Finally, the memory can be operated based on the correct or optimized configuration information, and the operation comprises a reading operation, an erasing operation and the like.

The disclosed embodiments provide a very simple way to re-trim a configuration block. The error information in the configuration page is modified by configuring the target modification data on additional pages of the configuration block, and the setting of the target Trim/eREM parameters may be updated without erasing and reprogramming the entire configuration block.

In some embodiments, as shown in fig. 8, the method further comprises:

step S103, after the configuration information is read, loading the configuration information to a control circuit of the memory device;

step S104, if the correction information is read, loading the correction information to the control circuit;

in the step S102, operating the memory device based on the configuration information and the correction information includes:

step S201, operating the memory device through the control circuit loaded with configuration information and correction information.

Control circuitry, such as the peripheral circuitry described above, may be utilized in a memory system to operate an array of memory cells.

It is understood that after reading the configuration information, the configuration information can be loaded to the control circuit, and then the correction information in the additional page can be read and loaded to the control circuit. Or directly reading the additional page after reading the configuration information, and if reading the correction information, loading the configuration information to the control circuit and finally loading the correction information. When the correction information is loaded, the correction information covers the error information in the loaded configuration information, so that the loaded configuration information is correct or optimized.

In some embodiments, as shown in fig. 9, the step of loading the configuration information to the control circuit of the memory device in the step S103 includes:

301, storing configuration information into a plurality of registers of a control circuit; the configuration information stored in at least one register is error information;

in the step 104, the loading the correction information into the control circuit includes:

step 302, the correction information is stored in the register storing the error information to update the error information.

The control circuitry may be part of the peripheral circuitry of the memory device, e.g., including control logic units and registers. The control circuit may also be a peripheral circuit of the memory device, including: page buffers/sense amplifiers, column decoders/bit line drivers, I/O circuits, row decoders/word line drivers, voltage generators, control logic units, at least one register, interfaces, and data buses, among others. In some embodiments, the configuration information may be stored in at least one register of the control circuit. When the memory device needs to be operated, the configuration information stored in the register corresponding to the operation instruction can be called according to the operation instruction to configure the voltage, the current and the like. For example, when the operation instruction is a write instruction, the corresponding write configuration information in the register may be called. According to the write configuration information, the voltage generator may generate and output a program voltage to a word line and/or a bit line of the memory cell array.

In some embodiments, the correction information may be stored in the same register as the configuration information, or may even be in the same location in the same register. The RAM register which can be used by the register has the advantage that the RAM register is a register which can be read and written at any time, can write data into a storage unit of any specified address at any time and can also read data from the storage unit of any specified address at any time. Thus, the modification of the configuration information can be conveniently realized. Therefore, the correction information can be overwritten by erroneous or suboptimal information in the configuration information during use of the memory device.

In some embodiments, as shown in fig. 10, the step of operating the memory device by the control circuit loaded with the configuration information and the correction information in step S201 includes:

step S401, generating a control signal for operating the memory device according to the configuration information and the correction information stored in the register by using the control circuit;

step S402, operating the memory device by the control signal.

The control circuitry may generate control signals (e.g., control signals for the three-dimensional memory word lines and control signals for the bit lines, etc.) for various voltages (e.g., program voltages, read voltages, bit line bias voltages, etc.).

The information of the control signal includes whether or not to allow the voltage application of the voltage generation block, where the voltage application is allowed and not allowed, the allowed on time, the prohibited application time, and the like of each signal can be controlled.

Such information of the control signal may be determined according to the configuration information and the correction information.

In some embodiments, as shown in fig. 11, the method further comprises:

in step S105, if no more positive information is read in the additional page, the memory device is operated based on the configuration information.

It will be appreciated that the memory device may not have error information during pre-factory configuration, and therefore, this case also does not require writing of correction information in the additional pages. However, since the configuration of the memory device is fixed, additional pages still need to be read during use.

For a memory device without correction information, the correction information is not read after reading the additional page, so that the read configuration information does not need to be refreshed, and the memory device can be operated by directly using the configuration information.

In some embodiments, as shown in fig. 12, the method further comprises:

step S501, after the configuration information is read, the configuration information is loaded to a control circuit of the memory device;

in the step S105, the step of operating the memory device based on the configuration information includes:

step S502, operating the memory device through the control circuit loaded with the configuration information.

If the correction information is not read when the additional page is read, it is no longer necessary to load the correction information to the control circuit. Accordingly, the configuration information may be loaded to the control circuit after the configuration information is read and before the additional page is read, or the configuration information may be loaded to the control circuit after the additional page is read. Finally, the read configuration information is used to operate the memory device.

In some embodiments, as shown in fig. 13, the loading the configuration information to the control circuit of the memory device in step S501 includes:

step S601, storing the configuration information into a plurality of registers of the control circuit;

in the step S502, the operating the memory device by the control circuit loaded with the configuration information includes:

step S602, generating, by the control circuit, a control signal for operating the memory device according to the configuration information stored in the register;

the memory device is controlled by the operation signal.

When the memory device needs to be operated, the configuration parameters in the register corresponding to the operation instruction can be called according to the operation instruction to configure the voltage, the current and the like. For example, when the operation instruction is a write instruction, the corresponding configuration information in the register may be called. According to the configuration information, the voltage generator may generate and output a program voltage to a word line and/or a bit line of the memory cell array.

The control circuit may generate control signals for various voltages (e.g., program voltage, read voltage). The information of the control signal includes whether or not to allow the voltage application of the voltage generation block, where the voltage application is allowed and not allowed, the allowed on time, the prohibited application time, and the like of each signal can be controlled.

Such information of the control signal may be decided according to the configuration information.

In some embodiments, as shown in fig. 14, in step S101, the reading the configuration information in the configuration page and the reading the additional page includes:

step S701, in response to the power-on reset command, reads the configuration information in the configuration page and reads the additional page.

In some embodiments, it is necessary to respond to a power-on reset command (FFh) to write configuration information and correction information into the control circuit. When a power-on reset command is received, the memory device may first read the configuration information for the configuration page in the configuration block and store it in the control circuitry (e.g., a register), and then read the additional page. Or directly reading the configuration page and the additional page when receiving the power-on reset command.

In some embodiments, the firmware program that reads and loads the configuration information in the configuration block adds an end algorithm to read and load the extra page data at the end of the original firmware program. Here, the original firmware program refers to a program that can be used to read and load data in the configuration page of the configuration block without reading and loading data of the additional page. If the data of the additional page read after the firmware program executes the program for reading the additional page is invalid data, that is, no correction information is read in the additional page, the firmware program may not execute the program for loading the data of the additional page.

If the data of the additional page read after the firmware program executes the program for reading the additional page is not all invalid data, that is, the correction information is read in the additional page, the firmware program can execute the data program for loading the additional page, so that the data of the additional page can be written into the control circuit and the error information is covered. Since the correction information can directly cover the error information, the writing position of the correction information can be consistent with the position of the error information, so that the content of the correction information in the additional page not only includes the parameter value of the correction information but also includes the address information of the error information to be covered by the correction information. For example, the format of the correction information may be (address, parameter value), and similarly, the format of the configuration information may also be (address, parameter value).

The embodiment of the disclosure executes the power-on reset command based on the firmware program, and performs a read operation on the data of the additional page regardless of whether the data of the additional page has the written correction information. Thus the time used by the power-on-reset command is increased by at least the time to read the additional page; if the additional page is written with the correction information, it is necessary to add an additional page of time to load the control circuit and to overwrite the error information, but these times are in the order of one hundred microseconds, which are hardly perceptible to the user during actual operation.

The embodiment of the present disclosure also provides a configuration method of a memory device, as shown in fig. 15, the memory device includes a configuration block; the configuration block comprises a configuration page and an additional page; the method comprises the following steps:

step S1001, writing configuration information into a configuration page;

step S1002, if the configuration information contains error information, writing correction information of the error information into the additional page.

In a test flow before the memory device leaves a factory, configuration blocks of the memory device need to be configured, that is, configuration information and correction information are written into pages of corresponding configuration blocks. If no error information exists in the configuration information, the additional page may not be written. If there is error information in the configuration information, correction information for modifying the error information may be written to the additional page. In some embodiments, after the correction information is written into the additional page, the correction information can be read to ensure that the correction information is correctly written.

An embodiment of the present disclosure provides a memory device, as shown in fig. 16, the memory device 300 includes:

a memory cell array 301 composed of a plurality of memory blocks 304; the plurality of memory blocks 304 includes at least one configuration block 330, the configuration block 330 including a configuration page 341 and an additional page 342; the configuration page 341 stores configuration information of the memory device; the additional page 342 stores correction information of error information in the configuration information;

a control circuit 401; the control circuit 401 is configured to operate the memory device 300 based on the configuration information and the correction information.

The memory device 300 may include a plurality of memory blocks 304, wherein at least one of the memory blocks 304 may serve as a configuration block 330 for storing configuration information. The configuration block 330 may be divided into at least two parts, a first part for placing the configuration page 341 and a second part for placing the additional page 342. If the configuration page 341 is more than one page, the page addresses of the configuration page 341 may be consecutive, and if the additional page 342 is more than one page, the page addresses of the additional page 342 may also be consecutive. The address of the configuration page 341 and the address of the additional page 342 may also be consecutive addresses.

The embodiment of the present disclosure further provides a memory system, as shown in fig. 1, where the memory system 400 includes:

a memory device 300 configured to perform a method as described in any of the embodiments above; and

a memory controller 200 coupled to the memory device 300 and configured to control the memory device 300.

In some embodiments, the memory system 400 may be a product such as an SSD, and may also be an electronic device such as a computer device including the memory apparatus 300.

According to the embodiment of the disclosure, the additional page is additionally arranged in the configuration block, so that the problem that the data setting error of the configuration page in the configuration block is difficult to modify is effectively solved. It will be appreciated that this additional page is present in the configuration block regardless of whether error information is present in the configuration block. When there is error information in the configuration block, correction information for the error information in the configuration information is stored in the additional page. When no error information exists in the configuration block, invalid information is stored in the additional page, i.e., the additional page is in an erased state. After the POR command is sent to the memory device, the information in the configuration page and the additional page is read, when invalid information is stored in the additional page, the configuration information in the configuration page can be loaded into the control circuit, and when the memory device needs to be operated subsequently, the configuration information in the control circuit is called to perform corresponding operation on the memory device. When the additional page stores the correction information, the configuration information in the configuration page can be loaded into the control circuit, then the correction information is loaded into the control circuit and covers the error information in the configuration information, and when the memory device needs to be operated subsequently, the configuration information and the correction information in the control circuit are called to perform corresponding operation on the memory device.

By adopting the mode, the standard of the product can be unified, and the independent setting of the operation program for the products under different conditions is not needed, so that the development cost is reduced.

It should be appreciated that reference throughout this specification to "some embodiments," "one embodiment," or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The above-mentioned serial numbers of the embodiments of the present disclosure are merely for description and do not represent the merits of the embodiments.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The above description is only an embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered by the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (11)

1. A method of operating a memory device, the memory device comprising a configuration block; the configuration block comprises a configuration page and an additional page; the method comprises the following steps:

reading the configuration information in the configuration page and reading the additional page;

if the additional page is read to have the correction information, operating the memory device based on the configuration information and the correction information; wherein the correction information is used for correcting error information in the configuration information.

2. The method of operation of claim 1, further comprising:

loading the configuration information to control circuitry of the memory device after reading the configuration information;

if the correction information is read, loading the correction information to the control circuit;

the step of operating the memory device based on the configuration information and the correction information comprises:

operating the memory device through the control circuit loaded with the configuration information and the correction information.

3. The method of claim 2, wherein the step of loading the configuration information into the control circuitry of the memory device comprises:

storing the configuration information into a plurality of registers of the control circuit; wherein the configuration information stored in at least one of the registers is the error information;

the loading of the correction information to the control circuitry comprises:

storing the correction information into the register storing the error information to update the error information.

4. The operating method according to claim 3, wherein the step of operating the memory device by the control circuit loaded with the configuration information and the correction information comprises:

generating, with the control circuit, a control signal to operate the memory device according to the configuration information and the correction information stored in the register;

operating the memory device by the control signal.

5. The method of operation of claim 1, further comprising:

if the correction information is not read in the additional page, operating the memory device based on the configuration information.

6. The method of operation of claim 5, further comprising:

loading the configuration information to control circuitry of the memory device after reading the configuration information;

the step of operating the memory device based on the configuration information comprises:

operating the memory device through a control circuit loaded with the configuration information.

7. The method of claim 6, wherein loading the configuration information into the control circuitry of the memory device comprises:

storing the configuration information into a plurality of registers of the control circuit;

the step of operating the memory device by the control circuit loaded with the configuration information comprises:

generating, with the control circuit, a control signal to operate the memory device according to the configuration information stored in the register;

operating the memory device by the control signal.

8. The operating method according to any one of claims 1 to 7, wherein the step of reading the configuration information in the configuration page and reading the additional page comprises:

and responding to a power-on reset command, reading the configuration information in the configuration page and reading the additional page.

9. A method of configuring a memory device, the memory device comprising a configuration block; the configuration block comprises a configuration page and an additional page; the method comprises the following steps:

writing configuration information into the configuration page;

and if the configuration information contains error information, writing correction information of the error information into the additional page.

10. A memory device, the memory device comprising:

a memory cell array constituted by a plurality of memory blocks; at least one configuration block is included in the plurality of memory blocks, the configuration block including a configuration page and an additional page; the configuration page stores configuration information of the memory device; the additional page stores correction information of error information in the configuration information;

a control circuit; the control circuit is configured to operate the memory device based on the configuration information and the correction information.

11. A memory system, the memory system comprising:

a memory device configured to perform the method of any of claims 1-8; and

a memory controller coupled to the memory device and configured to control the memory device.

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