CN115064443A - Manufacturing method of power semiconductor structure - Google Patents
Manufacturing method of power semiconductor structure Download PDFInfo
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- CN115064443A CN115064443A CN202210701050.7A CN202210701050A CN115064443A CN 115064443 A CN115064443 A CN 115064443A CN 202210701050 A CN202210701050 A CN 202210701050A CN 115064443 A CN115064443 A CN 115064443A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 40
- -1 arsenic ions Chemical class 0.000 claims abstract description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 238000011049 filling Methods 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 17
- 229910052785 arsenic Inorganic materials 0.000 claims abstract description 15
- 238000000151 deposition Methods 0.000 claims abstract description 15
- 238000001259 photo etching Methods 0.000 claims abstract description 15
- 229920005591 polysilicon Polymers 0.000 claims abstract description 15
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 12
- 239000011574 phosphorus Substances 0.000 claims abstract description 12
- 229910052796 boron Inorganic materials 0.000 claims abstract description 10
- 230000002093 peripheral effect Effects 0.000 claims abstract description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 6
- 210000000746 body region Anatomy 0.000 claims abstract description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 4
- 239000007943 implant Substances 0.000 claims abstract description 4
- 238000005498 polishing Methods 0.000 claims abstract description 4
- 238000000227 grinding Methods 0.000 claims abstract description 3
- 229910052751 metal Inorganic materials 0.000 claims description 56
- 239000002184 metal Substances 0.000 claims description 56
- 238000005530 etching Methods 0.000 claims description 26
- 238000005229 chemical vapour deposition Methods 0.000 claims description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 8
- 229910052721 tungsten Inorganic materials 0.000 claims description 8
- 239000010937 tungsten Substances 0.000 claims description 8
- MXSJNBRAMXILSE-UHFFFAOYSA-N [Si].[P].[B] Chemical compound [Si].[P].[B] MXSJNBRAMXILSE-UHFFFAOYSA-N 0.000 claims description 7
- 239000011521 glass Substances 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000000206 photolithography Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 2
- 150000004706 metal oxides Chemical class 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The disclosure relates to the field of power semiconductors, in particular to a method for manufacturing a power semiconductor structure, which comprises the following steps: filling oxide on the oxide layer in the groove; polishing and grinding the structure filled with the oxide, and then injecting conductive polysilicon into the oxide; forming a groove in the oxide injected with the conductive polysilicon through photoetching; depositing doped conductive polysilicon on the oxide layer in the trench, and injecting phosphorus and/or boron into the conductive polysilicon, wherein the peripheral specific region is positioned above the bottom of the conductive polysilicon and is defined as a body region; and selecting a specific region to implant arsenic ions in other regions of the upper surface of the substrate by photoetching, and diffusing the arsenic ions by high-temperature junction pushing, wherein the region into which the arsenic ions are diffused is defined as a source region. The current input end and the current output end of the current amplifier are arranged on the front side, and meanwhile, MOS (metal oxide semiconductor) can be ensured to circulate large current.
Description
Technical Field
The disclosure relates to the field of power semiconductors, and in particular relates to a manufacturing method of a power semiconductor structure.
Background
The power semiconductor device has a structure different from that of a general semiconductor and is not damaged even when a high voltage and a large current are used. In addition, the use of large power is likely to generate heat and generate high temperature, which causes a failure. The current mainstream technology of the power semiconductor is DMOS, drain metal is on the back of a wafer, and back metal is thinned on the back of the wafer after front metal is made; the DMOS wafer flowing period is long, and is mainly limited by the fact that the purchasing period of the epitaxial wafer is too long, the supply quantity is short, and the cost for purchasing the epitaxial wafer is too high. The adjustment process of the Breakdown Voltage (BV) of the power semiconductor device is complex, and can be realized by adjusting the size of the groove and the injection specification in multiple different engineering batches. And the breakdown current is increased to a limited extent due to the too long conducting path due to the isolation effect of the trench.
Disclosure of Invention
The disclosure provides a power semiconductor structure manufacturing method, which can solve the problem that the improvement of breakdown current is limited due to the isolation effect of a groove and the overlong conducting path, and ensure that a semiconductor structure can bear the flowing heavy current. In order to solve the technical problem, the present disclosure provides the following technical solutions:
as an aspect of the embodiments of the present disclosure, there is provided a method for manufacturing a power semiconductor structure, including the steps of:
etching the substrate to form a groove;
thermally growing an oxide layer on the inner wall of the groove;
filling oxide on the oxide layer in the groove;
polishing and grinding the structure filled with the oxide, and then injecting conductive polysilicon into the oxide;
forming a groove in the oxide injected with the conductive polysilicon through photoetching;
depositing doped conductive polycrystalline silicon on the oxide layer in the groove, injecting phosphorus and/or boron into the conductive polycrystalline silicon, and removing redundant conductive polycrystalline silicon by dry etching after annealing;
injecting phosphorus ions and/or boron ions into a peripheral specific region at the position of a selected groove on the upper surface of the substrate by photoetching, and distributing the phosphorus ions and/or the boron ions on the silicon substrate among the grooves by high-temperature junction pushing, wherein the peripheral specific region is positioned above the bottom of the conductive polycrystalline silicon and is defined as a body region;
and selecting a specific region to implant arsenic ions in other regions of the upper surface of the substrate by photoetching, and diffusing the arsenic ions by high-temperature junction pushing, wherein the region into which the arsenic ions are diffused is defined as a source region.
Preferably, the method further comprises the following steps after the source region is defined:
defining boron-phosphorus-silicon glass on the upper surface of the substrate as a first insulating medium layer;
etching a first contact hole on the first insulating medium layer, and filling metal tungsten in the first contact hole;
depositing a metal layer on the first insulating medium layer to define the metal layer as a first metal layer; the first metal layer is divided into a first source metal layer and a first drain metal layer by photolithography and etching.
Preferably, the method further comprises the following steps after the first metal layer is divided into the first source metal layer and the first drain metal layer by photolithography and etching:
depositing boron-phosphorus-silicon glass on the first metal layer to define the first metal layer as a first insulating medium layer;
and etching a second contact hole on the second insulating medium layer, and filling metal tungsten in the second contact hole.
Preferably, after filling the second contact hole with the tungsten metal, the method further includes the following steps:
depositing a second metal layer on the second insulating dielectric layer, forming a gate metal by photolithography and etching, and/or,
a source metal;
and/or the presence of a gas in the gas,
a drain metal;
preferably, before etching the substrate to form the trench, the method further includes the following steps:
providing a substrate, wherein the substrate is a P-type substrate;
and/or the presence of a gas in the atmosphere,
and implanting phosphorus and/or arsenic on the upper surface of the substrate.
Preferably, the step of etching the substrate to form the trench specifically includes:
depositing a hard mask on the upper surface of the substrate;
forming a groove pattern on the hard mask by photoetching;
and etching the substrate to form a groove.
Preferably, the step of thermally growing an oxide layer on the inner wall of the trench includes:
and removing the sacrificial layer and the hard mask by wet etching, and thermally growing an oxide layer on the inner wall of the groove.
Preferably, the step of filling the oxide layer in the trench includes:
and filling the oxide in the groove by adopting chemical vapor deposition equipment.
Preferably, the chemical vapor deposition equipment is used for realizing high-density plasma chemical vapor deposition of the oxide.
Preferably, the oxide is silicon dioxide.
The method does not need to thin the back gold, and has good improvement on cost reduction and production period shortening. The electric polycrystalline silicon forms a conductive channel on one side of the groove, a thick oxide layer is filled on the other side of the groove, the metal electrodes are arranged on the front surface of the chip, the current input end and the current output end of the structure are arranged on the front surface, and meanwhile, MOS (metal oxide semiconductor) circulation large current can be ensured.
Drawings
FIG. 1 is a schematic view of a substrate structure in an embodiment;
FIG. 2 is a schematic structural diagram of a trench etched in the embodiment;
FIG. 3 is a schematic diagram of an embodiment of a structure of a backfill oxide layer and a conductive polysilicon layer;
FIG. 4 is a schematic structural diagram of forming a body region and a source region by ion implantation in an embodiment;
FIG. 5 is a schematic structural diagram of deposition of BPSG, etching of contact holes, filling of contact holes and sputtering of a metal layer in an embodiment;
FIG. 6 is a schematic structural diagram of a molded power semiconductor in an embodiment;
Detailed Description
The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
As an aspect of the embodiments of the present disclosure, the present embodiments provide a method for manufacturing a power semiconductor structure, including the steps of:
step one, providing a substrate 1, wherein the substrate 1 is a P-type substrate as shown in fig. 1;
step two, as shown in fig. 2, etching the substrate 1 to form a groove 2; the trench 2 is divided into a cell trench and a termination trench.
Step three, removing the sacrificial layer and the hard mask by wet etching, and thermally growing an oxide layer 3 on the inner wall of the groove 2 as shown in fig. 3;
filling oxide on the oxide layer 3 in the trench 2; for example, the trench 2 is backfilled with HDP oxide, the oxide layer is thermally grown in a furnace tube, and subsequent polishing is required to accurately control the thickness. As shown in fig. 3, the oxide is thick on one side of the trench 2, the other side is thin, the thin side is used as gate oxide, and the thick side is used for isolating the conductive polysilicon 4 from the body region, and it is necessary to fill the trench with oxide and dig a rectangular trench by photolithography and etching processes.
Fifthly, injecting phosphorus and/or boron into the conductive polysilicon;
sixthly, after annealing, removing redundant conductive polysilicon by dry etching;
step seven, injecting phosphorus ions and/or boron ions into a peripheral specific region of the position of the selected groove 2 on the upper surface of the substrate 1 through photoetching;
step eight, as shown in fig. 4, the phosphorus ions and/or boron ions are distributed on the silicon substrate base 1 between the trenches 2 through high-temperature junction pushing, and the peripheral specific region is positioned above the bottom of the conductive polysilicon 4 and is defined as a body region;
step nine, selecting a specific area to inject arsenic ions into other areas on the upper surface of the substrate 1 through photoetching, and diffusing the arsenic ions through high-temperature junction pushing, wherein the area to which the arsenic ions are diffused is defined as a source area;
step ten, as shown in fig. 5-6, defining Boron Phosphorus Silicon Glass (BPSG) on the upper surface of the substrate 1 as a first insulating dielectric layer 5;
step eleven, etching a first contact hole 6 on the first insulating medium layer 5, and filling metal tungsten in the first contact hole 6;
step twelve, depositing a metal layer on the first insulating medium layer to define the metal layer as a first metal layer 7; the first metal layer is divided into a first source metal layer 7-1 and a first drain metal layer 7-2 by photoetching and etching, and the two metals are arranged in an interdigital shape.
Thirteen, depositing Boron Phosphorus Silicon Glass (BPSG) on the first metal layer 7, and defining the boron phosphorus silicon glass as a second insulating dielectric layer 8; and etching a second contact hole 9 on the second insulating medium layer 8, and filling metal tungsten in the second contact hole 9.
Fourteen, depositing a second metal layer 10 on the second insulating medium layer 8, and forming grid metal and/or source metal through photoetching and etching; and/or, a drain metal.
In some embodiments, it is also desirable to implant phosphorous and/or arsenic on the upper surface of the substrate 1.
In some embodiments, the step of etching the substrate 1 to form the trench 2 specifically includes:
depositing a hard mask on the upper surface of the substrate 1;
forming a groove 2 pattern on the hard mask by photoetching;
the substrate 1 is then etched to form trenches 2.
In some embodiments, the step of thermally growing an oxide layer 3 on the inner wall of the trench 2 includes:
and removing the sacrificial layer and the hard mask by wet etching, and thermally growing an oxide layer 3 on the inner wall of the groove 2.
In some embodiments, the step of filling the oxide layer 3 in the trench 2 with oxide includes:
the oxide is filled in the trench 2 by using a chemical vapor deposition apparatus.
In some embodiments, the chemical vapor deposition apparatus is used to achieve high density plasma chemical vapor deposition of oxides.
In some embodiments, the oxide is silicon dioxide.
The electric polycrystalline silicon of the embodiment forms a conductive channel on one side of the groove 2, the thick oxide layer 3 is filled on the other side of the groove, the metal electrodes are arranged on the front surface of the chip, the current input end and the current output end of the structure are arranged on the front surface, and meanwhile, MOS circulating heavy current can be ensured.
Although embodiments of the present disclosure have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the disclosure, the scope of which is defined in the appended claims and their equivalents.
Claims (10)
1. A method for manufacturing a power semiconductor structure is characterized by comprising the following steps:
etching the substrate to form a groove;
thermally growing an oxide layer on the inner wall of the groove;
filling oxide on the oxide layer in the groove;
polishing and grinding the structure filled with the oxide, and then injecting conductive polysilicon into the oxide;
injecting phosphorus and/or boron into the conductive polysilicon, and removing redundant conductive polysilicon by dry etching after annealing;
injecting phosphorus ions and/or boron ions into a peripheral specific region at the position of a selected groove on the upper surface of the substrate by photoetching, and distributing the phosphorus ions and/or the boron ions on the silicon substrate among the grooves by high-temperature junction pushing, wherein the peripheral specific region is positioned above the bottom of the conductive polycrystalline silicon and is defined as a body region;
and selecting a specific region to implant arsenic ions in other regions of the upper surface of the substrate by photoetching, and diffusing the arsenic ions by high-temperature junction pushing, wherein the region into which the arsenic ions are diffused is defined as a source region.
2. The method of fabricating a power semiconductor structure according to claim 1, further comprising, after defining the source region, the steps of:
defining boron-phosphorus-silicon glass on the upper surface of the substrate as a first insulating medium layer;
etching a first contact hole on the first insulating medium layer, and filling metal tungsten in the first contact hole;
depositing a metal layer on the first insulating medium layer to define the metal layer as a first metal layer; the first metal layer is divided into a first source metal layer and a first drain metal layer by photolithography and etching.
3. The method for fabricating a power semiconductor structure according to claim 2, further comprising, after dividing the first metal layer into the first source metal layer and the first drain metal layer by photolithography and etching, the steps of:
depositing boron-phosphorus-silicon glass on the first metal layer to define the first metal layer as a first insulating medium layer;
and etching a second contact hole on the second insulating medium layer, and filling metal tungsten in the second contact hole.
4. The method for manufacturing a power semiconductor structure according to claim 3, further comprising the following steps after filling the second contact hole with the metal tungsten:
depositing a second metal layer on the second insulating medium layer, and forming a gate metal and/or a source metal by photoetching and etching; and/or, a drain metal.
5. The method for fabricating a power semiconductor structure according to any one of claims 1 to 4, further comprising, before etching the substrate to form the trench, the steps of:
providing a substrate, wherein the substrate is a P-type substrate;
and/or the presence of a gas in the gas,
and implanting phosphorus and/or arsenic on the upper surface of the substrate.
6. The method for manufacturing a power semiconductor structure according to any one of claims 1 to 4, wherein the step of etching the substrate to form the trench specifically comprises:
depositing a hard mask on the upper surface of the substrate;
forming a groove pattern on the hard mask by photoetching;
and etching the substrate to form a groove.
7. The method for fabricating a power semiconductor structure according to any one of claims 1 to 6, wherein the step of thermally growing an oxide layer on the inner wall of the trench comprises:
and removing the sacrificial layer and the hard mask by wet etching, and thermally growing an oxide layer on the inner wall of the groove.
8. The method for fabricating a power semiconductor structure according to any one of claims 1 to 6, wherein the step of filling the oxide layer in the trench comprises:
and filling the oxide in the groove by adopting chemical vapor deposition equipment.
9. The method of fabricating a power semiconductor structure according to claim 8, wherein the chemical vapor deposition apparatus is adapted to perform oxide high density plasma chemical vapor deposition.
10. The method of fabricating a power semiconductor structure of any of claims 1-9, wherein the oxide is silicon dioxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202210701050.7A CN115064443A (en) | 2022-06-21 | 2022-06-21 | Manufacturing method of power semiconductor structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210701050.7A CN115064443A (en) | 2022-06-21 | 2022-06-21 | Manufacturing method of power semiconductor structure |
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Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5640034A (en) * | 1992-05-18 | 1997-06-17 | Texas Instruments Incorporated | Top-drain trench based resurf DMOS transistor structure |
| US20020125527A1 (en) * | 2000-03-01 | 2002-09-12 | Blanchard Richard A. | Trench DMOS transistor structure having a low resistance path to a drain contact located on an upper surface |
| US20070132016A1 (en) * | 2005-12-12 | 2007-06-14 | Elwin Matthew P | Trench ld structure |
| US20090294846A1 (en) * | 2008-05-28 | 2009-12-03 | Ptek Technology Co., Ltd. | Trench-type power mos transistor and integrated circuit utilizing the same |
| CN101840935A (en) * | 2010-05-17 | 2010-09-22 | 电子科技大学 | SOI (Silicon-on-insulator) MOSFET lateral (metal-oxide-semiconductor field effect transistor) device |
| CN104733531A (en) * | 2013-12-22 | 2015-06-24 | 万国半导体股份有限公司 | Dual oxide trench gate power mosfet using oxide filled trench |
| US20170092761A1 (en) * | 2015-09-29 | 2017-03-30 | Nxp B.V. | Semiconductor device |
| US20200135896A1 (en) * | 2018-10-26 | 2020-04-30 | Nxp Usa, Inc. | Transistor devices with extended drain regions located in trench sidewalls |
| CN111403472A (en) * | 2013-10-03 | 2020-07-10 | 德克萨斯仪器股份有限公司 | Trench gate trench field plate vertical MOSFET |
| US20210126125A1 (en) * | 2018-09-25 | 2021-04-29 | Nxp Usa, Inc. | Transistor devices with termination regions |
| CN114038914A (en) * | 2021-10-28 | 2022-02-11 | 江苏格瑞宝电子有限公司 | Double-withstand-voltage semiconductor power device and preparation method thereof |
| CN114038915A (en) * | 2021-10-28 | 2022-02-11 | 江苏格瑞宝电子有限公司 | Semiconductor power device and preparation method thereof |
-
2022
- 2022-06-21 CN CN202210701050.7A patent/CN115064443A/en active Pending
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5640034A (en) * | 1992-05-18 | 1997-06-17 | Texas Instruments Incorporated | Top-drain trench based resurf DMOS transistor structure |
| US20020125527A1 (en) * | 2000-03-01 | 2002-09-12 | Blanchard Richard A. | Trench DMOS transistor structure having a low resistance path to a drain contact located on an upper surface |
| US20070132016A1 (en) * | 2005-12-12 | 2007-06-14 | Elwin Matthew P | Trench ld structure |
| US20090294846A1 (en) * | 2008-05-28 | 2009-12-03 | Ptek Technology Co., Ltd. | Trench-type power mos transistor and integrated circuit utilizing the same |
| CN101840935A (en) * | 2010-05-17 | 2010-09-22 | 电子科技大学 | SOI (Silicon-on-insulator) MOSFET lateral (metal-oxide-semiconductor field effect transistor) device |
| CN111403472A (en) * | 2013-10-03 | 2020-07-10 | 德克萨斯仪器股份有限公司 | Trench gate trench field plate vertical MOSFET |
| CN104733531A (en) * | 2013-12-22 | 2015-06-24 | 万国半导体股份有限公司 | Dual oxide trench gate power mosfet using oxide filled trench |
| US20170092761A1 (en) * | 2015-09-29 | 2017-03-30 | Nxp B.V. | Semiconductor device |
| US20210126125A1 (en) * | 2018-09-25 | 2021-04-29 | Nxp Usa, Inc. | Transistor devices with termination regions |
| US20200135896A1 (en) * | 2018-10-26 | 2020-04-30 | Nxp Usa, Inc. | Transistor devices with extended drain regions located in trench sidewalls |
| CN114038914A (en) * | 2021-10-28 | 2022-02-11 | 江苏格瑞宝电子有限公司 | Double-withstand-voltage semiconductor power device and preparation method thereof |
| CN114038915A (en) * | 2021-10-28 | 2022-02-11 | 江苏格瑞宝电子有限公司 | Semiconductor power device and preparation method thereof |
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