CN115050727B - Wafer processor and circuit self-test and power supply management device used for same - Google Patents
Wafer processor and circuit self-test and power supply management device used for same Download PDFInfo
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Abstract
The invention discloses a wafer processor and a circuit self-test and power supply management device used for the wafer processor, which comprise a silicon substrate, wherein a wafer processing system is bonded on the silicon substrate, the top of the wafer processing system is connected with a power supply module through an elastic connector, the bottom of the wafer processing system is connected with the silicon substrate through a micro copper column, and a logic function circuit block is integrated in a mapping area corresponding to the wafer processing system in the silicon substrate through a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). According to the invention, the active circuit is designed in the silicon substrate of the wafer processor, and the BIST control unit in the silicon substrate realizes the testable function of the system after the Die of the wafer processor is bonded with the silicon substrate, so that the maintenance difficulty and cost of the wafer processor are reduced; and monitoring power supply faults and finely managing power supply faults of each wafer processor Die and each independent module inside the wafer processor Die, so that the influence on the normal work of other wafer processors Die or the functions of other modules of the wafer processor Die is avoided.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a wafer processor and a circuit self-test and power supply management device for the wafer processor.
Background
With the increasing demands of the fields of deep learning, large-scale data exchange and the like on the computing power of the processor, a single processor cannot meet all scenes for large-scale data processing. Therefore, wafer-level processors are proposed again with the advantages of extremely high interconnection bandwidth and power density, etc., and a super-large-scale processor cluster is realized by integrating a plurality of Known Good Die (Known qualified chips) on a complete large-size silicon substrate or similar high-speed medium through a bonding technology and interconnecting the Die with each other through a silicon substrate internal high-speed bus.
Built-in self-test (BIST) is widely used in the chip industry as an important test method for screening and screening Known Good Die, and the BIST technology only needs to apply necessary control signals from the outside during testing by adding some additional self-test circuits in the design of a chip, and detects defects or faults of a circuit to be tested by running built-in self-test hardware and software. The test vectors for built-in self-tests are typically generated internally rather than being input externally. Built-in self-test can simplify the testing steps and eliminate the need for expensive test equipment and equipment (e.g., ATE equipment), but it adds complexity to the chip design, thereby increasing the cost of the chip.
Currently, the BIST circuit is mainly used to test the individual wafer processors Die, for the wafer processor system, since the silicon substrate is used as a communication path between the wafer processors Die, large bandwidth and low delay communication are required between the wafer processors Die, a large number of high-speed parallel signal lines are designed in the silicon substrate for data interaction between the wafer processors Die, therefore, a large amount of communication bump needs to be bonded between the wafer processor Die and the silicon substrate, for the top powered wafer processor system, a large number of tiny copper pillars need to be grown on the silicon substrate and at the gaps between the wafer processors Die for the interaction of clock input, power input, reset input, debugging configuration, etc., in order to ensure the high density and small pitch of the wafer processors Die, the number of the copper columns is limited, and the number of the communication signal lines between the wafer processors Die is large and the speed is high, so that the communication signal lines cannot be led out through the copper columns, this presents an inconvenience to the testing of the bonded wafer handler system, where the tester cannot extract the communication interface signals of each wafer handler Die through the limited number of micro copper pillars around, and testing and evaluating the bonded wafer processor Die through an external test probe card, if the bonded wafer handler system is directly injection-molded without test, and if a failure (such as a short circuit between two bumps or poor bump contact) caused by bonding is found in subsequent tests, it is difficult to de-bond, repair and re-bond the faulty wafer handler Die in the injection molded wafer handler, therefore, it is necessary to design a BIST circuit after the wafer processor Die and the silicon substrate are integrally bonded, so as to improve the error coverage and reduce the dependence of the wafer processor test on the automatic test equipment.
At present, in order to improve the yield of a high-process-processing processor, the size of a wafer processor Die is generally small, and basically, for a high-performance wafer processor Die, the size of a voltage conversion module is generally difficult to be completely matched with that of each wafer processor Die, so for the wafer processor, a dicing power supply mode is generally adopted, that is, a power supply system is divided into a plurality of independent power supply units, and each power supply unit corresponds to a plurality of voltage domains to supply power to a plurality of wafer processors Die together. However, in the manner that one power supply unit supplies power to a plurality of wafer processors Die simultaneously, when any wafer processor Die draws a large current due to abnormal operation, the power supply unit stops operating due to overcurrent, and thus other wafer processors Die corresponding to the power supply unit also stop operating.
For the silicon substrate which undertakes communication connection between the wafer processors Die, besides designing a large number of metal interconnection lines inside to realize flexible communication between the wafer processors Die, a CMOS circuit can be designed to undertake partial logic functions, namely an active silicon substrate. The active silicon substrate is larger in size, the current mainstream size is 12 inches, and even if a mature process is used, the yield rate is difficult to reach 100%, so that the function of a part of circuits in the active silicon substrate fails.
Aiming at the problems of circuit self-test and power supply management of the wafer processor system, the invention provides the implementation of the BIST control unit, the current detection, the clock power supply control, the gate control switch and other circuits in the silicon substrate, and effectively solves the problems of self-test and refined power supply management of the wafer processor system.
Disclosure of Invention
The present invention is directed to solving the above-mentioned problems, and provides a wafer handler and a circuit self-test and power management apparatus for the wafer handler.
The technical scheme adopted by the invention is as follows:
a circuit self-test and power supply management device for a wafer processor comprises a silicon substrate, wherein a wafer processing system is bonded on the silicon substrate, the top of the wafer processing system is connected with a power supply module through an elastic connector, the bottom of the wafer processing system is connected with the silicon substrate through a micro copper column, and a logic function circuit block is integrated in a mapping area corresponding to the wafer processing system in the silicon substrate through a Metal Oxide Semiconductor Field Effect Transistor (MOSFET).
Furthermore, each wafer processor corresponds to two logic function circuit blocks, one logic function circuit block serves as a main circuit, the other logic function circuit block serves as a redundant circuit, each logic function circuit block leads out a global enabling pin through a metal connecting line in the silicon substrate and the micro copper column, and the global enabling pin is connected with the power supply module.
Furthermore, the wafer processing system comprises a plurality of wafer processors, the miniature copper columns are arranged at the gaps between the adjacent wafer processors, injection molding materials are filled in the gaps between the wafer processors and the miniature copper columns, the power supply module comprises a PCB carrier plate, and a voltage conversion circuit and a peripheral matching circuit which are arranged on the PCB carrier plate, and the PCB carrier plate is connected with the silicon substrate through the miniature copper columns.
Further, the logic function circuit block includes:
the BIST control unit is used for detecting circuit faults formed by the wafer processing system and the silicon substrate after bonding and before injection molding and detecting circuit faults inside the silicon substrate;
the current detection unit is used for converting a current induction value input by the wafer processing system and induced by the gating switch/current sensor unit into a current value and transmitting the current value to the clock power supply control unit;
the clock power supply control unit is used for setting a short-circuit current threshold value corresponding to each unit in the logic function circuit block, detecting whether the current value exceeds the short-circuit current threshold value or not and transmitting a detection result to the gate control switch/current sensor unit;
and the gate control switch/current sensor unit is used for sensing a current sensing value input by the wafer processing system, closing the global or local function of the wafer processing system when the clock power supply control unit detects that the current value exceeds the short-circuit current threshold value, and feeding back the closed logic function to the wafer processing system and the power supply module.
Further, the BIST control unit includes:
the test vector generator is used for generating test data and packaging to obtain a test vector, and sending the test vector to the tested circuit;
the output response analyzer is used for receiving, unpacking, comparing data and outputting a comparison result of the output data of the circuit to be tested;
and the self-test controller is used for controlling the opening and closing of the tested circuit, the feedback of the test result, the initial configuration of the test vector generator and the output response analyzer port.
Further, the method for detecting the circuit fault formed by the wafer processing system and the silicon substrate after bonding and before injection molding by the BIST control unit comprises the following steps:
the method comprises the following steps: the wafer test card sends the enabling signal to the BIST control unit through the metal connecting wire in the silicon substrate and the micro copper column, and transmits the enabling signal to a test vector generator in the BIST control unit and an output response analyzer in the BIST control unit through a self-test controller in the BIST control unit;
step two: the test vector generator generates a test vector and transmits the test vector to the wafer processing system by using a communication interface of the wafer processing system;
step three: and after the wafer processing system calculates the test vector, the calculation result is returned to the BIST control unit through a communication interface at the other end of the wafer processing system, the output result of the output response analyzer in the BIST control unit is compared with the actual output result, and the output feedback result is transmitted to the wafer test card through the metal connecting wire and the micro copper column in the silicon substrate.
Further, the method for detecting a circuit failure inside the silicon substrate by the BIST control unit includes the steps of:
step S1: the power supply module supplies power to the wafer processing system through the elastic connector and the miniature copper column, and the gate control switch/current sensor unit senses a current sensing value input by the wafer processing system;
step S2: the current detection unit converts the induction value into a current value and transmits the current value to the clock power supply control unit;
and step S3: the clock power supply control unit sets a short-circuit current threshold value corresponding to each unit in the logic function circuit block;
and step S4: the clock power supply control unit detects whether the current value exceeds the short-circuit current threshold value, if so, the global or local function of the wafer processing system is closed through the gate control switch/current sensor unit, and the closed logic function is fed back to the wafer processing system and the power supply module; if not, the clock power supply control unit continues to detect whether the current value exceeds the short-circuit current threshold value.
Further, the initial gate value of the MOSFET in the current detection unit is set to 1, and when the clock power control unit detects that the short-circuit current threshold is exceeded, the global or local function of the wafer processing system is turned off through the gate control switch/current sensor unit, and the gate of the MOSFET in the current detection unit is set to 0.
Further, the gate control switch/current sensor unit specifically includes: and connecting a metal-oxide-semiconductor field effect transistor (MOSFET) inside the silicon substrate in series to the clock power control unit to serve as a gate switch of the clock power control unit, using the temperature coefficient characteristic of the MOSFET inside the silicon substrate as a current detection sensor, and representing the magnitude of the channel current by using the resistance value and the voltage difference between two ends of the sensor.
The invention also provides a wafer processor which comprises a plurality of processor Dies which are bonded on a silicon substrate to form a high-performance computing cluster, wherein the silicon substrate comprises transistors and metal wires, the transistors are used for completing self-test and power management functions of the wafer processor by using any one of the circuit self-test and power supply management device for the wafer processor, and the metal wires are used for realizing high-speed interconnection among the processor Dies and providing a control path, a power supply path and an external communication connection channel.
The invention has the beneficial effects that: according to the invention, the active circuit is designed in the silicon substrate of the wafer processor, and the BIST control unit in the silicon substrate is used for realizing the testable function of the system after the Die of the wafer processor is bonded with the silicon substrate, so that the maintenance difficulty and cost of the wafer processor are reduced. The power failure monitoring and refined power supply failure management of each wafer processor Die and each internal independent module thereof are realized through a clock power supply control unit, a current detection unit and a gating switch/current sensor unit in the silicon substrate, so that when any wafer processor Die or internal independent module continuously draws large current due to failure, a power supply path can be timely cut off, and the influence on the normal work of other wafer processors Die or other module functions of the wafer processor Die is avoided. By designing the redundant circuits in the silicon substrate, the influence of internal active circuit faults caused by the problem of the manufacturing yield of the active silicon substrate on the power management and self-test functions of each wafer processor Die is avoided.
Drawings
FIG. 1 is a schematic diagram of an embodiment of a circuit self-test and power management apparatus for a wafer handler;
FIG. 2 is a partial top view of a circuit self-test and power management apparatus for a wafer handler of the present invention;
FIG. 3 is a schematic diagram of logic function circuit blocks corresponding to each Die of the wafer handler of the apparatus for self-test and power management of the wafer handler of the present invention;
FIG. 4 is a functional block diagram of a current sensing unit of an embodiment;
FIG. 5 is a functional block diagram of an embodiment BIST control unit.
Detailed Description
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1-3, a circuit self-test and power supply management device for a wafer processor comprises a silicon substrate, a wafer processing system is bonded on the silicon substrate, the top of the wafer processing system is connected with a power supply module through an elastic connector, the bottom of the wafer processing system is connected with the silicon substrate through a micro copper column, and a logic function circuit block is integrated in the silicon substrate corresponding to a mapping area of the wafer processing system through a Metal Oxide Semiconductor Field Effect Transistor (MOSFET).
Each wafer processor corresponds to two logic function circuit blocks, one logic function circuit block serves as a main circuit, the other logic function circuit block serves as a redundant circuit, each logic function circuit block leads out a global enabling pin through a metal connecting line in the silicon substrate and the micro copper column, and the global enabling pin is connected with the power supply module.
Because the area of the silicon substrate is large, even if a mature process is used, a small part of logic function circuit blocks still have defects in the production and manufacturing process, one of the two logic function circuit blocks is used as the redundancy of the other logic function circuit block, and the logic function circuit block can be closed when one logic function circuit block fails, and the redundancy circuit is used to ensure that the logic function circuit block corresponding to each wafer processor Die in the silicon substrate can normally work.
bump: grown on Die or silicon substrates for interconnection of Die or silicon substrates with the outside, typically by small spherical conductive materials such as copper-tin or gold bumps.
Because the internal circuit of the silicon substrate is simpler than that of the wafer processor Die, the mature process of 130nm and 180nm in a wafer foundry can be adopted, the yield of the active circuit in the silicon substrate is improved, and the production and manufacturing cost is reduced. Meanwhile, the mature MOSFET has larger size, has larger MOSFET current capacity than the advanced CMOS process (such as 7nm, 14nm, 22nm and the like), is favorable for using less MOSFETs to respectively control the power input passages of the Die of the wafer processor, and if the required current of the bump of a single processor is larger than the maximum current capacity of the MOSFETs, a plurality of MOSFETs are connected in parallel to increase the total current capacity.
The wafer processing system comprises a plurality of wafer processors, the miniature copper columns are arranged at the gaps between the adjacent wafer processors, injection molding materials are filled in the gaps between the wafer processors and the miniature copper columns, the power supply module comprises a PCB carrier plate, a voltage conversion circuit and a peripheral matching circuit, the voltage conversion circuit and the peripheral matching circuit are arranged on the PCB carrier plate, and the PCB carrier plate is connected with the silicon substrate through the miniature copper columns.
The power supply module (including the voltage conversion circuit and peripheral support circuits required by the wafer processor Die, such as the core voltage conversion circuit, the interface voltage conversion circuit, the clock circuit, the reset circuit, the download configuration circuit, the power supply management circuit, etc.) is located at the top of the wafer processor Die, the PCB carrier board carrying the voltage conversion circuit and the peripheral support circuits is connected with the silicon substrate through micro copper columns, the micro copper columns are located around each wafer processor Die and clamped in the gaps between the wafer processors Die, and the top view of the micro copper columns is shown in fig. 2.
As shown in fig. 3, each logic function circuit block internally includes a BIST control unit, a current detection unit, a clock power supply control unit, a gate switch/current sensor unit. The power input transmitted from the power supply module is simultaneously connected to two logic function circuit blocks through the micro copper column and the metal connecting wire in the silicon substrate, each logic function circuit block is provided with a global enabling pin and is led out through the metal connecting wire in the silicon substrate and the micro copper column, and the enabling and the closing of the logic function circuit blocks can be controlled on the power supply module.
And two identical logic function circuit blocks corresponding to each processor Die on the active silicon substrate, wherein one logic function circuit block is a main circuit, and the other logic function circuit block is a redundant circuit, and the enable or the close of the logic function circuit blocks is controlled by a power supply module and a switch circuit on a wafer test card. After the production of the silicon substrate is finished, before a non-bonded wafer processor Die, a wafer test needle card is used for firstly testing whether the function of a circuit in the silicon substrate is normal or not, screening out and marking a logic function circuit block with normal function, and then outputting an enabling signal on the bonded wafer processor test card and a corresponding power supply module to enable a signal of the marked normal logic function circuit block and close another logic function circuit block.
The logic function circuit block includes:
the BIST control unit is used for detecting circuit faults formed by the wafer processing system and the silicon substrate after bonding and before injection molding and detecting circuit faults inside the silicon substrate;
the current detection unit is used for converting a current induction value input by the wafer processing system and induced by the gating switch/current sensor unit into a current value and transmitting the current value to the clock power supply control unit;
and when the clock power supply control unit detects that the short-circuit current threshold value is exceeded, the gate control unit closes the global or local function of the wafer processing system and sets the gate of the MOSFET in the current detection unit to 0. The gate control switch/current sensor unit specifically comprises: connecting the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) inside the silicon substrate in series to the clock power supply control unit to serve as a gate switch of the clock power supply control unit, and enabling the temperature coefficient characteristic R of the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) inside the silicon substrate DS(ON) As a current detection sensor, the resistance value and the voltage difference between the two ends of the current detection sensor are used for representing the magnitude of the current of the channel.
When the wafer processing system normally works, when the clock power supply control unit detects that the short-circuit current threshold value is exceeded, the gate 1 of the metal-oxide-semiconductor field effect transistor (MOSFET) in the current detection unit closes the global or local function of the wafer processing system through the gate control switch/current sensor unit, and the gate of the metal-oxide-semiconductor field effect transistor (MOSFET) in the current detection unit is set to be 0.
The clock power supply control unit is used for setting a short-circuit current threshold value corresponding to each unit in the logic function circuit block, detecting whether the current value exceeds the short-circuit current threshold value or not and transmitting a detection result to the gate control switch/current sensor unit;
the software of the wafer processor system will adjust the allocation of either computational tasks or communication tasks at the system level. If the current of an independent module of the wafer processor Die is monitored to be abnormal (such as a communication interface of a bank and a processor core of a multi-core processor), the module is closed without affecting the operation and processing of other modules in the wafer processor Die, that is, other modules of the wafer processor Die can bypass a fault module and still can undertake partial operation or communication tasks, the clock power supply control unit only closes the power supply and the clock of the fault module of the wafer processor Die, and if the current of the global function module of a wafer processor Die is monitored to be abnormal, all the power supplies and clocks of the wafer processor Die can only be closed, and the normal operation of other wafer processors Die in the plurality of wafer processors Die powered by the power supply unit is not affected.
The gate control switch/current sensor unit is used for sensing a current sensing value input by the wafer processing system and closing the global or local function of the wafer processing system when the clock power supply control unit detects that the current value exceeds the short-circuit current threshold value, and feeding back the closed logic function to the wafer processing system and the power supply module;
the gate control switch/current sensor unit is realized by using a MOSFET (metal oxide semiconductor field effect transistor) in a silicon substrate, a voltage input and a clock input corresponding to each voltage bump of the wafer processor Die are connected by using a source electrode and a drain electrode of the MOSFET, and the gate electrode is used for carrying out switch control on the voltage input and the clock input. While the gate-controlled switch/current sensor unit uses R of MOSFET DS（ON） I.e. the on-resistance of the source and drain of the MOSFET. At present, the current detection method is commonly used to serially detect the resistance in the voltage transmission path, but because the current detection resistance is increased,the resistor generates additional power consumption, which reduces the power supply efficiency of the wafer processor with low voltage and large current. According to the invention, the inherent characteristics of the MOSFET serving as the gating switch in the silicon substrate are utilized, and the on-resistances of the source and the drain are used as the current detection sensor, so that the extra power consumption generated by the current detection circuit can be reduced, and the design and manufacturing cost of the silicon substrate is also reduced. Further, R using MOSFET DS（ON） The method is not suitable for precise current detection, and the invention mainly uses R DS（ON） The method is used for detecting the large current possibly generated by bump short circuit in the bonding process of the Die and the silicon wafer of the wafer processor, and the large short circuit current is far larger than the current in normal operation, so that the threshold current can be set to a value which is greatly different from the normal operation current in the current detection unit, and R is offset DS（ON） The effect of accuracy.
The BIST control unit is responsible for detecting whether the functions of a circuit formed by the wafer processor Die and the silicon substrate after bonding and before injection molding are normal or not, and finding out circuit faults in time so as to conveniently perform debonding, repairing and rebonding on the wafer processor Die before injection molding and reduce the repairing difficulty.
The BIST control unit includes:
the test vector generator is used for generating test data and packaging to obtain a test vector, and sending the test vector to the tested circuit;
the output response analyzer is used for receiving, unpacking, comparing data and outputting a comparison result of the output data of the circuit to be tested;
and the self-test controller is used for controlling the opening and closing of the circuit to be tested, the feedback of the test result, the initial configuration of the test vector generator and the output response analyzer port.
The BIST control unit is located in the silicon substrate and is mainly responsible for testing the corresponding wafer processor Die, and meanwhile, for the isomorphic wafer processors, the BIST control unit corresponding to the four wafer processors Die adjacent to each wafer processor Die can also intensively test the central wafer processor Die more comprehensively. During testing, a wafer test card is used for transmitting a clock and a control signal to a BIST control unit through a metal connecting wire in a micro copper column and a silicon substrate, then the BIST control unit starts working to generate a test vector, the test vector is input to a wafer processor Die through a communication interface of the wafer processor Die, after the wafer processor Die finishes operation, an operation result is returned to the BIST control unit through a communication interface at the other end of the wafer processor Die, the BIST control unit compares an expected output result of the input vector with an actual output result, finally the test result is fed back to the wafer test card through the metal connecting wire in the silicon substrate and the micro copper column, and a tester determines whether to repair the wafer processor or not through a feedback result received in the wafer test card.
The method for detecting the circuit fault formed by the wafer processing system and the silicon substrate after bonding and before injection molding by the BIST control unit comprises the following steps:
the method comprises the following steps: the wafer test card sends the enabling signal to the BIST control unit through the metal connecting wire in the silicon substrate and the micro copper column, and transmits the enabling signal to a test vector generator in the BIST control unit and an output response analyzer in the BIST control unit through a self-test controller in the BIST control unit;
step two: the test vector generator generates a test vector and transmits the test vector to the wafer processing system by using a communication interface of the wafer processing system;
step three: and after the wafer processing system calculates the test vector, the calculation result is returned to the BIST control unit through a communication interface at the other end of the wafer processing system, the output result of the output response analyzer in the BIST control unit is compared with the actual output result, and the output feedback result is transmitted to the wafer test card through the metal connecting wire and the micro copper column in the silicon substrate.
The self-test controller comprises enabling control, feedback output, port number PROT address configuration, IP address configuration, MAC address configuration, an initial value of a PRBS31 and a source polynomial logic function, is used for starting and closing control, test result feedback, test vector generator and initial configuration of an output response analyzer port of the BIST control unit, and is externally connected with a wafer test card through a bonding pad on the silicon substrate;
the test vector generator comprises an application layer PRBS31, a transmission layer UDP, a network layer IP and a 10G Ethernet link layer MAC, and an ARP logic composition, and is used for generating, packaging and sending test vectors, the application layer PRBS31 is used for generating pseudo-random data as the original data of the 10G Ethernet link layer MAC and ARP test vectors, the transmission layer UDP and the network layer IP contain UDP and IP protocol package unpacking function logic, and the 10G Ethernet link layer MAC, and the ARP logic mainly comprises an Ethernet MAC controller, an ARP logic and an Ethernet PHY;
the output response analyzer comprises an application layer PRBS31, a transmission layer UDP, a network layer IP, a 10G Ethernet link layer MAC, an ARP logic, a timer, a counter and a data comparison analysis logic, and is used for receiving, unpacking, comparing data, outputting a comparison result and the like of a test vector, wherein the PRBS31 generator, the UDP/IP protocol stack and the 10G Ethernet link layer MAC are the same as those in the test vector generator, the timer and the counter count the transmission time and the packet loss number of the test vector, and when a set threshold value is exceeded, an abnormal condition is determined and an abnormal result is output.
The BIST control unit is used for detecting whether the functions of a circuit formed by the wafer processor Die and the silicon substrate after bonding and before injection molding are normal or not, and also is used for detecting whether the internal circuit of the silicon substrate is normal or not after the silicon substrate is produced, and the BIST control unit comprises a BIST control unit, a clock power supply control unit, a current detection unit and a gate switch/current sensor unit.
The method for detecting the circuit fault inside the silicon substrate by the BIST control unit comprises the following steps:
step S1: the power supply module supplies power to the wafer processing system through the elastic connector and the miniature copper column, and the gate control switch/current sensor unit senses a current sensing value input by the wafer processing system;
step S2: the current detection unit converts the induction value into a current value and transmits the current value to the clock power supply control unit;
and step S3: the clock power supply control unit sets a short-circuit current threshold value corresponding to each unit in the logic function circuit block;
and step S4: the clock power supply control unit detects whether the current value exceeds the short-circuit current threshold value, if so, the global or local function of the wafer processing system is closed through the gate control switch/current sensor unit, and the closed logic function is fed back to the wafer processing system and the power supply module; if not, the clock power supply control unit continues to detect whether the current value exceeds the short-circuit current threshold value.
The embodiment is as follows: a circuit self-test and power supply management device for a wafer processor is characterized in that a 12-inch active silicon substrate is used as a substrate of the whole wafer processor system, the thickness of the silicon substrate is about 500 mu m, a 180nm process technology international to a central core is adopted, a heat dissipation area is arranged below the active silicon substrate and is tightly attached to a water-cooling heat sink, 15 × 15 wafer processors Die are bonded on the upper surface of the active silicon substrate, the total number of the 225 wafer processors Die is 15 × 15, the size of each wafer processor Die is 12 × 12mm, the wafer processor Die is a 320Gbps Ethernet data exchange processor, two voltage domains are arranged inside the wafer processor system and are divided into a core voltage domain and an interface voltage domain, the average current of each bump in the core voltage domain is 100mA, and the average current of each bump in the interface voltage domain is 200mA, each wafer processor Die has 32 ports in total, each port is 10Gbps, the distance between the wafer processors Die is 500um, each port uses 64 data lines and corresponding clocks and control lines to form a communication channel with the speed of 10Gbps, the whole wafer processing system has 25 independent power supply modules for supplying power to the wafer processing system, each power supply module is responsible for 3X 3 and 9 wafer processors Die in total and peripheral matching circuits, the power supply module is positioned above the wafer processors Die, the periphery of each wafer processor Die is surrounded by a circle of micro copper columns, and the PCB carrier plate is responsible for connecting the silicon substrate and the power supply modules, the diameter of each micro copper column is 100um, and the diameter height ratio is 1:1, the distances between the micro copper columns and the wafer processor Die are both 100um. In the active silicon substrate, each wafer processor Die comprises two sets of same logic function circuit blocks in a vertical projection area, wherein one set of the same logic function circuit blocks is a main logic function circuit block, and the other set of the same logic function circuit blocks is a redundant logic function circuit block.
The logic function circuit block comprises a BIST control unit, a clock power supply control unit, a current detection unit and a gating switch/current sensor unit.
The BIST control unit, as shown in fig. 5, uses an application layer PRBS31, a transport layer UDP, a network layer IP and a 10G ethernet link layer MAC, and an ARP logic to form a test vector generator, which is responsible for generating, packaging and sending test data, the application layer PRBS31 is configured to generate pseudo random data as raw data of the 10G ethernet link layer MAC and the ARP test vector, the transport layer UDP and the network layer IP contain UDP and IP protocol packet unpacking function logic, and the 10G ethernet link layer MAC, and the ARP logic mainly includes an ethernet MAC controller, an ARP logic and an ethernet PHY; an application layer PRBS31, a transmission layer UDP, a network layer IP, a 10G Ethernet link layer MAC, an ARP logic, a timer, a counter and a data comparison analysis logic are used for forming an output response analyzer which is responsible for receiving, unpacking, data comparison, outputting comparison results and the like of test messages, wherein the PRBS31 generator, the UDP/IP protocol stack and the 10G Ethernet link layer MAC are the same as those in the test vector generator, the timer and the counter count the transmission time and the packet loss number of the test vectors, and when the transmission time and the packet loss number of the test vectors exceed a set threshold value, the abnormal results are judged and output. The built-in self-test controller consists of enabling control, feedback output, port number PROT address configuration, IP address configuration, MAC address configuration, an initial value of a PRBS31 and a source polynomial logic function, is responsible for starting and closing control, test result feedback, initial configuration of a test vector generator and an output response analyzer port of the BIST control unit, and is connected with a wafer test card through a bonding pad on the silicon substrate;
when the BIST control unit is used for testing, a wafer test card is used for providing a stable power supply and a clock for a wafer processor, firstly, the wafer test card sends an enabling signal to enable the BIST control unit, a built-in self-test controller in the BIST control unit sends two sets of different PORT number PROT addresses, an IP address configuration, an MAC address configuration, a set of common initial values of a PRBS31 and a source polynomial logic function to a test vector generator and an output response analyzer, the destination PORT address and the IP address of the test vector generator and the output response analyzer are the source PORT address and the IP address of the opposite party, then the PRBS31 generator in the test vector generator generates ten thousand of pseudo random data, the pseudo random data are packaged into an Ethernet data packet through a transmission layer UDP and a network layer IP protocol stack and then sent to a wafer processor Die to be tested through a link layer at a bandwidth of 10 percent, the method comprises the steps that a tested wafer processor Die sends an Ethernet data packet to a corresponding PORT according to a destination IP address and an MAC address in a message, an output response analyzer receives the data transmitted from the PORT of the tested wafer processor Die, unpacks the data to obtain the data in the message, compares the data with the data obtained by a PRBS31 generator in the output response analyzer, if the comparison result is wrong, a feedback signal is set to be 1, otherwise, the feedback signal is set to be 0, the data is fed back to a wafer test card through a test probe, in addition, a timer and a counter in the output response analyzer start to work when a test vector generator sends the message, if the output response analyzer still does not receive any message after 2 seconds, the feedback signal is set to be 1, the counter counts the number of the received data to be less than ten thousand, the feedback signal is set to be 1, and otherwise, the feedback signal is set to be 0.
The clock power supply control unit respectively sets abnormal thresholds for different voltage domains, sets a short-circuit threshold of 300mA for 100mA current of each bump processed by a core, sets a short-circuit threshold of 600mA for 200mA current of each bump communicated by an interface, and when the numerical value transmitted by the current detection unit exceeds the threshold, the current is considered as a short-circuit current, and a gated switch/current sensor unit is used for disconnecting the power supply with the corresponding function from the clock and outputting a corresponding feedback code to the wafer test card.
As shown in fig. 4, Q1 of the current detection unit is a MOSFET tube, V1 and V2 are voltages of a source and a drain of the MOSFET, a load is a transistor set corresponding to a power supply bump of the connected wafer processor Die, I is a current for supplying power to one of the bumps of the wafer processor Die through the source and the drain of the MOSFET, and R1 and R2 are voltage dividing resistors because
The value of current I flowing through the MOSFET is the ratio of the voltage difference of a source electrode and a drain electrode to the on-resistance:
the calculation formula for obtaining the current value I in the current detection unit by combining the two formulas is as follows:
therefore, the current detection unit measures the output VOUT of the operational amplifier and the known constants R1, R2 and R DS(ON) And calculating the current value flowing through each MOSFET tube by using three parameters.
N-type MOSFET tubes with a central core international 180nm process are connected in series in a silicon substrate to connect a Die of a wafer processor in the silicon substrate and a clock and power supply connecting line of an external Pad (a power supply path and a clock path), the power supply and the clock are gated, when the silicon substrate works normally, a grid electrode of the MOSFET tube is set to be 1, and if a clock power supply control unit detects overcurrent abnormity, the grid electrodes of all the clocks and power supply gated MOSFET tubes with corresponding functions are set to be 0.
A wafer processor comprises a plurality of processor Dies which are bonded on a silicon substrate to form a high-performance computing cluster, wherein the silicon substrate comprises transistors and metal wires, the transistors are used for completing the self-test and power management functions of the wafer processor by using a circuit self-test and power management device for the wafer processor, which is described in any one of the above, and the metal wires are used for realizing high-speed interconnection among the processor Dies and providing a control path, a power supply path and an external communication connection path.
In summary, in the embodiment, a circuit self-test and power supply management device for a wafer processor is designed on an active silicon substrate of the wafer processor, so that fine management of power supply of the wafer processor is realized, and the abnormal function of any one Die or module of the wafer processor does not affect the normal operation of other Die or modules of the wafer processor.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. The circuit self-test and power supply management device for the wafer processor is characterized by comprising a silicon substrate, wherein a wafer processing system is bonded on the silicon substrate, the top of the wafer processing system is connected with a power supply module through an elastic connector, the bottom of the wafer processing system is connected with the silicon substrate through a micro copper column, and a logic function circuit block is integrated in a mapping area, corresponding to the wafer processing system, in the silicon substrate through a Metal Oxide Semiconductor Field Effect Transistor (MOSFET);
the logic function circuit block includes:
the BIST control unit is used for detecting circuit faults formed by the wafer processing system and the silicon substrate after bonding and before injection molding and detecting circuit faults inside the silicon substrate;
the current detection unit is used for converting a current induction value input by the wafer processing system induced by the gating switch/current sensor unit into a current value and transmitting the current value to the clock power supply control unit;
the clock power supply control unit is used for setting a short-circuit current threshold value corresponding to each unit in the logic function circuit block, detecting whether the current value exceeds the short-circuit current threshold value or not and transmitting a detection result to the gate control switch/current sensor unit;
and the gating switch/current sensor unit is used for sensing a current sensing value input by the wafer processing system and closing the global or local function of the wafer processing system when the clock power supply control unit detects that the current value exceeds the short-circuit current threshold value, and feeding back the closed logic function to the wafer processing system and the power supply module.
2. The apparatus of claim 1, wherein each of said wafer processors is associated with two of said logic function blocks, one of said logic function blocks being a main circuit and the other of said logic function blocks being a redundant circuit, each of said logic function blocks having a global enable pin routed through a metal interconnect in said silicon substrate and said micro copper pillar, said global enable pin being connected to said power module.
3. The apparatus of claim 1, wherein the wafer processing system comprises a plurality of wafer handlers, the micro copper pillars are disposed adjacent to gaps of the wafer handlers, gaps between the wafer handlers and the micro copper pillars are filled with injection molding material, the power supply module comprises a PCB carrier and a voltage conversion circuit and peripheral support circuits disposed on the PCB carrier, and the PCB carrier is connected to the silicon substrate through the micro copper pillars.
4. A circuit self-test and power management arrangement for a wafer processor as claimed in claim 1 wherein said BIST control unit comprises:
the test vector generator is used for generating and packaging test data to obtain a test vector and sending the test vector to the tested circuit;
the output response analyzer is used for receiving, unpacking, comparing data and outputting a comparison result of the output data of the tested circuit;
and the self-test controller is used for controlling the opening and closing of the tested circuit, the feedback of the test result, the initial configuration of the test vector generator and the output response analyzer port.
5. The apparatus of claim 4, wherein the BIST control unit is configured to detect a failure of a circuit formed by the wafer processing system and the silicon substrate after bonding and before injection molding, the method comprising:
the method comprises the following steps: the wafer test card sends the enable signal to the BIST control unit through the metal connecting wire and the micro copper column in the silicon substrate, and transmits the enable signal to the test vector generator in the BIST control unit and the output response analyzer in the BIST control unit through the self-test controller in the BIST control unit;
step two: the test vector generator generates a test vector and transmits the test vector to the wafer processing system by using a communication interface of the wafer processing system;
step three: and after the wafer processing system calculates the test vector, the calculation result is returned to the BIST control unit through a communication interface at the other end of the wafer processing system, the output result of the output response analyzer in the BIST control unit is compared with the actual output result, and the output feedback result is transmitted to the wafer test card through the metal connecting wire and the micro copper column in the silicon substrate.
6. A circuit self-test and power management arrangement for a wafer processor as claimed in claim 1 wherein the method of the BIST control unit for detecting circuit faults inside the silicon substrate comprises the steps of:
step S1: the power supply module supplies power to the wafer processing system through the elastic connector and the miniature copper column, and the gate control switch/current sensor unit senses a current sensing value input by the wafer processing system;
step S2: the current detection unit converts the induction value into a current value and transmits the current value to the clock power supply control unit;
and step S3: the clock power supply control unit sets short-circuit current threshold values corresponding to all units in the logic function circuit block;
and step S4: the clock power supply control unit detects whether the current value exceeds the short-circuit current threshold value, if so, the global or local function of the wafer processing system is closed through the gate control switch/current sensor unit, and the closed logic function is fed back to the wafer processing system and the power supply module; if not, the clock power supply control unit continues to detect whether the current value exceeds the short-circuit current threshold value.
7. The apparatus of claim 1, wherein the initial gate of the MOSFET in the current detection unit is set to 1, and when the clock power control unit detects that the short-circuit current threshold is exceeded, the gate switch/current sensor unit turns off the global or local function of the wafer processing system and sets the gate of the MOSFET in the current detection unit to 0.
8. The apparatus of claim 1, wherein the gated switch/current sensor unit is specifically configured to: and connecting the metal-oxide-semiconductor field effect transistor (MOSFET) inside the silicon substrate in series to the clock power supply control unit to serve as a gate switch of the clock power supply control unit, using the temperature coefficient characteristic of the metal-oxide-semiconductor field effect transistor (MOSFET) inside the silicon substrate as a current detection sensor, and representing the magnitude of the channel current by using the resistance value and the voltage difference between two ends of the current detection sensor.
9. A wafer processor, characterized in that, the wafer processor comprises a plurality of processors Die bonded on a silicon substrate to form a high performance computing cluster, the silicon substrate comprises transistors and metal wires, the transistors are used for completing self-test and power management functions of the wafer processor by using a circuit self-test and power management device for the wafer processor as claimed in any one of claims 1 to 8, the metal wires realize high speed interconnection among the processors Die and provide control path, power supply path and external communication connection channel.
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| CN115237036B (en) * | 2022-09-22 | 2023-01-10 | 之江实验室 | Full-digitalization management device for wafer-level processor system |
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