CN114979593A - Video display driving system based on novel high-speed 4K digital micromirror chip - Google Patents
Video display driving system based on novel high-speed 4K digital micromirror chip Download PDFInfo
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- H04N9/12—Picture reproducers
- H04N9/31—Projection devices for colour picture display, e.g. using electronic spatial light modulators [ESLM]
- H04N9/3141—Constructional details thereof
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- H04N9/00—Details of colour television systems
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Abstract
The invention discloses a video display driving system based on a novel high-speed 4K digital micromirror chip, which comprises an FPGA (field programmable gate array) ZYNQ subsystem, an MCU (microprogrammed control Unit) singlechip module, a power supply module, a daughter board module, a three-color laser module, a video input module, a galvanometer module, a USB (universal serial bus) concentrator module, a fan module and a diffusion wheel module. The invention is compatible with various video input modes, digital micromirror chip (DMD) drive with various data rates, can realize digital micromirror chip drive with the highest data rate of 3.2Gbps, and can be used in a plurality of fields such as environment simulation, face recognition, home theater, large-scale exhibition hall projection, digital advertisement projection and the like. The invention has the advantages of small volume, complete functions, excellent performance, strong developability and the like, and can bring high-quality video viewing experience to users.
Description
Technical Field
The invention relates to a video display and digital micromirror chip driving technology, in particular to a video display driving system based on a novel high-speed 4K digital micromirror chip, which is used as a digital micromirror chip video display driving platform and can drive ultra-high definition dynamic video with the highest display data rate of 3.2Gbps and the highest display resolution of 3840 x 2160.
Background
With the gradual improvement of the life quality of people, the requirements of people on visual experience are also gradually improved. While projection is the only display technology that proves to offer 4K large image sizes at a reasonable price, as in the day.
The DLP projection technology is the mainstream technology used by the projection equipment at present, the projection equipment in the market is realized by the technology, and the DLP projector occupies 91.9% of the projection market at present and occupies the market dominance. The digital micromirror chip (DMD) is used as the core technology of Digital Light Processing (DLP) technology, and is locked by a certain company in a certain country and monopolized by a single family, and the projection driving display platform is limited by the core technology of the company, so that the digital micromirror chip (DMD) and the driving field thereof in China are slowly developed.
Disclosure of Invention
The invention aims to provide a video display driving system based on a novel high-speed 4K digital micromirror chip, aiming at the defects of the video projection driving technology of the conventional novel high-speed 4K ultra-high-definition digital micromirror chip, and the video display driving system adopts an FPGA ZYNQ subsystem, an MCU singlechip module, a power supply module, a daughter board module, a three-color laser module, a video input module, a galvanometer module, a USB concentrator module, a fan module and a diffusion wheel module, and carries out platform development aiming at the design of the driving chip of the novel high-speed 4K ultra-high-definition digital micromirror chip (DMD) and the display projection of real-time video data.
The invention can meet the high requirement of the verification of a novel high-speed 4K digital micromirror drive chip on one hand, and is suitable for the intelligent development of a 4K ultra-high definition resolution projection market on the other hand. The system adopts ZYNQ series FPGA of Xilinx company as a core processor, is provided with peripherals such as PL DDR4, PS DDR4, SATA, FLASH and the like, and performs data interaction with external connections through interfaces such as LVDS interfaces, GTH interfaces, communication interfaces, USB3.0, UART and the like. The invention can be compatible with various video input modes, including HDMI interface and V-by-One interface; the invention is compatible with digital micromirror chip drivers with various data rates, can realize the digital micromirror chip driver with the data rate of 1.6Gbps through the LVDS interface, and can realize the digital micromirror chip driver with the data rate of 3.2Gbps at most through the GTH interface. The invention can be used in a plurality of fields such as environment simulation, face recognition, home theater, large exhibition hall projection, digital advertisement projection and the like. The invention has the advantages of small volume, complete functions, excellent performance, strong developability and the like, and can bring high-quality video viewing experience to users.
The specific technical scheme for realizing the purpose of the invention is as follows:
a video display driving system based on a novel high-speed 4K digital micromirror chip comprises an FPGA (field programmable gate array) ZYNQ subsystem, an MCU (microprogrammed control Unit) singlechip module, a power module, a daughter board module, a three-color laser module, a video input module, a vibrating mirror module, a USB (Universal Serial bus) concentrator module, a fan module and a diffusion wheel module, wherein the FPGA ZYNQ subsystem is respectively connected with the MCU singlechip module, the power module, the daughter board module, the three-color laser module, the video input module, the vibrating mirror module and the USB concentrator module; the MCU singlechip module is connected with the FPGA ZYNQ subsystem, the video input module, the USB concentrator module, the fan module and the diffusion wheel module; the power supply module is connected with the FPGA ZYNQ subsystem, the MCU singlechip module, the daughter board module, the three-color laser module, the video input module, the galvanometer module, the USB concentrator module, the fan module and the diffusion wheel module; the video input module is connected with the FPGA ZYNQ subsystem, the MCU singlechip module and the USB concentrator module; wherein:
the FPGA ZYNQ subsystem comprises a ZYNQ chip, a 2GB 64-bit DDR4 memory, a 1GB 32-bit DDR4 memory, a daughter board LVDS interface, a daughter board GTH interface, an SATA module, a FLASH module, an SD card module, a USB UART module, a USB3.0 module and a communication interface; the ZYNQ chip is respectively connected with a 2GB 64-bit DDR4 memory, a 1GB 32-bit DDR4 memory, a daughter board LVDS interface, a daughter board GTH interface, an SATA module, a FLASH module, an SD card module, a USB UART module, a USB3.0 module, a USB2.0 module and a communication interface;
the daughter board module comprises a daughter board and a DMD chip, and the DMD chip is connected to the daughter board through a chip base; the daughter board is connected to a daughter board LVDS interface or a daughter board GTH interface in the FPGA ZYNQ subsystem through an LVDS interface;
the three-color laser module comprises a red laser driving module, a green laser driving module, a blue laser driving module and a light supplementing driving module; the red laser driving module, the green laser driving module, the blue laser driving module and the light supplementing driving module are respectively connected with a ZYNQ chip in the FPGA ZYNQ subsystem;
the video input module consists of an HDMI input interface, a video transceiving chip GSV2011 and a V-by-One input interface, wherein the HDMI input interface is connected with the video transceiving chip GSV2011, and the video transceiving chip GSV2011 is connected with a ZYNQ chip in the FPGA ZYNQ subsystem; the V-by-One input interface is connected with a ZYNQ chip, an MCU single chip module and a USB concentrator module in the FPGA ZYNQ subsystem;
the galvanometer module comprises a first direction galvanometer driving module and a second direction galvanometer driving module; the first direction galvanometer driving module and the second direction galvanometer driving module are respectively connected with a ZYNQ chip in the FPGA ZYNQ subsystem;
the fan module comprises a first fan driving module, a second fan driving module, a third fan driving module, a fourth fan driving module, a fifth fan driving module, a sixth fan driving module and a seventh fan driving module, and each fan driving module corresponds to one fan interface; the first fan driving module, the second fan driving module, the third fan driving module, the fourth fan driving module, the fifth fan driving module, the sixth fan driving module and the seventh fan driving module are respectively connected with the MCU singlechip module.
The daughter board LVDS interface module consists of a daughter board LVDS interface and 18 direct-current level conversion modules; the specific circuit of the direct current level conversion module is composed of a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C1 and a capacitor C2, one end and the other end of the resistor R1 are respectively connected with a ZYNQ chip in the FPGA ZYNQ subsystem, one end of the resistor R2 is connected with a power supply, the other end of the resistor R3 is connected with the ground, one end of the resistor R4 is connected with the power supply, the other end of the resistor R5 is connected with the ground, the other end of the resistor R5 is connected with the resistor R1, the other end of the capacitor C1 is connected with the resistor R2 and one end of the differential signal in the daughter board LVDS interface, one end of the capacitor C2 is connected with the resistor R1, and the other end of the capacitor R4 is connected with the other end of the differential signal in the daughter board LVDS interface.
The invention has the following advantages:
1) the invention is provided with a path of HDMI input interface, a V-by-One interface, a four-path laser control interface, a diffusion wheel interface, a vibrating mirror interface, a seven-path fan interface, a USB-UART interface, an SATA interface, a USB3.0 interface and a multi-path communication interface. The interface is abundant and perfect, meet the demand that the video reveals the drive, and the invention is small, with low costs.
2) The digital micromirror chip video display driving platform provided by the invention can be compatible with digital micromirror chip drives with various data rates, and can support the digital micromirror chip drive with the highest data rate of 3.2 Gbps.
4) The invention supports the input of the video data of V-by-One while supporting the input of the video data of HDMI ultra-high definition resolution 4K @60 Hz. And a plurality of video access modes can be provided for users.
5) The invention can realize various front-end video processing algorithms including image sharpening, brightness contrast adjustment, color gamut adjustment, gamma correction, OSD superposition, trapezoidal correction, split-screen display and the like while displaying a real-time image with ultrahigh definition resolution, and can provide various video sensory experiences for users.
6) The platform is based on an independently designed high-speed printed circuit board, and the FPGA program, the C language and the C + + language are developed by an inventor team without any finished product module. The hardware system adopts a 16-layer laminated design, ensures Signal Integrity (SI), Power Integrity (PI) and electromagnetic compatibility (EMI) through simulation calculation, and has stable platform work and good performance.
Drawings
FIG. 1 is a block diagram of the system of the present invention;
FIG. 2 is a circuit block diagram of a ZYNQ subsystem of the FPGA programmable gate array of the present invention;
FIG. 3 is a block diagram of a daughter board module circuit in accordance with the present invention;
FIG. 4 is a circuit block diagram of a three-color laser module according to the present invention;
FIG. 5 is a block diagram of a video input module according to the present invention;
FIG. 6 is a block diagram of the galvanometer module of the present invention;
FIG. 7 is a circuit block diagram of a fan module according to the present invention;
FIG. 8 is a block diagram of a daughter board LVDS interface module according to the present invention;
FIG. 9 is a block diagram of a DC level shift module according to the present invention;
fig. 10 is a circuit block diagram of embodiment 1 of the present invention.
Detailed Description
Referring to fig. 1, the video display driving system based on the novel high-speed 4K digital micromirror chip of the present invention specifically includes:
the system comprises an FPGA (field programmable gate array) ZYNQ subsystem 1, an MCU (microprogrammed control Unit) singlechip module 2, a power supply module 3, a daughter board module 4, a three-color laser module 5, a video input module 6, a galvanometer module 7, a USB (universal serial bus) concentrator module 8, a fan module 9 and a diffusion wheel module 10, wherein the FPGA ZYNQ subsystem 1 is respectively connected with the MCU singlechip module 2, the power supply module 3, the daughter board module 4, the three-color laser module 5, the video input module 6, the galvanometer module 7 and the USB concentrator module 8; the MCU singlechip module 2 is connected with the FPGA ZYNQ subsystem 1, the video input module 6, the USB concentrator module 8, the fan module 9 and the diffusion wheel module 10; the power supply module 3 supplies power to the FPGA ZYNQ subsystem 1, the MCU singlechip module 2, the daughter board module 4, the three-color laser module 5, the video input module 6, the galvanometer module 7, the USB concentrator module 8, the fan module 9 and the diffusion wheel module 10; the video input module 6 is connected with the FPGA ZYNQ subsystem 1, the MCU singlechip module 2 and the USB concentrator module 8.
The MCU singlechip module 2 adopts an MSP430F5525IRGC type singlechip, is used for driving the fan module 9 and the diffusion wheel module 10, and communicates with the V-by-One input interface 63 and the USB hub module 8 in the video input module 6. The power module 3 has 22 power chips for supplying 61 power supplies and 20 different voltages. The USB concentrator module 8 adopts an FE1.1 chip, supports One path of USB differential signal input and simultaneously outputs four paths of same USB differential signals, in the invention, the USB differential signal input of the FE1.1 comes from a V-by-One input interface 63 in the video input module 6, One path of USB differential signal of the FE1.1 is output to a USB2.0 module 111 in the FPGA ZYNQ subsystem 1, and the other path of USB differential signal is output to the MCU singlechip module 2.
Referring to fig. 2, the FPGA programmable gate array ZYNQ subsystem 1 includes a ZYNQ chip 11, a 2GB 64-bit DDR4 memory 12, a 1GB 32-bit DDR4 memory 13, a daughter board LVDS interface 14, a daughter board GTH interface 15, an SATA module 16, a FLASH module 17, an SD card module 18, a USB UART module 19, a USB3.0 module 110, a USB2.0 module 111, and a communication interface 112; the ZYNQ chip 11 is respectively connected with a 2GB 64-bit DDR4 memory 12, a 1GB 32-bit DDR4 memory 13, a daughter board LVDS interface 14, a daughter board GTH interface 15, a SATA module 16, a FLASH module 17, an SD card module 18, a USB UART module 19, a USB3.0 module 110, a USB2.0 module 111 and a communication interface 112; wherein the ZYNQ chip 11 adopts XCZU7EV-FFVC1156E type FPGA; the data rate of the 2GB 64bit DDR4 memory 12 can reach 2666MT/s, and the memory is used for storing input video data subjected to front-end video processing; the data rate of the 1GB 32bit DDR4 memory 13 can reach 2400MT/s, and the data rate is used for storing resources required by starting the ZYNQ chip 11; the daughter board LVDS interface 14 supports the DMD chip 42 in the daughter board module 4 at the highest data rate of 1.6Gbps, and the daughter board GTH interface 15 supports the DMD chip 42 in the daughter board module 4 at the highest data rate of 3.2 Gbps; the communication interface 112 includes three protocol interfaces of SPI, IIC, and UART, for performing communication interaction with the outside.
Referring to fig. 3, the daughter board module 4 includes a daughter board 41 and a DMD chip 42, and the DMD chip 42 is connected to the daughter board 41 through a chip base; the daughter board 41 is connected to the daughter board LVDS interface 14 or the daughter board GTH interface 15 in the FPGA ZYNQ subsystem 1 through the LVDS interface; the digital micro-mirror chip driver can be compatible with digital micro-mirror chip drivers with various data rates, the LVDS interface rate is 800M DDR double-edge transmission, the GTH interface rate is 1.6G DDR double-edge transmission, 18 pairs of data signals are respectively arranged on the LVDS interface and the GTH interface, and the video resolution of 3840 × 2160 is supported to the maximum.
Referring to fig. 4, the three-color laser module 5 includes a red laser driving module 51, a green laser driving module 52, a blue laser driving module 53, and a fill light driving module 54; the red laser driving module 51, the green laser driving module 52, the blue laser driving module 53 and the supplementary lighting driving module 54 are respectively connected with the ZYNQ chip 11 in the FPGA programmable gate array ZYNQ subsystem 1; through the accurate opening time who controls red laser, green laser, blue laser and light filling of ZYNQ chip 11 for the color that the user can see is more bright-colored, and the most real reproduction objective world is abundant color.
Referring to fig. 5, the video input module 6 is composed of an HDMI input interface 61, a video transceiver chip GSV201162 and a V-by-One input interface 63, wherein the HDMI input interface 61 is connected with the video transceiver chip GSV201162, and the video transceiver chip GSV201162 is connected with the ZYNQ chip 11 in the FPGA ZYNQ subsystem 1; the V-by-One input interface 63 is connected with a ZYNQ chip 11, an MCU singlechip module 2 and a USB concentrator module 8 in the FPGA ZYNQ subsystem 1. The GSV2011 is used as a video coding and decoding chip, has the function of receiving and transmitting an HDMI2.0 interface, is compatible with an HDMI1.4 interface downwards, has 16 pairs of LVDS differential pairs in total, and has the upper limit of the highest data transmission rate of a single pair of LVDS of 1.5 Gbps; the V-by-One interface comprises 8 pairs of differential data signals and other interactive interfaces, wherein the V-by-One interface comprises 1 pair of USB differential signals and 12 single-ended signals, the 8 pairs of differential data signals are used for transmitting video data, the highest data rate of each pair of differential signals can reach 3.2Gbps, compared with the traditional LVDS parallel video signal interface, the V-by-One interface needs fewer signal lines, wire cost is effectively reduced, and resource space is saved.
Referring to fig. 6, the galvanometer module 7 includes a first directional galvanometer driving module 71 and a second directional galvanometer driving module 72; the first direction galvanometer driving module 71 and the second direction galvanometer driving module 72 are respectively connected with a ZYNQ chip 11 in the FPGA ZYNQ subsystem 1. The resolution of the novel high-speed 4K digital micromirror chip based on the invention is 1920 x 1080 (2K), if the 4K resolution projection display is realized by using the 2K resolution digital micromirror chip, the invention needs to be matched with a vibrating mirror, and the 2K resolution digital micromirror chip can realize the 4K resolution image projection display by shaking the vibrating mirror once in two directions, namely shaking twice in total. The ZYNQ chip 11 controls the first direction galvanometer driving module 71 and the second direction galvanometer driving module 72, so that the effect of controlling the galvanometer dithering twice can be realized.
Referring to fig. 7, the fan module 9 includes a first fan driving module 91, a second fan driving module 92, a third fan driving module 93, a fourth fan driving module 94, a fifth fan driving module 95, a sixth fan driving module 96 and a seventh fan driving module 97, where each fan driving module corresponds to one fan interface; the first fan driving module 91, the second fan driving module 92, the third fan driving module 93, the fourth fan driving module 94, the fifth fan driving module 95, the sixth fan driving module 96 and the seventh fan driving module 97 are respectively connected with the MCU single chip module 2; every fan drive module corresponds a fan interface respectively, can realize the real-time fan rotational speed regulation of different speeds through MCU single chip module 2, can fully satisfy laser source, digital micromirror chip (DMD) and the not equidimension heat dissipation demand of core treater ZYNQ chip 11.
Referring to fig. 8, the daughter board LVDS interface module 14 is composed of a daughter board LVDS interface 141 and 18 dc level shift circuit modules 142; there are 18 pairs of differential signals in the daughter board LVDS interface 141, and each pair of differential signals is respectively connected to one dc level shift circuit module 142.
Referring to fig. 9, the specific circuit of the dc level conversion circuit module 142 is composed of a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C1, and a capacitor C2, one end and the other end of the resistor R1 are respectively connected to the ZYNQ chip 11 in the FPGA ZYNQ subsystem 1, one end of the resistor R2 is connected to the power supply, the other end is connected to the resistor R3, the other end of the resistor R3 is connected to the ground, one end of the resistor R4 is connected to the power supply, the other end is connected to the resistor R5, the other end of the resistor R5 is connected to the ground, one end of the capacitor C1 is connected to the resistor R1, the other end of the capacitor C2 and one end of the differential signal in the LVDS daughter board interface 141, and one end of the capacitor C2 is connected to the resistor R1, the other end of the differential signal in the LVDS daughter board interface 141. The common-mode voltage of the interface data signal of the novel high-speed 4K digital micromirror chip is 0.6V, the common-mode voltage of the LVDS signal output by the ZYNQ chip 11 is 1.2V, and the LVDS signal output by the ZYNQ chip 11 can be used for driving the novel high-speed 4K digital micromirror chip only through a direct-current level conversion circuit.
Examples
Referring to fig. 10, the invention can form a 4K ultra high definition real-time video display platform, the video input/output module 8 realizes video input, and the video data decoded into the video data that can be processed by the FPGA is sent to the ZYNQ chip 11 in the FPGA ZYNQ system 1. The code stored in the SD card module 18 can realize the driving of a novel high-speed 4K digital micro-mirror chip, and can realize the ultrahigh-definition projection display of 4K resolution by matching with the three-color laser module 5, the vibrating mirror module 7, the fan module 9 and the diffusion wheel module 10, and meanwhile, can realize the man-machine interaction by being connected with an upper computer through the USB-UART module 19, and can adjust the front-end video algorithm such as brightness contrast, tone, trapezoidal correction and the like, thereby providing high-quality video viewing experience for users.
The specific working process is as follows: when the system is powered on, the ZYNQ chip 11 reads the compiled codes from the SD card module 18, the MCU singlechip module 2 reads the compiled codes from the self-contained storage module, and the system is started. The projection display video is input to the ZYNQ chip 11 from a V-by-One interface 63 of the video input module 6; the ZYNQ chip 11 sends the decoded video data to the daughter board GTH interface 15, and transmits the video data to the daughter board 41 through a flexible flat cable, so as to drive two hundred and ten thousand micromirrors on the DMD chip 42 to flip. Meanwhile, according to the connection condition of the current optical machine, the ZYNQ chip 11 drives the three-color laser module 5 to stably project different colors, and the ZYNQ chip 11 drives the galvanometer module 7 to realize galvanometer dithering twice; meanwhile, the MCU singlechip module 2 controls and drives the fan module 9 and the diffusion wheel module 10 to realize the rotation of the fan and the diffusion wheel. Finally, the DMD chip 42 on the daughter board is matched with a projection screen cloth through a light path, a diffusion wheel and a galvanometer to perform projection of 4K full high-definition resolution; if a user selects to perform video front-end processing on a video to be projected by connecting an upper computer through a USB-UART module 19, the original video is processed by a video front-end processing algorithm solidified in an SD card module 18, the processed video data is sent to a daughter board GTH interface 15 through a digital micromirror drive algorithm and is transmitted to a daughter board module 4 through a flexible flat cable, and finally, a digital micromirror chip on the daughter board performs 4K full-high-definition resolution projection on a projection screen cloth through the matching of a light path, a diffusion wheel and a galvanometer; in the video processing process, in order to realize real-time ultra-high-definition data processing, the ZYNQ chip 11 is provided with a 2GB 64bit DDR4 memory 14, and the highest data rate can reach 2666 MT/s.
Claims (2)
1. A video display driving system based on a novel high-speed 4K digital micromirror chip is characterized by comprising an FPGA (field programmable gate array) ZYNQ subsystem (1), an MCU (microprogrammed control unit) singlechip module (2), a power module (3), a daughter board module (4), a three-color laser module (5), a video input module (6), a galvanometer module (7), a USB (universal serial bus) concentrator module (8), a fan module (9) and a diffusion wheel module (10), wherein the FPGA ZYNQ subsystem (1) is respectively connected with the MCU singlechip module (2), the power module (3), the daughter board module (4), the three-color laser module (5), the video input module (6), the galvanometer module (7) and the USB concentrator module (8); the MCU singlechip module (2) is connected with the FPGA ZYNQ subsystem (1), the video input module (6), the USB concentrator module (8), the fan module (9) and the diffusion wheel module (10); the power supply module (3) is connected with the FPGA ZYNQ subsystem (1), the MCU singlechip module (2), the daughter board module (4), the three-color laser module (5), the video input module (6), the galvanometer module (7), the USB concentrator module (8), the fan module (9) and the diffusion wheel module (10); the video input module (6) is connected with the FPGA ZYNQ subsystem (1), the MCU singlechip module (2) and the USB concentrator module (8); wherein:
the FPGA programmable gate array ZYNQ subsystem (1) comprises a ZYNQ chip (11), a 2GB 64bit DDR4 memory (12), a 1GB 32bit DDR4 memory (13), a daughter board LVDS interface (14), a daughter board GTH interface (15), an SATA module (16), a FLASH module (17), an SD card module (18), a USB UART module (19), a USB3.0 module (110), a USB2.0 module (111) and a communication interface (112); the ZYNQ chip (11) is respectively connected with a 2GB 64bit DDR4 memory (12), a 1GB 32bit DDR4 memory (13), a daughter board LVDS interface (14), a daughter board GTH interface (15), an SATA module (16), a FLASH module (17), an SD card module (18), a USB UART module (19), a USB3.0 module (110), a USB2.0 module (111) and a communication interface (112);
the daughter board module (4) comprises a daughter board (41) and a DMD chip (42), and the DMD chip (42) is connected to the daughter board (41) through a chip base; the daughter board (41) is connected to a daughter board LVDS interface (14) or a daughter board GTH interface (15) in the FPGA ZYNQ subsystem (1) through an LVDS interface;
the three-color laser module (5) comprises a red laser driving module (51), a green laser driving module (52), a blue laser driving module (53) and a supplementary lighting driving module (54); the red laser driving module (51), the green laser driving module (52), the blue laser driving module (53) and the supplementary lighting driving module (54) are respectively connected with a ZYNQ chip (11) in the FPGA ZYNQ subsystem (1);
the video input module (6) consists of an HDMI input interface (61), a video transceiver chip GSV2011 (62) and a V-by-One input interface (63), wherein the HDMI input interface (61) is connected with the video transceiver chip GSV2011 (62), and the video transceiver chip GSV2011 (62) is connected with a ZYNQ chip (11) in the FPGA ZYNQ subsystem (1); the V-by-One input interface (63) is connected with a ZYNQ chip (11), an MCU single chip module (2) and a USB concentrator module (8) in the FPGA ZYNQ subsystem (1);
the galvanometer module (7) comprises a first direction galvanometer driving module (71) and a second direction galvanometer driving module (72); the first direction galvanometer driving module (71) and the second direction galvanometer driving module (72) are respectively connected with a ZYNQ chip (11) in the FPGA ZYNQ subsystem (1);
the fan module (9) comprises a first fan driving module (91), a second fan driving module (92), a third fan driving module (93), a fourth fan driving module (94), a fifth fan driving module (95), a sixth fan driving module (96) and a seventh fan driving module (97), and each fan driving module corresponds to one fan interface; the first fan driving module (91), the second fan driving module (92), the third fan driving module (93), the fourth fan driving module (94), the fifth fan driving module (95), the sixth fan driving module (96) and the seventh fan driving module (97) are respectively connected with the MCU single chip microcomputer module (2).
2. The video display driving system based on the novel high-speed 4K digital micromirror chip of claim 1, wherein the daughter board LVDS interface module (14) is composed of a daughter board LVDS interface (141) and 18 dc level conversion modules (142); wherein the daughter board LVDS interface (141) is provided with 18 pairs of differential signals, each pair of differential signals is respectively connected with a DC level conversion module (142), the direct current level conversion module (142) is composed of a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C1 and a capacitor C2, one end and the other end of the resistor R1 are respectively connected with a ZYNQ chip (11) in the FPGA ZYNQ subsystem (1), one end of the resistor R2 is connected with a power supply, the other end of the resistor R2 is connected with a resistor R3, the other end of the resistor R3 is connected with the ground, one end of the resistor R4 is connected with the power supply, the other end of the resistor R5 is connected with the resistor R5, one end of the capacitor C1 is connected with the resistor R1, the other end of the capacitor R2 and one end of a differential signal in an LVDS daughter board interface (141), one end of the capacitor C2 is connected with the resistor R1, the other end of the capacitor C4 and the other end of the differential signal in the LVDS interface (141).
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