CN114967839A - Serial cascade system and method based on multiple clocks, and parallel cascade system and method - Google Patents

Serial cascade system and method based on multiple clocks, and parallel cascade system and method Download PDF

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CN114967839A
CN114967839A CN202210913086.1A CN202210913086A CN114967839A CN 114967839 A CN114967839 A CN 114967839A CN 202210913086 A CN202210913086 A CN 202210913086A CN 114967839 A CN114967839 A CN 114967839A
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chip
buffer
output
input
stage
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CN114967839B (en
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朱珂
徐庆阳
钟丹
谭力波
张波
肖峰
王盼
李丹丹
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Jingxin Microelectronics Technology Tianjin Co Ltd
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Jingxin Microelectronics Technology Tianjin Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0002—Serial port, e.g. RS232C
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0004—Parallel ports, e.g. centronics
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0038—System on Chip
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention belongs to the technical field of multi-clock cascade, and particularly relates to a serial cascade system and a method, a parallel cascade system and a method based on multiple clocks.

Description

Serial cascade system and method based on multiple clocks, and parallel cascade system and method
Technical Field
The invention belongs to the technical field of multi-clock cascade, and particularly relates to a serial cascade system and method and a parallel cascade system and method based on multiple clocks.
Background
The high-speed serial interface circuit (SerDes) mainly realizes that a transmitting end converts multi-path low-speed parallel signals into high-speed serial signals, and finally converts the high-speed serial signals into low-speed parallel signals again at a receiving end through transmission, the transmission mode can fully utilize the channel capacity of a transmission medium, reduce the number of transmission channels and device pins, improve the signal transmission speed and reduce the communication cost, because the SerDes is widely applied to a high-speed interface of a chip, the SerDes IP integrated into the chip generally needs to input a differential or single-ended low-frequency clock from the outside of the chip, and realize the speed output required by the high-speed interface through a PLL (phase locked loop) and a frequency division circuit inside the IP, because the high-speed interface of the SerDes is sensitive to the influences of jitter, crosstalk and the like, the quality requirement on an input reference clock is high, but in a high-speed exchange chip, a plurality of SerDes IPs are generally integrated, and the sensitive characteristic of the number of external pins of the chip is considered, it is generally desirable that the fewer pins outside the chip are better, so it is unlikely that one-to-one reference clock inputs are made from outside the chip for the SerDes IPs inside the chip; from the user use perspective, the multiple SerDes IPs input the reference clock from the outside of the chip one to one, which will increase the manufacturing cost of the PCB, which is relatively unacceptable in chip products;
the situation that a plurality of SerDes IPs are integrated inside a chip is common, and especially inside a switch chip, in order to ensure that more devices are connected to the switch chip, the more external high-speed interfaces are desired, the better the external high-speed interfaces are, so as to realize high-capacity switching and multi-node intercommunication. The current processing schemes for reference clocks in on-chip multiple SerDes IP integration can be mainly summarized into two types:
(1) PCB board level solution: as shown in fig. 5, in the method, the reference clock of each SerDes in the chip is led out to the top layer of Die through Bump, and the Bump is mapped to Ball one by one when the chip is packaged, so that when a PCB is welded, the corresponding chip can see the reference clock pair which is equal to SerDes IP in the chip, and then the driving clock is connected to each reference clock pair at the PCB level, and the reference clocks are directly injected one by one at the outside; secondly, the clock chip provides drive for a plurality of reference clocks, and the input of the clock chip is an off-chip crystal oscillator. Although the first mode can provide a high-quality reference clock through a crystal oscillator for a chip containing a plurality of high-speed SerDes IPs, the cost of the PCB can be increased by the board card of the crystal oscillator, and meanwhile, the reliability of the system can be reduced by the board card of the crystal oscillator; although the second mode can reduce the number of crystal oscillators, for tens of SerDes IP chips, the number of reference clocks that can be provided by the clock chip is still limited, and more crystal oscillators are still required, and in addition, the reference clocks provided by the clock chip can make the reference clocks travel a longer distance on the PCB, so that the design requirements of chip clock quality need to be specially considered in PCB design, the principle of clock line design is followed, the difficulty of PCB design is greatly increased, and the cost of manpower consumption is increased;
(2) packaging level solution: as shown in fig. 6, in this way, cascading of multiple reference clocks is solved on a package substrate, where the reference clock of each SerDes in a chip is led out to the top layer of Die through Bump, and multiple bumps are connected in parallel through traces of the package substrate in the chip package, and externally mapped into a group of pad balls, so that only one group of Ball access points for inputting the reference clock can be seen outside the chip, and only one crystal oscillator or one clock chip needs to be provided on a PCB, which can effectively solve the problems encountered in the PCB solution, but the cascading of this way has a high design requirement on the package substrate, and the good or bad packaging technology can also directly affect the performance of the chip, and this cascading way obviously increases the packaging difficulty and is not beneficial to the performance improvement of the chip; in addition, the reference clock on the packaging substrate can only realize the cascade connection of a plurality of SerDes IPs in a parallel routing mode, and the mode has strict requirements on the access mode of the SerDes IP reference clock and needs to consider the problem of matching impedance under parallel access; on the other hand, the area of the package substrate is larger than that of the chip, which leads to overlong reference clock routing on the package substrate, and the tolerance requirement of the on-chip SerDes IP on the quality of the reference clock is extremely high due to the long routing. Package-level solutions therefore place high demands on SerDes design and package substrate design.
In summary, the prior art has a problem of how to drive the reference clock for a long distance in the high-speed serial interface circuit with the multi-clock structure.
Disclosure of Invention
The invention provides a serial cascade system and a method based on multiple clocks, and a parallel cascade system and a method, which aim to solve the problem of how to drive a reference clock in a long distance in a high-speed serial interface circuit with a multi-clock structure in the prior art.
The technical problem solved by the invention is realized by adopting the following technical scheme: a serial cascade system based on multiple clocks, comprising: an off-chip crystal oscillator and an on-chip reference clock;
an input buffer and an output buffer with amplifying and shaping driving functions are respectively integrated in the chip;
the input end of the input buffer in the chip of the current stage is connected with the output end of the output buffer in the chip of the previous stage, and the output end of the input buffer in the chip of the current stage is connected with the reference clock in the chip;
the input end of the output buffer in the chip of the current stage is connected with the output end of the output buffer in the chip of the previous stage, and the output end of the output buffer in the chip of the current stage is connected with the input end of the input buffer in the chip of the next stage.
Further, the serial cascade system further includes: the input end of the first-stage in-chip input buffer is connected with the off-chip crystal oscillator, and the output end of the final in-chip output buffer is suspended.
Further, the serial cascade system further includes:
if the distance between two adjacent stages is larger than the maximum allowable distance threshold, inserting an enhanced buffer between the two stages;
and if the two-stage distance between the off-chip crystal oscillator and the input buffer in the first stage is larger than the maximum allowable distance threshold, inserting an enhanced buffer between the off-chip crystal oscillator and the input buffer in the first stage.
Meanwhile, the invention also provides a serial cascade method based on multiple clocks, which comprises the following steps:
inputting oscillation signals generated by an off-chip crystal oscillator into an on-chip input buffer and an on-chip output buffer;
the input buffer in the first chip outputs a driving signal output by amplification and shaping to a reference clock in the first chip;
the output buffer in the first chip is output to the input buffer in the next chip and the output buffer in the chip through the amplified and shaped output driving signal;
the input buffer in the chip of the current stage receives a driving signal output by the output buffer in the chip of the previous stage, and the driving signal output by amplification and shaping is output to a reference clock in the chip of the current stage;
the output buffer in the chip of the current stage receives a driving signal output by the output buffer in the first chip, and outputs the driving signal output by amplification and shaping to the input buffer in the next chip and the output buffer in the chip;
the final stage of in-chip input buffer receives a driving signal output by the last stage of in-chip output buffer, and outputs the driving signal output by amplification and shaping to a final pole piece in-chip reference clock;
and the final stage in-chip output buffer receives the driving signal output by the last stage in-chip output buffer and outputs a final pole driving signal through amplification and shaping suspension.
Further, the serial concatenation method further comprises:
if the distance between the previous stage and the current stage is larger than the maximum allowable distance threshold value, then:
the input buffer in the chip of the current stage receives a driving signal output by the output buffer in the chip of the previous stage through the enhanced buffer;
if the distance between the current stage and the next stage is larger than the maximum allowable distance threshold value, then:
the output buffer in the chip of the current level is output to the input buffer and the output buffer in the chip of the next level through the enhanced buffer;
if the distance between the off-chip crystal oscillator and the first stage is larger than the maximum allowable distance threshold value, then:
the off-chip crystal oscillator outputs to the input buffer and the output buffer in the next chip through the enhanced buffer.
Meanwhile, the invention also provides a parallel cascade system based on multiple clocks, which comprises: an off-chip crystal oscillator and an on-chip reference clock;
integrating an input buffer with amplifying and shaping driving functions on a chip;
the input end of the on-chip input buffer of the current level is connected with the off-chip crystal oscillator, and the output end of the on-chip input buffer of the current level is connected with the on-chip reference clock.
Further, the parallel cascade system further includes:
if the distance between two adjacent stages is larger than the maximum allowable distance threshold, inserting an enhanced buffer between the two stages;
and if the two-stage distance between the off-chip crystal oscillator and the on-chip input buffer of the current stage is larger than the maximum allowable distance threshold, inserting an enhanced buffer into the output of the off-chip crystal oscillator.
Further, the parallel cascade system further comprises: the input buffer adopts differential input or single-ended input.
Meanwhile, the invention also provides a parallel cascade method based on multiple clocks, which comprises the following steps:
an oscillation signal generated by an off-chip crystal oscillator is input into an on-chip input buffer, and the on-chip input buffer of the current stage outputs to an on-chip reference clock of the current stage through a driving signal output by amplification and shaping.
Further, the parallel cascading method further comprises the following steps:
and if the distance between the off-chip crystal oscillator and the current level is larger than the maximum allowable distance threshold, the off-chip crystal oscillator is output to the current level of on-chip input buffer through the enhanced buffer.
The beneficial technical effects are as follows:
the method comprises the steps of using an off-chip crystal oscillator and an on-chip reference clock; an input buffer and an output buffer with amplifying and shaping driving functions are respectively integrated in the chip; the input end of the input buffer in the chip of the current stage is connected with the output end of the output buffer in the chip of the previous stage, and the output end of the input buffer in the chip of the current stage is connected with the reference clock in the chip; the input end of the output Buffer in the chip of the present level is connected with the output end of the output Buffer in the chip of the previous level, the output end of the output Buffer in the chip of the present level is connected with the input end of the input Buffer in the chip of the next level, after a reference clock input by an off-chip crystal oscillator enters the chip of the serial structure, the serial structure is firstly connected into a customized drive Buffer circuit Buffer, the drive Buffer circuit converts the reference clock input from the off-chip into a reference clock which can be transmitted in the chip, a reference clock input interface is reserved at one side of the physical position of each SerDes IP in the chip, two groups of drive Buffer circuits are designed in the SerDes IP, one group of internal logics is used for driving the SerDes IP of the present level, one group is arranged at the output side boundary of the IP physical position and is used as the output of the reference clock, when the reference clock is input into the first drive Buffer in the chip from the off-chip or the clock chip, the output of the SerDes IP is connected to the drive Buffer input of the present level through the reference clock input of the SerDes, and amplifying and shaping the reference clock by using a driving Buffer placed at the physical position of the SerDes IP output side, and then outputting the reference clock to a reference clock input interface of the second-level SerDes IP, and repeating the steps until all the SerDes IPs in the chip are all cascaded. The reference clock input outside the chip is an independent input reference clock, is not influenced by the state of a chip, and can exist all the time after the clock is input, meanwhile, the drive Buffer customized by the reference clock cascading mode inside the chip is used for realizing the amplification and reshaping of the reference clock, and is essentially an amplifier and a shaper; the circuit designs a brand new reference clock cascade mode, abandons an external reference clock cascade mode, adopts a Die internal reference clock cascade mode, and can solve the design problem and the cost problem brought by the prior art cascade mode.
Drawings
FIG. 1 is a schematic diagram of the structure of the serial cascade system of the present invention;
FIG. 2 is a method flow diagram of the serial concatenation method of the present invention;
FIG. 3 is a schematic diagram of the architecture of the parallel cascade system of the present invention;
FIG. 4 is a method flow diagram of the parallel concatenation method of the present invention;
FIG. 5 is a schematic diagram of the PCB level solution of the present invention;
fig. 6 is a schematic diagram of the package level solution of the present invention.
In the figure:
1-an off-chip crystal oscillator, 2-an on-chip reference clock, 3-a local level of an on-chip input buffer, 4-a local level of an on-chip output buffer, 5-an upper level of an on-chip input buffer, 6-an upper level of an on-chip output buffer, 7-a lower level of an on-chip input buffer, 8-a lower level of an on-chip output buffer, and 9-an enhanced buffer;
s101, inputting oscillation signals generated by an off-chip crystal oscillator into an on-chip input buffer and an on-chip output buffer;
s102, outputting a driving signal output by the buffer input in the first chip through amplification and shaping to a reference clock in the first chip;
s103, outputting a driving signal output by the output buffer in the first stage chip through amplification and shaping to an input buffer in the next stage chip and an output buffer in the chip;
s104, receiving a driving signal output by an output buffer in the previous stage by the input buffer in the current stage, and outputting the driving signal output by amplification and shaping to a reference clock in the current stage;
s105, the output buffer in the chip of the current stage receives the driving signal output by the output buffer in the first stage, and the driving signal output by amplification and shaping is output to the input buffer in the next stage and the output buffer in the chip;
s106, receiving a driving signal output by an output buffer in the previous stage by the final stage in-chip input buffer, and outputting the driving signal output by amplifying and shaping to a reference clock in the final pole piece;
s107, the final stage in-chip output buffer receives the driving signal output by the last stage in-chip output buffer, and outputs a final pole driving signal through amplification and shaping suspension;
s201, inputting an oscillation signal generated by an off-chip crystal oscillator into an on-chip input buffer;
s202, outputting the driving signal output by the buffer in the current stage through amplification and shaping to the reference clock in the current stage.
Detailed Description
The invention is further described below with reference to the accompanying drawings:
example (b):
in this embodiment: as shown in fig. 1, the serial cascade system based on multiple clocks comprises: an off-chip crystal oscillator 1 and an on-chip reference clock 2;
an input buffer and an output buffer with amplifying and shaping driving functions are respectively integrated in the chip;
the input end of the input buffer3 in the current stage of the chip is connected with the output end of the output buffer6 in the last stage of the chip, and the output end of the input buffer3 in the current stage of the chip is connected with the reference clock 2 in the chip;
the input end of the output buffer4 in the current-stage chip is connected with the output end of the output buffer6 in the previous-stage chip, and the output end of the output buffer4 in the current-stage chip is connected with the input end of the input buffer7 in the next-stage chip.
The adoption of the chip comprises an off-chip crystal oscillator and an on-chip reference clock; an input buffer and an output buffer with amplifying and shaping driving functions are respectively integrated in the chip; the input end of the input buffer in the chip of the current stage is connected with the output end of the output buffer in the chip of the previous stage, and the output end of the input buffer in the chip of the current stage is connected with the reference clock in the chip; the input end of the output Buffer in the chip of the present level is connected with the output end of the output Buffer in the chip of the previous level, the output end of the output Buffer in the chip of the present level is connected with the input end of the input Buffer in the chip of the next level, after a reference clock input by an off-chip crystal oscillator enters the chip of the serial structure, the serial structure is firstly connected into a customized drive Buffer circuit Buffer, the drive Buffer circuit converts the reference clock input from the off-chip into a reference clock which can be transmitted in the chip, a reference clock input interface is reserved at one side of the physical position of each SerDes IP in the chip, two groups of drive Buffer circuits are designed in the SerDes IP, one group of internal logics is used for driving the SerDes IP of the present level, one group is arranged at the output side boundary of the IP physical position and is used as the output of the reference clock, when the reference clock is input into the first drive Buffer in the chip from the off-chip or the clock chip, the output of the SerDes IP is connected to the drive Buffer input of the present level through the reference clock input of the SerDes, and amplifying and shaping the reference clock by using a driving Buffer placed at the physical position of the SerDes IP output side, and then outputting the reference clock to a reference clock input interface of the second-level SerDes IP, and repeating the steps until all the SerDes IPs in the chip are all cascaded. The reference clock input outside the chip is an independent input reference clock, is not influenced by the state of a chip, and can exist all the time after the clock is input, meanwhile, the drive Buffer customized by the reference clock cascading mode inside the chip is used for realizing the amplification and reshaping of the reference clock, and is essentially an amplifier and a shaper; the circuit designs a brand new reference clock cascade mode, abandons an external reference clock cascade mode, adopts a Die internal reference clock cascade mode, and can solve the design problem and the cost problem brought by the prior art cascade mode.
The serial cascade system further comprises: the input end of the first-stage on-chip input buffer is connected to the off-chip crystal oscillator 1, and the output end of the final on-chip output buffer is suspended.
Due to the adoption of the serial cascade system, the method further comprises the following steps: the input end of the first-stage in-chip input buffer is connected with the off-chip crystal oscillator, and the output end of the final-stage in-chip output buffer is suspended.
The serial cascade system further comprises:
if the distance between two adjacent stages is larger than the maximum allowable distance threshold, inserting an enhancement buffer9 between the two stages;
if the two-stage distance between the off-chip crystal oscillator 1 and the input buffer in the first stage is greater than the maximum allowable distance threshold, an enhanced buffer9 is inserted between the off-chip crystal oscillator 1 and the input buffer in the first stage.
Due to the adoption of the serial cascade system, the method further comprises the following steps: if the distance between two adjacent stages is larger than the maximum allowable distance threshold, inserting an enhanced buffer between the two stages; if the two-stage distance between the off-chip crystal oscillator and the input Buffer in the first stage is larger than the maximum allowable distance threshold, an enhanced Buffer is inserted between the off-chip crystal oscillator and the input Buffer in the first stage, because if the routing between two adjacent IPs is larger than a certain distance, a new drive Buffer needs to be inserted between the IPs to meet the drive requirement, when the distance is larger than the certain distance, the Buffer is inserted, the Lane widths between different IPs have difference, a determined value cannot be given, and preferably, the maximum allowable distance threshold is preferably selected>8W Lane mm, SerDes receives and transmits data through Lane, 8WLane refers to the width of 8 Lanes of the SerDes, and the cascade method of the drive Buffer is customized. Aiming at the arrangement of a plurality of SerDes IP physical positions in a chip, in order to meet the transmission quality of a SerDes reference clock, a customized drive Buffer IP needs to be inserted between two adjacent SerDes IPs according to the requirements of the SerDes, and the drive Buffer IP is arranged between two adjacent SerDes IPsThe driving Buffer essentially realizes the amplification and reshaping of the reference clock, and a serial cascade mode mainly considers the distance between the input Buffer and the output Buffer between two stages.
As shown in fig. 2, the serial concatenation method based on multiple clocks includes:
inputting oscillation signals generated by the off-chip crystal oscillator 1 into the on-chip input buffer S201 and the on-chip output buffer S101;
the driving signal output by the buffer input in the first chip through amplification and shaping is output to a reference clock 2S 102 in the first chip;
the output buffer in the first level chip is output to the input buffer7 in the next level chip and the output buffer S103 in the chip through the amplified and shaped output driving signal;
the input buffer3 in the current stage of chip receives the driving signal output by the output buffer6 in the previous stage of chip, and outputs the amplified and shaped output driving signal to the reference clock 2S 104 in the current stage of chip;
the output buffer4 in the current stage receives the driving signal output by the output buffer in the first stage, and outputs the driving signal output by amplification and shaping to the input buffer7 in the next stage and the output buffer S105 in the next stage;
the final stage intra-chip input buffer receives the driving signal output by the last stage intra-chip output buffer6, and outputs the driving signal output by amplification and shaping to the final intra-chip reference clock 2S 106;
the final stage in-chip output buffer receives the driving signal output by the previous stage in-chip output buffer6, and outputs the final pole driving signal S107 by amplifying and shaping the driving signal.
Meanwhile, the invention also provides a serial cascade method based on multiple clocks, which comprises the following steps: inputting oscillation signals generated by an off-chip crystal oscillator into an on-chip input buffer and an on-chip output buffer; the input buffer in the first chip outputs a driving signal output by amplification and shaping to a reference clock in the first chip; the first stage in-chip output buffer outputs a drive signal output by amplifying and shaping to a next stage in-chip input buffer and an in-chip output buffer, the final stage in-chip output buffer receives the drive signal output by the last stage in-chip output buffer, and outputs a final stage drive signal by amplifying and shaping, because a signal of a reference clock input by an off-chip crystal oscillator is output to a reference clock in the first stage through the in-chip input buffer, and simultaneously, the signal is output to the in-chip input buffer and the in-chip output buffer in a next stage SerDes IP through the in-chip output buffer, similarly, the in-chip input buffer and the in-chip output buffer in the next stage SerDes IP are output to the in-chip reference clock in the current stage and the in-chip input buffer and the in-chip output buffer in the next stage SerDes IP, and so on until the output is at the final stage, through a serial cascade system structure based on multiple clocks, the clock signals are finally transmitted in series among all related SerDes IPs, so that the method is used for solving the problem of a cascade mode of multiple reference clocks of multiple SerDes on the premise of solving long-distance transmission and impedance matching.
The serial concatenation method further comprises:
if the distance between the previous stage and the current stage is larger than the maximum allowable distance threshold value, then:
the input buffer3 in the current stage receives the driving signal output by the output buffer6 in the previous stage through the enhanced buffer 9;
if the distance between the current level and the next level is larger than the maximum allowable distance threshold value, then:
the output buffer4 in the current level of the chip is output to the input buffer7 in the next level of the chip and the output buffer in the chip through the enhanced buffer 9;
if the distance between the off-chip crystal oscillator 1 and the first stage is larger than the maximum allowable distance threshold value, then:
the off-chip crystal oscillator 1 outputs to the next stage of on-chip input buffer7 and on-chip output buffer through the enhanced buffer 9.
Because the method adopts the following steps if the distance between the upper stage and the current stage is larger than the maximum allowable distance threshold value: the input buffer in the chip of the current stage receives a driving signal output by the output buffer in the chip of the previous stage through the enhanced buffer; ... when the off-chip crystal oscillator outputs to the next level of on-chip input Buffer and the on-chip output Buffer through the enhanced Buffer, similarly, if the routing between two adjacent IPs is greater than a certain distance, a new driving Buffer needs to be inserted between the IPs to meet the driving requirement, when the distance is greater than the certain distance, the Buffer is inserted, the Lane widths between different IPs are different, a determined value cannot be given, preferably, the maximum allowable spacing threshold is greater than 8WLanemm, the SerDes transmits and receives data through the Lane, the 8WLane refers to the width of 8 Lanes of the SerDes, and the cascading method of the driving Buffer is customized. Aiming at the emission of a plurality of SerDes IP physical positions in a chip, in order to meet the transmission quality of a SerDes reference clock, a customized driving Buffer IP needs to be inserted between two adjacent SerDes IPs according to the requirements of the SerDes, and the driving Buffer essentially realizes the amplification and reshaping of the reference clock.
As shown in fig. 3, the parallel cascade system based on multiple clocks is characterized by comprising: an off-chip crystal oscillator 1 and an on-chip reference clock 2;
integrating an input buffer with amplifying and shaping driving functions on a chip;
the input end of the on-chip input buffer3 of the current stage is connected to the off-chip crystal oscillator 1, and the output end of the on-chip input buffer3 of the current stage is connected to the on-chip reference clock 2.
Meanwhile, the invention also provides a parallel cascade system based on multiple clocks, which comprises: an off-chip crystal oscillator and an on-chip reference clock; integrating an input buffer with amplifying and shaping driving functions on a chip; the input end of the in-chip input Buffer of the level is connected with the off-chip crystal oscillator, the output end of the in-chip input Buffer of the level is connected with the in-chip reference clock, because the mechanism has the same purpose with the serial cascade structure, the reference clock input from the outside of the chip is firstly input into the in-chip customized drive Buffer, the output of the drive Buffer is respectively output to the reference clock input sides of a plurality of SerDes IPs in a multi-path parallel mode, and a plurality of SerDes of each path are processed in a serial cascade mode. The same reference clock input outside the chip enters the Die through the custom drive Buffer, the reference clock is an independent input reference clock and is not influenced by the chip state, and the clock always exists after being input. But the connection modes of the reference clock entering the Die are different between the IPs, and the reference clock input outside the chip is used as the reference clock source in the Die and is respectively input to the interior of the IP to be used leftwards and rightwards. The invention adopts the mode of cascade connection of multiple SerDes IP internal reference clocks of Die, realizes the long-distance driving of the reference clocks of the full-chip multiple SerDes IP by designing a driving Buffer with signal amplification and reshaping functions in a chip, simultaneously carries out the cascade connection of the reference clocks in the Die in the mode of parallel cascade connection between the SerDes IPs, unifies the problem of cascade connection of the reference clocks into the SerDes IP design, can also solve the problem of matched impedance, and simultaneously has the technical effect of parallel connection relative to the serial cascade connection mode that the reference clocks in each stage of the chip are synchronously driven by an on-chip input Buffer through an off-chip crystal oscillator, the synchronism is better.
The parallel cascade system further comprises:
if the distance between two adjacent stages is larger than the maximum allowable distance threshold, inserting an enhancement buffer9 between the two stages;
and if the two-stage distance between the off-chip crystal oscillator 1 and the on-chip input buffer3 at the current stage is larger than the maximum allowable distance threshold, inserting an enhanced buffer9 into the output of the off-chip crystal oscillator 1.
Because the method is adopted, if the distance between two adjacent stages is larger than the maximum allowable distance threshold, the enhancement buffer is inserted between the two stages; if the two-stage distance between the off-chip crystal oscillator and the input Buffer in the chip is larger than the maximum allowable distance threshold, inserting an enhanced Buffer into the output of the off-chip crystal oscillator, because in a parallel cascade mode, if the routing between two adjacent IPs is larger than a certain distance, a new drive Buffer needs to be inserted between the IPs to meet the drive requirement, when the distance is larger than the distance, the Buffer is inserted, the Lane widths between different IPs have difference, a determined value cannot be given, preferably, the maximum allowable distance threshold is larger than 8WLanemm, SerDes receives and transmits data through Lane, 8WLane refers to the width of 8 Lanes of SerDes, and the cascade method of the drive Buffer is customized. Aiming at the emission of a plurality of SerDes IP physical positions in a chip, in order to meet the transmission quality of a SerDes reference clock, a customized driving Buffer IP needs to be inserted between two adjacent SerDes IPs according to the requirements of the SerDes, the driving Buffer essentially realizes the amplification and reshaping of the reference clock, and the cascade is the distance between two stages of input buffers, which is different from the parallel mode.
The parallel cascade system further comprises: the input buffer adopts differential input or single-ended input.
The parallel cascade system also comprises: the input buffer adopts differential input or single-ended input, the buffer can adopt single-ended input or differential input, and the output buffer is suitable for the output of different off-chip clocks, and has more flexible and convenient application mode and wide application range.
As shown in fig. 4, the parallel cascading method based on multiple clocks includes:
the oscillation signal generated by the off-chip crystal oscillator 1 is input to the on-chip input buffer S201, and the driving signal output by the current-stage on-chip input buffer3 through amplification and shaping is output to the current-stage on-chip reference clock 2S 202.
Meanwhile, the invention also provides a parallel cascade method based on multiple clocks, which comprises the following steps: the method comprises the steps that an oscillation signal generated by an off-chip crystal oscillator is input into an on-chip input buffer, the on-chip input buffer of the stage outputs a driving signal output by amplification and shaping to an on-chip reference clock of the stage, and only one group of input buffers are used for the on-chip reference clock of the stage due to a parallel cascade method.
The parallel cascading method further comprises the following steps:
if the distance between the off-chip crystal oscillator 1 and the current level is larger than the maximum allowable distance threshold, the off-chip crystal oscillator 1 outputs the enhanced buffer9 to the current level on-chip input buffer 3.
The parallel cascade method also comprises the following steps: if the distance between the off-chip crystal oscillator and the current stage is larger than the maximum allowable distance threshold, the off-chip crystal oscillator outputs the enhanced Buffer to the on-chip input Buffer of the current stage, and similarly, because the cascade is different from the parallel mode, the distance between the two input buffers is the distance between the two input buffers, if the routing between two adjacent IPs is larger than a certain distance, a new drive Buffer needs to be inserted between the IPs to meet the drive requirement, when the distance is larger than the certain distance, the Buffer is inserted, the Lane widths between different IPs have difference, a determined value cannot be given, preferably, the maximum allowable distance threshold is larger than 8WLanemm, SerDes receives and transmits data through Lane, 8WLane refers to the width of 8 Lanes of the SerDes, and the cascade method of the drive Buffer is customized. Aiming at the emission of a plurality of SerDes IP physical positions in a chip, in order to meet the transmission quality of a SerDes reference clock, a customized driving Buffer IP needs to be inserted between two adjacent SerDes IPs according to the requirements of the SerDes, and the driving Buffer essentially realizes the amplification and reshaping of the reference clock.
The working principle is as follows:
the method comprises the steps that an off-chip crystal oscillator and an on-chip reference clock are adopted; an input buffer and an output buffer with amplifying and shaping driving functions are respectively integrated in the chip; the input end of the input buffer in the chip of the current stage is connected with the output end of the output buffer in the chip of the previous stage, and the output end of the input buffer in the chip of the current stage is connected with the reference clock in the chip; the input end of the output Buffer in the chip of the present level is connected with the output end of the output Buffer in the chip of the previous level, the output end of the output Buffer in the chip of the present level is connected with the input end of the input Buffer in the chip of the next level, after a reference clock input by an off-chip crystal oscillator enters the chip of the serial structure, the serial structure is firstly connected into a customized drive Buffer circuit Buffer, the drive Buffer circuit converts the reference clock input from the off-chip into a reference clock which can be transmitted in the chip, a reference clock input interface is reserved at one side of the physical position of each SerDes IP in the chip, two groups of drive Buffer circuits are designed in the SerDes IP, one group of internal logics is used for driving the SerDes IP of the present level, one group is arranged at the output side boundary of the IP physical position and is used as the output of the reference clock, when the reference clock is input into the first drive Buffer in the chip from the off-chip or the clock chip, the output of the SerDes IP is connected to the drive Buffer input of the present level through the reference clock input of the SerDes, and amplifying and shaping the reference clock by using a driving Buffer placed at the physical position of the SerDes IP output side, and then outputting the reference clock to a reference clock input interface of the second-level SerDes IP, and repeating the steps until all the SerDes IPs in the chip are all cascaded. The reference clock input outside the chip is an independent input reference clock, is not influenced by the state of a chip, and can exist all the time after the clock is input, meanwhile, the drive Buffer customized by the reference clock cascading mode inside the chip is used for realizing the amplification and reshaping of the reference clock, and is essentially an amplifier and a shaper; the circuit designs a brand-new reference clock cascade mode, abandons an external reference clock cascade mode, adopts the reference clock cascade in die, and can solve the design problem and the cost problem brought by the cascade mode in the prior art.
The invention solves the problem of how to drive the reference clock in a long distance in a high-speed serial interface circuit with a multi-clock structure in the prior art, and has the beneficial technical effects of solving the long-distance driving problem of the multi-reference clock and the problem of impedance matching.
The technical solutions of the present invention or similar technical solutions designed by those skilled in the art based on the teachings of the technical solutions of the present invention are all within the scope of the present invention to achieve the above technical effects.

Claims (10)

1. A serial cascade system based on multiple clocks, comprising: an off-chip crystal oscillator and an on-chip reference clock;
an input buffer and an output buffer with amplifying and shaping driving functions are respectively integrated in the chip;
the input end of the input buffer in the chip of the current stage is connected with the output end of the output buffer in the chip of the previous stage, and the output end of the input buffer in the chip of the current stage is connected with the reference clock in the chip;
the input end of the output buffer in the chip of the current stage is connected with the output end of the output buffer in the chip of the previous stage, and the output end of the output buffer in the chip of the current stage is connected with the input end of the input buffer in the chip of the next stage.
2. The serial cascading system of claim 1, further comprising: the input end of the first-stage in-chip input buffer is connected with the off-chip crystal oscillator, and the output end of the final in-chip output buffer is suspended.
3. The serial cascading system of claim 2, further comprising:
if the distance between two adjacent stages is larger than the maximum allowable distance threshold, inserting an enhanced buffer between the two stages;
and if the two-stage distance between the off-chip crystal oscillator and the input buffer in the first stage is larger than the maximum allowable distance threshold, inserting an enhanced buffer between the off-chip crystal oscillator and the input buffer in the first stage.
4. The serial cascade method based on multiple clocks is characterized by comprising the following steps:
inputting oscillation signals generated by an off-chip crystal oscillator into an on-chip input buffer and an on-chip output buffer;
the input buffer in the first chip outputs a driving signal output by amplification and shaping to a reference clock in the first chip;
the output buffer in the first chip is output to the input buffer in the next chip and the output buffer in the chip through the amplified and shaped output driving signal;
the input buffer in the chip of the current stage receives a driving signal output by the output buffer in the chip of the previous stage, and the driving signal output by amplification and shaping is output to a reference clock in the chip of the current stage;
the output buffer in the chip of the current stage receives a driving signal output by the output buffer in the first chip, and outputs the driving signal output by amplification and shaping to the input buffer in the next chip and the output buffer in the chip;
the final stage of in-chip input buffer receives a driving signal output by the last stage of in-chip output buffer, and outputs the driving signal output by amplification and shaping to a final pole piece in-chip reference clock;
and the final stage in-chip output buffer receives the driving signal output by the last stage in-chip output buffer and outputs a final pole driving signal through amplification and shaping suspension.
5. The serial concatenation method of claim 4, further comprising:
if the distance between the previous stage and the current stage is larger than the maximum allowable distance threshold value, then:
the input buffer in the chip of the current stage receives a driving signal output by the output buffer in the chip of the previous stage through the enhanced buffer;
if the distance between the current stage and the next stage is larger than the maximum allowable distance threshold value, then:
the output buffer in the chip of the current level is output to the input buffer and the output buffer in the chip of the next level through the enhanced buffer;
if the distance between the off-chip crystal oscillator and the first stage is larger than the maximum allowable distance threshold value, then:
the off-chip crystal oscillator outputs to the input buffer and the output buffer in the next chip through the enhanced buffer.
6. A parallel cascade system based on multiple clocks, comprising: an off-chip crystal oscillator and an on-chip reference clock;
integrating an input buffer with amplifying and shaping driving functions on a chip;
the input end of the local-level on-chip input buffer is connected to the off-chip crystal oscillator, and the output end of the local-level on-chip input buffer is connected to the on-chip reference clock.
7. The parallel cascading system of claim 6, further comprising:
if the distance between two adjacent stages is larger than the maximum allowable distance threshold, inserting an enhanced buffer between the two stages;
and if the two-stage distance between the off-chip crystal oscillator and the on-chip input buffer of the current stage is larger than the maximum allowable distance threshold, inserting an enhanced buffer into the output of the off-chip crystal oscillator.
8. The parallel cascading system of claim 7, further comprising: the input buffer adopts differential input or single-ended input.
9. The parallel cascading method based on multiple clocks is characterized by comprising the following steps:
an oscillation signal generated by an off-chip crystal oscillator is input into an on-chip input buffer, and the on-chip input buffer of the current stage outputs to an on-chip reference clock of the current stage through a driving signal output by amplification and shaping.
10. The parallel cascading method of claim 9, further comprising:
and if the distance between the off-chip crystal oscillator and the current level is larger than the maximum allowable distance threshold, the off-chip crystal oscillator is output to the current level of on-chip input buffer through the enhanced buffer.
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US20010017558A1 (en) * 1998-08-06 2001-08-30 Satoru Hanzawa Semiconductor integrated circuit having a clock recovery circuit
WO2005104368A1 (en) * 2004-04-20 2005-11-03 Advantest Corporation Jitter generating circuit
CN104022775A (en) * 2014-06-02 2014-09-03 复旦大学 FIFO protocol based digital interface circuit for SerDes technology

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115882870A (en) * 2023-02-01 2023-03-31 井芯微电子技术(天津)有限公司 High-speed serializer and deserializer integration method and electronic equipment

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