CN114938131B

CN114938131B - Control circuit and method of power factor correction circuit based on FLYBACK

Info

Publication number: CN114938131B
Application number: CN202210619410.9A
Authority: CN
Inventors: 李伊珂
Original assignee: Jingyi Semiconductor Co ltd
Current assignee: Jingyi Semiconductor Co ltd
Priority date: 2022-06-01
Filing date: 2022-06-01
Publication date: 2023-02-28
Anticipated expiration: 2042-06-01
Also published as: CN114938131A

Abstract

Embodiments of the present disclosure relate to control circuits and methods for FLYBACK-based power factor correction circuits. The control circuit includes a duty cycle adjustment signal generation circuit. A duty ratio adjustment signal generation circuit generates a duty ratio adjustment signal based on a main switch control signal and an error signal generated based on an output voltage feedback signal. The duty ratio adjusting signal is used for adjusting an on-time control signal generated by the on-time generating circuit and an off-time control signal generated by the off-time generating circuit, and further controlling the input current to change along with the input voltage. The control circuit is simple and easy to implement, high in dynamic response speed and good in power factor correction effect.

Description

Control circuit and method of power factor correction circuit based on FLYBACK

Technical Field

The present invention relates to electronic circuits, and more particularly, to a control circuit and method for a Power Factor Correction (PFC) circuit based on FLYBACK.

Background

In recent years, switching power supply devices have been widely used in related fields such as power systems, industries, and transportation. However, due to the non-linear characteristic of the switching power supply, when the switching power supply is connected with a power grid, the input current of the power grid is distorted by the rectifying equipment, so that the current contains a large amount of harmonic waves, the power factor of the power supply is low, the electronic components are operated by mistake, and the service life and the normal function of the equipment are seriously influenced. Meanwhile, a large amount of harmonic waves flow into the power grid, and serious harmonic pollution is caused to the power grid. In order to reduce harmonic pollution of power electronic devices such as switching power supplies to the power grid, some national and international organizations have set relevant harmonic standards one after another. In order to meet these harmonic standards, PFC techniques must be used to bring the input current harmonics of the switching converter to the limiting criteria.

Generally speaking, the input voltage V of the PFC circuit _IN The mains supply with a sinusoidal waveform with the frequency of 50 Hz is obtained after rectification and is a sinusoidal half-wave signal. To achieve PFC control, the current I is input _IN The waveform of (A) needs to follow the input voltage V _IN And the phases of the two need to be identical, thereby improving the power factor of the circuit.

In a common PFC topology structure, for example, a PFC circuit of a BOOST topology, because the inductor current is continuous, when only the switching converter of the BOOST topology needs to be controlled to operate in an interrupted or critical mode, the input current can automatically track the input voltage, and thus, the PFC circuit has an automatic PFC function. However, in some applications requiring electrical isolation, the inductor current is discontinuous, and therefore, it is desirable to provide a power factor correction circuit and method based on the FLYBACK topology.

Disclosure of Invention

The present invention is directed to solving the above-mentioned problems in the prior art, and provides a control circuit and method for a power factor correction circuit based on a FLYBACK circuit.

According to an aspect of the present invention, there is provided a control circuit of a FLYBACK-based power factor correction circuit, including: the error amplifying circuit receives a voltage feedback signal representing the output voltage of the power factor correction circuit, compares the voltage feedback signal with a first reference voltage and generates an error signal, and the error signal represents the difference value of the voltage feedback signal and the first reference voltage; the duty ratio adjusting signal generating circuit receives an inverted signal and an error signal of a control signal and generates a duty ratio adjusting signal according to the inverted signal and the error signal of the control signal, wherein the control signal is used for controlling the on-off switching of a main switching tube in the power factor correcting circuit; the on-time generating circuit receives the error signal, the control signal, the duty ratio adjusting signal and the input current sampling signal and generates an on-time control signal according to the error signal, the control signal, the duty ratio adjusting signal and the input current sampling signal, wherein the input current sampling signal represents the input current of the power factor correcting circuit; the turn-off time generating circuit receives the duty ratio adjusting signal and the secondary side current sampling signal and generates a turn-off time control signal according to the duty ratio adjusting signal and the secondary side current sampling signal, wherein the secondary side current sampling signal represents the current flowing through the secondary side of the transformer in the power factor correction circuit; and the logic circuit receives the on-time control signal and the off-time control signal and performs logic operation on the on-time control signal and the off-time control signal to generate a control signal.

According to another aspect of the present invention, there is provided a power factor correction method based on FLYBACK, including: generating an error signal according to the voltage feedback signal, wherein the voltage feedback signal represents the output voltage of FLYBACK, and the error signal represents the difference between the voltage feedback signal and the first reference voltage; generating a duty ratio adjusting signal according to an inverted signal and an error signal of a control signal, wherein the control signal is used for controlling the on-off switching of a main switching tube in FLYBACK; generating a conduction time control signal according to the error signal, the control signal, the duty ratio adjusting signal and the input current sampling signal, wherein the input current sampling signal represents the input current of FLYBACK; generating a turn-off time control signal according to the duty ratio adjusting signal and a secondary side current sampling signal, wherein the secondary side current sampling signal represents the current flowing through the secondary side of a transformer in the FLYBACK converter; and performing logic operation on the on-time control signal and the off-time control signal to generate a control signal.

According to another aspect of the present invention, there is provided a power factor correction method based on a FLYBACK circuit, including: generating the minimum on-time and the minimum off-time of a main switching tube in the FLYBACK circuit according to the voltage feedback signal; judging whether the input current of the FLYBACK circuit is larger than a minimum input current threshold value or not; when the input current of the FLYBACK circuit is larger than the minimum current threshold value, controlling the main switching tube to be conducted for minimum conduction time and to be switched off for minimum turn-off time; when the input current of the FLYBACK circuit is smaller than the minimum current threshold value, prolonging the conduction time of a main switching tube to a first conduction time, and prolonging the turn-off time of the main switching tube to a first turn-off time, wherein the first conduction time is longer than the minimum conduction time, and the first turn-off time is longer than the minimum turn-off time; judging whether the secondary side current is reduced to zero or not; if the secondary side current is reduced to zero, judging whether the turn-off time of the main switching tube is more than or equal to the minimum turn-off time; if the turn-off time of the main switching tube is equal to the turn-off and turn-on time, controlling the main switching tube to be turned on for the minimum turn-on time; and if the turn-off time of the main switching tube is longer than the turn-off conduction time, prolonging the conduction time of the main switching tube to enable the conduction time of the main switching tube to be longer than the minimum conduction time

By using the embodiments of the present disclosure, corresponding technical effects can be achieved.

Drawings

Fig. 1 provides a PFC circuitry based on FLYBACK according to an illustrative embodiment of the invention.

Fig. 2 is a schematic diagram of waveforms according to an embodiment of the present invention.

Fig. 3 is a circuit schematic of the control circuit 100 according to an embodiment of the present invention.

Fig. 4 is a schematic diagram illustrating a partial signal waveform of the control circuit 100 according to an embodiment of the present invention.

Fig. 5 is a schematic diagram of a partial signal waveform of the control circuit 100 according to another embodiment of the present invention.

Fig. 6 illustrates a circuit schematic diagram of the minimum on-time generation circuit 31 shown in fig. 3 according to an embodiment of the present invention.

Fig. 7 illustrates a circuit schematic of the error amplifying circuit 11 shown in fig. 3 according to another embodiment provided by the present invention.

Fig. 8 illustrates a PFC control method according to one embodiment provided by the present invention.

As shown in the drawings, like reference numerals refer to like parts throughout the different views. The drawings presented herein are for purposes of illustrating the embodiments, principles, concepts, etc., and are not necessarily drawn to scale.

Detailed Description

Specific embodiments of the present invention will now be described without limitation with reference to the accompanying drawings. Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. The verbs "comprising" and "having" are used herein as open-ended limitations that neither exclude nor require the presence of unrecited features. The features recited in the dependent claims may be freely combined with each other, unless explicitly stated otherwise. The use of the terms "a" or "an" (i.e., singular forms) in defining an element throughout this document does not exclude the possibility of a plurality of such elements. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Unless specified otherwise, the term "connected" is used to designate direct electrical connections between circuit elements, while the term "coupled" is used to designate electrical connections between circuit elements that may be direct or via one or more other elements. In contrast, when an element is referred to as being "directly connected to" or "directly coupled to" another element, there are no intervening elements present. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. When referring to a voltage of a node or terminal, unless otherwise indicated, the voltage is considered to be the voltage between the node and a reference potential (typically ground). Further, when referring to the potential of a node or a terminal, the potential is considered to refer to a reference potential unless otherwise indicated. The voltage and potential of a given node or a given terminal will be further designated with the same reference numerals. A signal that alternates between a first logic state (e.g., a logic low state) and a second logic state (e.g., a logic high state) is referred to as a "logic signal". The high and low states of different logic signals of the same electronic circuit may be different. In particular, the high and low states of the logic signal may correspond to voltages or currents that may not be completely constant in the high or low states.

Fig. 1 provides a PFC circuitry based on FLYBACK according to an illustrative embodiment of the invention. In the PFC circuitry shown in FIG. 1, an AC voltage V is applied _AC Rectified by a rectifier and a capacitor C _IN After filtering, the voltage becomes input voltage V _IN . Input voltage V _IN PFC circuit with FLYBACK topological structure is used for correcting power factor and changing the corrected power factor into output voltage V _OUT . The PFC circuit of the FLYBACK topological structure comprises a transformer Trans, a main switching tube MS, a diode D and an output capacitor C _OUT An input current sampling circuit, a secondary current sampling circuit, an output voltage sampling circuit and a control circuit 100. The primary side of the transformer Trans is coupled with the input capacitor C _IN Between the positive terminal and the main switching tube MS; the secondary side of transformer Trans is coupled to output capacitor C via diode D _OUT And ground reference. As will be appreciated by those of ordinary skill in the art, in the FLYBACK topology, the secondary switch tube is illustrated asIn other embodiments, the secondary switch tube may also be a controllable semiconductor power switch device, as the primary switch tube MS. In the embodiment shown in fig. 1, the main switch MS is illustrated as an N-type Metal Oxide Semiconductor Field Effect Transistor (NMOSFET), but it will be understood by those skilled in the art that the main switch MS may also be other suitable controllable Semiconductor power switch devices.

In the embodiment shown in FIG. 1, the input current sampling circuit samples the input current I _IN I.e. the primary current of the transformer Trans and generating a representative input current I _IN Input current sampling signal Ics.

In the embodiment shown in fig. 1, the secondary current sampling circuit samples the current of the secondary side of the transformer Trans and generates a secondary current sampling signal I representing the current of the secondary side of the transformer Trans _FB 。

In the embodiment shown in fig. 1, the output voltage sampling circuit samples the output voltage V _OUT And generates a representative output voltage V _OUT Output voltage feedback signal V _FB 。

The control circuit 100 includes an error amplification circuit 11, a duty ratio adjustment signal generation circuit 12, an on time generation circuit 13, an off time generation circuit 14, and a logic circuit 15.

The error amplifying circuit 11 receives the output voltage feedback signal V _FB And feeds back the output voltage to the signal V _FB And comparing the signal with the first reference voltage signal to generate an error signal COMP. The error signal COMP represents the output voltage feedback signal V _FB And a first reference voltage.

A duty ratio adjusting signal generating circuit 12 for receiving the inverted signal of the control signal CTL

And an error signal COMP, and is based on the inverted signal of the control signal

And the error signal COMP generates the duty cycle adjustment signal Reg. In the field ofAs will be appreciated by those of ordinary skill in the art: inverse signal of control signal CTL

Refers to a signal that is logically complementary to the control signal CTL. The duty ratio adjusting signal Reg is used for adjusting the on-time and the off-time of the main switching tube MS, and further adjusting the on-duty ratio D and the switching period Ts of the main switching tube MS, so that the square D of the duty ratio ² The product of the switching period Ts and the product of the switching period Ts is kept constant, thereby realizing the function of power factor correction.

The on-time generation circuit 13 receives the error signal COMP, the control signal CTL, the duty ratio adjustment signal Reg, and the input current sampling signal Ics, and generates an on-time control signal T according to the error signal COMP, the control signal CTL, the duty ratio adjustment signal Reg, and the input current sampling signal Ics _ON For controlling the on-time of the main switching tube MS. In one embodiment, the on-time control signal T _ON Including high and low logic level signals, having an active state and an inactive state. In one embodiment, the logic low level is the on-time control signal T _ON The active state. In one embodiment, the control signal T is turned on _ON When changing from the active state (e.g. logic low level) to the inactive state (e.g. logic high level), the main switching tube MS is turned off. The on-time generating circuit 13 generates a minimum on-time ton _ min in response to the error signal COMP, the minimum on-time ton _ min being proportional to the error signal COMP. At the same time, the on-time generating circuit 13 will increase the on-time of the main switch transistor MS according to the value of the input current sampling signal Ics or keep the on-time of the main switch transistor MS at the minimum on-time ton _ min.

The turn-off time generation circuit 14 receives the duty ratio regulation signal Reg and the secondary side current sampling signal I _FB And according to the duty ratio regulation signal Reg and the secondary side current sampling signal I _FB Generating an off-time control signal T _OFF For controlling the off-time of the main switching tube MS. In one embodiment, the off-time control signal T _OFF Including high and low logic level signals, having an active state and an inactive state. In one embodimentLogic high level is off-time control signal T _OFF The active state. In one embodiment, the time control signal T is turned off _OFF When changing from an inactive state (e.g. a logic low level) to an active state (e.g. a logic high level), the main switch tube MS is turned on. The off-time generating circuit 14 generates a minimum off-time toff _ min, which is inversely proportional to the error signal COMP, according to the duty ratio adjusting signal Reg. At the same time, the off-time generation circuit 14 will also sample the signal I according to the output current _FB The value of (1) is increased by the turn-off time of the main switching tube MS or the turn-off time of the main switching tube MS is kept to be the minimum turn-off time toff _ min.

The logic circuit 15 receives the on-time control signal T _ON And off time control signal T _OFF And controls the signal T for the conduction time _ON And off time control signal T _OFF And performing logic operation to generate the control signal CTL. The control signal CTL is used to control the on and off switching of the main switching tube MS. In one embodiment, control signal CTL comprises a high-low logic level signal having an active state and an inactive state. In one embodiment, the logic high level is the active state of control signal CTL. In one embodiment, when the control signal CTL is in an active state (e.g., logic high level), the main switch MS is turned on; when the control signal CTL is in an inactive state (e.g., logic high level), the main switch tube MS is turned off.

Fig. 2 is a schematic diagram of waveforms according to an embodiment of the present invention. The figure shows an input voltage V _IN Waveform, input current I _IN Input current I _IN Sinusoidal envelope, input current I _IN And the waveform of the control signal CTL and the waveform of the average current Iavg.

As shown in fig. 2, the input current I _IN The maximum current Ip when the main switching tube MS is switched on can be expressed as:

wherein, L is the inductance of the primary side of the transformer Trans, D is the conduction duty ratio of the main switching tube MS, and Ts is the switching period. Thus, the input current I _IN Average current Ia ofvg can be expressed as:

as long as D is maintained ² X Ts is not changed, then the current I is inputted _IN Will follow the input voltage V _IN And changing to further realize power factor correction of the system.

At a certain error signal COMP, the main switching tube MS has a minimum on-time ton _ min and a minimum off-time toff _ min. Under normal conditions, due to the input voltage V _IN And an input current I _IN Is much smaller than the switching frequency of the main switching tube MS, so that at the input current I _IN The minimum on-time ton _ min and the minimum off-time toff _ min remain unchanged during the half-wave period of (a).

But at the input voltage V _IN At low, the main switch MS will extend the on-time from ton _ min to ton1 (ton 1 > ton _ min) due to the limitation of the minimum input current. To achieve power factor correction, the duty cycle adjustment signal generation circuit 12 in fig. 1 will extend the off-time of the main switch tube MS to toff1 (toff 1 > toff _ min) together with the off-time generation circuit 14 to maintain D1 ² X Ts1 and Normal case D ² The value of x Ts was unchanged. Wherein, the first and the second end of the pipe are connected with each other,

in addition, at the input voltage V _IN At a higher time, the main switch tube MS will prolong the turn-off time due to the limitation that the secondary side current must cross zero, and the turn-off time is prolonged from toff _ min to toff2 (toff 2 > toff _ min). To achieve power factor correction, the duty cycle adjustment signal generation circuit 12 in fig. 1 will extend the on-time of the main switch transistor MS to ton2 (ton 2 > ton _ min) together with the on-time generation circuit 13 to keep D2 ² X Ts2 and Normal case D ² The value of x Ts was unchanged. At this point in the process,

fig. 3 is a circuit schematic of the control circuit 100 according to an embodiment of the present invention. It should be noted that, in the embodiment shown in fig. 3, the error amplifying circuit 11, the duty ratio adjusting signal generating circuit 12, the on-time generating circuit 13, the off-time generating circuit 14, and the logic circuit 15 are all shown by using a specific implementation circuit, but those skilled in the art will understand that each specific implementation circuit is not unique, and each module may also be replaced by a circuit module that can implement the same function.

As shown in fig. 3, the error amplifying circuit 11 is illustrated as a voltage error amplifier EA. The voltage error amplifier EA has a positive input terminal and a negative input terminal, wherein the positive input terminal of the voltage error amplifier EA receives a first reference voltage signal V _REF (ii) a The inverting input terminal of the voltage error amplifier EA receives the output voltage feedback signal V _FB 。

The duty ratio adjustment signal generation circuit 12 includes a ramp signal generation circuit 121 and a ramp comparison circuit 122. The ramp signal generating circuit 121 includes a current source 20, a capacitor 21, a switch 22, an operational amplifier 23, a transistor 24, a resistor 25, a current mirror 26, a capacitor 27, and a pull-down current source 28.

The current source 20 and the capacitor 21 are coupled in series between the supply voltage VCC and ground reference. The switch 22 has a first terminal, a second terminal, and a control terminal. A first terminal of the switch 22 is coupled to a common node of the current source 20 and the capacitor 21; a second terminal of the switch 22 is coupled to ground; the control terminal of the switch 22 receives the inverse signal of the control signal

The operational amplifier 23, the transistor 24, the resistor 25 and the current mirror 26 function as a voltage-current converting circuit for converting the voltage signal on the capacitor 21 into a ramp current signal Iramp. Specifically, the operational amplifier 23 has a first terminal coupled to the first terminal of the switch 22, a second terminal electrically connected to the ground through the resistor 25, and an output terminal. Transistor 24 has a first terminal, a second terminal, and a control terminal. A first terminal of transistor 24 is coupled to a first terminal of current mirror 26; a second terminal of transistor 24 is coupled to ground; the control terminal of the transistor 24 is coupled to the output terminal of the operational amplifier 23. A second terminal of the current mirror 26 provides a ramp current signal Iramp.

The capacitor 27 has a first terminal and a second terminal. A first terminal of the capacitor 27 is coupled to the second terminal of the current mirror 26 for receiving the ramp current signal Iramp; a second terminal of the capacitor 27 is connected to ground.

The pull-down current source 28 has a first terminal, a second terminal, and a control terminal. A first terminal of the pull-down current source 28 is coupled to a second terminal of the current mirror 26; a second terminal of the pull-down current source 28 is connected to ground; a control terminal of the pull-down current source 28 receives the error signal COMP. The voltage signal on the capacitor 27 is the Ramp signal Ramp.

The ramp comparator circuit 122 is illustrated as a voltage comparator. The voltage comparator is provided with a positive phase input end and an inverted phase input end, wherein the positive phase input end of the voltage comparator receives the Ramp signal Ramp; the inverting input end of the voltage comparator receives a second reference voltage REF; the voltage comparator compares the Ramp signal Ramp with a second reference voltage Ref to generate a duty ratio adjustment signal Reg.

With continued reference to fig. 3, the on-time generating circuit 13 includes a minimum on-time generating circuit 31, a minimum current limiting circuit 32, and a logic gate circuit 33.

The minimum on-time generating circuit 31 receives the error signal COMP and the control signal CTL, and generates a minimum on-time signal TON _ MIN for determining the minimum on-time TON _ MIN of the main switch transistor MS according to the error signal COMP and the control signal CTL. The minimum on-time ton min is proportional to the error signal COMP.

The minimum current limiting circuit 32 is illustrated as a current comparator. The current comparator is provided with a positive phase input end and an inverse phase input end, wherein the positive phase input end of the current comparator receives an input current sampling signal Ics; the inverting input end of the current comparator receives a minimum input current threshold Imin; the current comparator compares the input current sampling signal Ics with a minimum input current threshold Imin to generate a current indication signal Ilimit. In one embodiment, the current indication signal Ilimit comprises a high-low logic level signal having an active state and an inactive state. In one embodiment, the logic high level is an active state of the current indication signal Ilimit, indicating that the input current sampling signal Ics is greater than the minimum input current threshold Imin.

The logic gate circuit 33 is illustrated as a logic and gate. The logic AND gate receives the duty ratio adjusting signal Reg, the current indicating signal Ilimit and the minimum conduction time signal TON _ MIN, and performs logic AND operation on the duty ratio adjusting signal Reg, the current indicating signal Ilimit and the minimum conduction time signal TON _ MIN to generate a conduction time control signal TON.

With continued reference to fig. 3, the off-time generating circuit 14 includes a current zero-crossing comparing circuit 41 and a second logic circuit.

The current zero crossing comparison circuit 41 is illustrated as a zero crossing comparator. The zero-crossing comparator is provided with a positive phase input end and an inverted phase input end, wherein the positive phase input end of the zero-crossing comparator receives a zero-crossing threshold Izero; the inverting input end of the zero-crossing comparator receives a secondary side current sampling signal I _FB (ii) a The zero crossing comparator samples a zero crossing threshold Izero and a secondary side current sampling signal I _FB And comparing to generate a zero-crossing indication signal ZCD. In one embodiment, the zero crossing indication signal ZCD comprises a high and low logic level signal having an active state and an inactive state. In one embodiment, the logic high level is an active state of the zero crossing indication signal ZCD, representing the secondary side current sampling signal I _FB Down to the zero crossing threshold Izero. It will be appreciated by those skilled in the art that the zero-crossing threshold Izero is ideally zero, but actually is a reference value slightly greater than zero.

The second logic circuit is illustrated as comprising an inverter 42 and a logic and gate 43. The inverter 42 receives and inverts the duty cycle adjusting signal Reg to generate an inverted signal

The logic AND gate 43 receives the zero crossing indication signal ZCD and the inverted signal

And most preferably to the zero crossing indication signal ZCD and the inverted signal

Performing logic AND operation to generate a turn-off time control signal T _OFF 。

The logic circuit 15 is illustrated as an RS flip-flop. The RS trigger comprises a set terminal S, a reset terminal R, a first output terminal Q and a second output terminal

The set terminal S of the RS trigger receives the control signal T of the turn-off time _OFF (ii) a The reset terminal R of the RS trigger receives the on-time control signal T _ON (ii) a A first output end Q of the RS trigger outputs a control signal CTL; second output end of RS trigger

Outputting an inverted control signal

Fig. 4 is a schematic diagram illustrating a partial signal waveform of the control circuit 100 according to an embodiment of the present invention. Fig. 4 illustrates, from top to bottom, the waveform of the control signal CTL, the waveform of the Ramp signal Ramp, the waveform of the reference signal Ref, the waveform of the duty ratio adjustment signal Reg, and the on-time control signal T in this order _ON Waveform of (2), inverted signal

And the waveform of the zero-crossing indication signal ZCD.

The operating principle of the control circuit 100 will be described next in connection with fig. 4 and 3. Under normal operating conditions (e.g., period TS), the input current sampling signal Ics is greater than the minimum input current threshold Imin. The minimum on-time ton _ min of the main switch tube MS is generated by the minimum on-time generation circuit 31 according to the error signal COMP. In the case of a constant error signal COMP, the minimum off-time toff _ min is also constant. But at an input voltage V _IN At a low time (such as period TS 1), the main switch tube MS will prolong the conduction time due to the limitation of the minimum input current threshold Imin, and during conductionThe interval ton _ min is extended to ton1, and the extended on-time is shown as Δ ton1. That is, in the period TS1, the on-time control signal T _ON The low state of (c) is extended.

Control signal T at on-time _ON During the low level state of the capacitor 27, the control signal CTL is in the high level state, the switch 22 in the Ramp signal generating circuit 121 is turned off, the current source 20 charges the capacitor 21, the operational amplifier 23, the transistor 24, the capacitor 25 and the current mirror 26 work cooperatively to convert the voltage on the capacitor 21 into the Ramp current signal Iramp, the Ramp current Iramp charges the capacitor 27, and the voltage signal on the capacitor 27 is the Ramp signal Ramp. Control signal T at on-time _ON The Ramp signal Ramp rises in a squared relationship with time during the low state of (2). When the on-time ton1 is reached, the on-time control signal T _ON When the low level state is changed into the high level state, the control signal CTL is changed from the high level state into the low level state, and the main switching tube MS is switched off. The voltage on capacitor 27 is discharged by pull-down current source 28 and Ramp signal Ramp decreases in inverse proportion to time, with the slope of the decrease being controlled by error signal COMP. When the error signal COMP is constant, the discharge rate is constant. In one embodiment, the value of the current discharged by capacitor 27 through pull-down current source 28 is proportional to error signal COMP. The larger the error signal COMP, the larger the current discharged from the capacitor 27 through the pull-down current source 28, and the larger the falling slope of the Ramp signal Ramp.

When the Ramp signal Ramp falls to the second reference voltage REF, the duty ratio regulation signal Reg changes from a high level state to a low level state, and the inverted signal

The low level state is changed into the high level state, and the zero crossing indication signal ZCD is also in the high level state at this time, so that the control signal CTL is changed from the low level state into the high level state, and the main switch tube MS is turned on. During period TS1, the off time is also extended from toff _ min to toff1, the extended off time being Δ toff1. It is estimated that the extended off time Δ toff1 is square to the extended on time Δ ton1. Therefore, the average current Iavg can still be ensured to follow the outputInput voltage V _IN And the power factor correction function is good.

Fig. 5 is a schematic diagram of a partial signal waveform of the control circuit 100 according to another embodiment of the present invention. Fig. 5 shows, in order from top to bottom, the waveform of the control signal CTL, the waveform of the Ramp signal Ramp, the waveform of the reference signal Ref, the waveform of the duty ratio adjustment signal Reg, and the inverted signal

Waveform of (2), on-time control signal T _ON And the waveform of the zero-crossing indication signal ZCD.

The operating principle of the control circuit 100 will be described next in connection with fig. 5 and 3. Similar to the illustration of fig. 4, under normal operation conditions (e.g. period TS), the main switch MS maintains the minimum on-time ton _ min and the minimum off-time toff _ min with the error signal COMP unchanged. But at the input voltage V _IN When the current is higher, the main switching tube MS can prolong the turn-off time as the requirement of meeting the limitation of transformer Trans secondary side current zero crossing is met. As shown in fig. 5, when the Ramp signal Ramp falls to the second reference voltage Ref, since the zero-crossing indication signal ZCD is in a low level state (the secondary side current is not zero), the main switching tube MS will continue to be turned off for a time Δ toff2 until the high level state of the zero-crossing indication signal ZCD is reached, and the main switching tube MS is turned on.

The duty ratio regulation signal Reg regulates the conduction time of the main switch tube MS, and when the conduction time controls the signal T _ON And the main switching tube MS is switched off when the duty ratio regulation signal Reg is high. Referring to the illustration of period TS2 in fig. 5, the on time of the main switch tube MS is extended to ton2, so as to correspond to the extension of the off time of the main switch tube MS. Therefore, the average current Iavg can still be ensured to follow the input voltage V _IN And the power factor correction function is good.

As shown in fig. 6, the minimum on-time generation circuit 31 includes a controllable current source 311, a capacitor 312, a switch 313 and a voltage comparator 314. The controllable current source 311 has a first terminal, a second terminal, and a control terminal, the first terminal is connected to the supply voltage VCC, and the control terminal receives the error signal COMP. The capacitor 312 has a first terminal coupled to the second terminal of the controllable current source 311 and a second terminal connected to the ground. The switch 313 has a first terminal coupled to the first terminal of the capacitor 312, a second terminal connected to the ground reference, and a control terminal receiving the control signal CTL. The voltage comparator 314 has a first input terminal coupled to the first terminal of the capacitor 312, a second input terminal coupled to the predetermined voltage VD, and an output terminal, wherein the voltage comparator 314 compares the voltage on the capacitor 312 with the predetermined voltage VD to generate the minimum on-time signal TON _ MIN.

Fig. 7 illustrates a circuit schematic of the error amplifying circuit 11 shown in fig. 3 according to another embodiment provided by the present invention. In the embodiment shown in fig. 7, the error amplification circuit 11 includes a low-pass filter 110 in addition to the voltage error amplifier EA. The low-pass filter 110 is configured to perform low-pass filtering on the signal EAO output by the error amplifier EA and then output an error signal COMP. In this way, the value of the error signal COMP during one low frequency half-wave period remains unchanged.

Fig. 8 illustrates a PFC control method according to an embodiment of the present invention. The PFC control method may be used for the PFC circuitry in the illustrated embodiment described above. As shown in fig. 8, the PFC control method includes steps S1 to S6.

Step S1: according to the output voltage feedback signal V _FB A minimum on-time ton min and a minimum off-time toff min are generated.

Step S2: determining the input current V _IN Whether greater than a minimum input current threshold Imin.

And step S3: if the input current V is _IN And if the input current is larger than the minimum input current threshold Imin, controlling the main switching tube to be conducted for the minimum conducting time ton _ min and the minimum turn-off time toff _ min.

And step S4: if the input current V _IN If the minimum input current threshold Imin is less than the minimum input current threshold Imin, the conduction time of the main switching tube MS is prolonged until the input current V _IN Greater than a minimum input current threshold Imin. The extended on-time is denoted as ton1 (ton 1 > ton _ min), while the main switching tube MS is extended off-time to toff1 (toff 1 > toff _ min). In one embodiment, the extended on-time Δ ton1 (Δ ton1= ton1-ton _ min) is related to the magnitude of the input current. In one embodiment, the extended off-time Δ toff1 (Δ toff1= toff1-toff _ min) is determined by generating a Ramp signal Ramp. The value of the rising edge of the Ramp signal Ramp and the conduction time of the main switching tube MS form a square relation; the value of the falling edge of the Ramp signal Ramp is inversely proportional to the off time of the main switching tube MS.

Step S5: and judging whether the secondary side current is reduced to zero or not.

Step S6: and if the secondary side current is reduced to zero, judging whether the turn-off time of the MS of the main switching tube is more than or equal to the minimum turn-off time toff _ min.

Step S7: and if the turn-off time of the main switching tube MS is equal to the minimum turn-off time toff _ min, controlling the main switching tube MS to be conducted for the minimum turn-on time ton _ min.

Step S8: if the main switch tube MS is off for more than the minimum off-time toff _ min (if toff2, toff2 > toff _ min is assumed), the on-time of the main switch tube MS is extended, and the extended on-time is indicated as ton2 (ton 2 > ton _ min). In one embodiment, the extended off-time Δ toff2 (Δ toff2= toff2-toff _ min) is compared with the secondary side current sample signal I _FB Is related to the size of the cell. In one embodiment, the extended on-time Δ ton2 (Δ ton2= ton2-ton _ min) is determined by generating a Ramp signal Ramp. The value of the rising edge of the Ramp signal Ramp and the conduction time of the main switching tube MS form a square relation; the value of the falling edge of the Ramp signal Ramp is inversely proportional to the off time of the main switching tube MS.

While the present invention has been described with reference to several exemplary embodiments, it is understood by those of ordinary skill in the relevant art that the terminology used in the embodiments disclosed is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Furthermore, various modifications in form and detail of the disclosed embodiments of the invention may occur to those skilled in the art without departing from the spirit and concept of the invention and, therefore, such modifications are intended to be included within the scope of the present invention as defined in the appended claims and their equivalents.

Claims

1. A control circuit for a FLYBACK-based power factor correction circuit, comprising:

the error amplifying circuit receives a voltage feedback signal representing the output voltage of the power factor correction circuit, compares the voltage feedback signal with a first reference voltage and generates an error signal, and the error signal represents the difference value of the voltage feedback signal and the first reference voltage;

the duty ratio adjusting signal generating circuit receives an inverted signal and an error signal of the control signal and generates a duty ratio adjusting signal according to the inverted signal and the error signal of the control signal, wherein the control signal is used for controlling the on-off switching of a main switching tube in the power factor correction circuit;

the on-time generating circuit receives the error signal, the control signal, the duty ratio adjusting signal and the input current sampling signal and generates an on-time control signal according to the error signal, the control signal, the duty ratio adjusting signal and the input current sampling signal, wherein the input current sampling signal represents the input current of the power factor correction circuit;

the turn-off time generating circuit receives the duty ratio adjusting signal and the secondary side current sampling signal and generates a turn-off time control signal according to the duty ratio adjusting signal and the secondary side current sampling signal, wherein the secondary side current sampling signal represents the current flowing through the secondary side of the transformer in the power factor correction circuit; and

and the logic circuit receives the on-time control signal and the off-time control signal and performs logic operation on the on-time control signal and the off-time control signal to generate a control signal.

2. The control circuit of claim 1, wherein the duty cycle adjustment signal generation circuit comprises:

the ramp signal generating circuit receives the inverted signal and the error signal of the control signal and generates a ramp signal according to the inverted signal and the error signal of the control signal, wherein the rising time of the ramp signal determines the on-time of the main switching tube, and the falling time of the ramp signal determines the off-time of the main switching tube; and

and the ramp comparison circuit receives the ramp signal and compares the ramp signal with the second reference voltage to generate a duty ratio regulation signal.

3. The control circuit of claim 2, wherein the ramp signal rises by a value squared with the on-time of the main switching transistor and falls by a value inversely proportional to the off-time of the main switching transistor.

4. The control circuit of claim 1, wherein the on-time generation circuit comprises:

the minimum on-time generating circuit receives the error signal and the control signal and generates a minimum on-time signal according to the error signal and the control signal;

the minimum current comparison circuit receives the input current sampling signal, compares the input current sampling signal with a minimum current threshold value and generates a current indication signal; and

and the first logic circuit receives the minimum conduction time signal, the current indicating signal and the duty ratio adjusting signal, performs logic operation on the minimum conduction time signal, the current indicating signal and the duty ratio adjusting signal and generates a conduction time control signal.

5. The control circuit of claim 4 wherein the duration of the active state of the minimum on-time signal is directly proportional to the error signal.

6. The control circuit of claim 1, wherein the off-time generating circuit comprises:

the current zero-crossing comparator receives the secondary side current sampling signal and compares the secondary side current sampling signal with a zero-crossing threshold value to generate a zero-crossing indication signal; and

and the second logic circuit receives the zero-crossing indication signal and the duty ratio regulation signal, performs logic operation on the zero-crossing indication signal and the duty ratio regulation signal and generates a turn-off time control signal.

7. The control circuit of claim 2, wherein the ramp signal generating circuit comprises:

a first current source;

the first capacitor is provided with a first end and a second end, the first end of the first capacitor is coupled with the first current source, and the second end of the first capacitor is connected with the reference ground;

the first end of the ramp switch is coupled with a common node of the first current source and the first capacitor, the second end of the ramp switch is connected with the reference ground, and the control end of the ramp switch receives an inverted signal of the control signal;

the conversion circuit receives the voltage signal on the first capacitor, converts the voltage signal on the first capacitor into a ramp current signal and outputs the ramp current signal at the output end;

the second capacitor is coupled between the output end of the conversion circuit and the reference ground; and

and the second current source is provided with a first end, a second end and a control end, the first end of the second current source is coupled with the output end of the conversion circuit, the second end of the second current source is connected with the reference ground, the control end of the second current source receives the error signal, and the voltage on the second capacitor is the ramp signal.

8. The control circuit of claim 7, wherein a value of current discharged by the second capacitor through the second current source is directly proportional to the error signal.

9. A power factor correction method based on a FLYBACK circuit comprises the following steps:

generating an error signal according to a voltage feedback signal, wherein the voltage feedback signal represents the output voltage of the FLYBACK circuit, and the error signal represents the difference value between the voltage feedback signal and a first reference voltage;

generating a duty ratio adjusting signal according to an inverted signal and an error signal of a control signal, wherein the control signal is used for controlling the conduction and the turn-off switching of a main switching tube in the FLYBACK circuit;

generating a conduction time control signal according to the error signal, the control signal, the duty ratio adjusting signal and the input current sampling signal, wherein the input current sampling signal represents the input current of the FLYBACK circuit;

generating a turn-off time control signal according to the duty ratio adjusting signal and a secondary side current sampling signal, wherein the secondary side current sampling signal represents the current flowing through the secondary side of a transformer in the FLYBACK circuit; and

and performing logic operation on the on-time control signal and the off-time control signal to generate a control signal.

10. A power factor correction method based on a FLYBACK circuit comprises the following steps:

generating the minimum on-time and the minimum off-time of a main switching tube in the FLYBACK circuit according to a voltage feedback signal, wherein the voltage feedback signal represents the output voltage of the FLYBACK circuit;

judging whether the input current of the FLYBACK circuit is larger than a minimum input current threshold value or not;

when the input current of the FLYBACK circuit is larger than the minimum current threshold value, controlling the main switching tube to be conducted for minimum conduction time and to be switched off for minimum turn-off time;

when the input current of the FLYBACK circuit is smaller than the minimum current threshold value, prolonging the conduction time of a main switching tube to a first conduction time, and prolonging the turn-off time of the main switching tube to a first turn-off time, wherein the first conduction time is longer than the minimum conduction time, and the first turn-off time is longer than the minimum turn-off time;

judging whether the secondary side current is reduced to zero or not;

if the secondary side current is reduced to zero, judging whether the turn-off time of the main switching tube is more than or equal to the minimum turn-off time;

if the turn-off time of the main switching tube is equal to the minimum turn-off time, controlling the main switching tube to be conducted for the minimum turn-on time; and

and if the turn-off time of the main switching tube is greater than the minimum turn-off time, prolonging the turn-on time of the main switching tube to a second turn-on time, wherein the second turn-on time is greater than the minimum turn-on time.