CN1149364A - Parameter sampling apparatus - Google Patents

Abstract

Apparatus for sampling a signal parameter of a plurality of data signals comprises a plurality of data signal sources. Each data signal includes sequentiald ata groups. Each group has the same fixed predetermined time duration, and includes sequential data blocks. The parameter determining circuits are each responsive to a respective one of the data signals and produce sequential signals to represent the signal parameter. A data sampler is responsive to the plurality of accumulators to sample the cumulative parameter representative signals from all of the accumulators substantially simultaneously at time intervals equal to the fixed predetermined time duration, to reset all of the accumulators to zero and to generate the control signal.

Description

Parameter sampling apparatus

The present invention relates to be used for device with the signal sampling of the parameter of a plurality of each data-signal of data-signal of representative.

Sometimes need the signal parameter (for example, codec complexity) of each in a plurality of data-signals is sampled.If all data-signals are phase mutually synchronization, this just relates to simply provides response data signal, be used to produce the corresponding signal of the signal parameter of designate data signal, and in the suitable moment determinator to these parameter representation signals sampling.Yet, asynchronous at data-signal, but need to control under the situation of processing of all data-signals according to the correlation of each signal parameter, be necessary in all data-signals, side by side signal parameter to be sampled basically.In this case, the sampling to signal parameter is a problem.

In a system as example, be transferred to each television receiver in the user family by the broadcasting satellite circuit from a plurality of vision signals that may be each passage of TV network feed, TV station or other video source.Each vision signal can be encoded as the signal that is formed by the data sequence group, and every group comprises the continuous videos image of representing fixed qty or the data that are called as one group of image (GOP) of frame.When each group in all data-signals had same fixing predetermined time period (equaling the duration of the quantity of video image in this group or frame), the sequential of the group that the different video signal is interior was nonsynchronous.

In this system, be combined at headend station from the data of different passages, promptly be multiplexed into single data flow.This multiplexed data flow is sent to the station, rear end in the transmission link such as lead, optical fiber or radio link (as a satellite circuit) class, to separate from the passage of the data of multiplexed data stream at this, be that multichannel is decomposed, offer the recipient of expection then.One satellite circuit as example comprises the Digital Transmission path of can per second transmitting 24 megabits (Mbps).For efficient and the purposes maximum that makes this circuit, need share this circuit by a plurality of vision signals.For example, may wish to share above-mentioned satellite link by at least six video channels.

The bit rate that has proposed the multiplex signal that will be propagated by satellite circuit is given different passages according to the present encoding complexity dynamic assignment of the image of these channels spread.All passages just are being transmitted the codec complexity of image and are calculating on the basis of GOP, and are sampled simultaneously basically.Relation according to total coding complexity of the present encoding complexity of this passage and all passages is given each passage with the pro rate of total bit rate of transmission line.The coding of next GOP of every passage is based on the bit rate that dynamic assignment is given that passage.

The inventor has recognized that each GOP comprises that each representative is transmitted a frame of image or a plurality of alphabetic data pieces of a picture, and can produce a complexity representative signal for each such piece.The inventor further recognizes, represents the signal of the complexity of a GOP to represent to be worth by the complexity of each piece among this GOP that adds up (being frame or picture) and produces.The inventor also recognizes, when producing GOP complexity value, as long as will add up from the complexity value of the piece (being frame or picture) of equal number in each vision signal, and after each sampling, accumulator is resetted, if these pieces are not all to reside among the same GOP, then can not bring adverse influence to GOP complexity value.This same principle generally can be applicable to have any data parameters sampling system of these characteristics.

The purpose of this invention is to provide the device that is used for the signal parameter sampling of a plurality of data-signals, it comprises a plurality of data signal sources, each data-signal comprises the alphabetic data group, and every group of data in each data-signal have same fixing predetermined time period, and comprise the alphabetic data piece.A plurality of parameters determine that circuit respectively responds a corresponding data-signal, and produce to have and represent in the corresponding data signal sequential signal of the signal parameter of each piece in the alphabetic data piece.In each response parameter representation signal of a plurality of accumulators corresponding one, and produce the signal of the parameter value that adds up of designate data signal.A data sampler responds a plurality of accumulators, and fixedly the time interval of predetermined time period side by side samples basically to the parameter representation signal that adds up from all accumulators to equal.

Can side by side sample basically according to system of the present invention, and these data-signals do not require it is synchronous, only need be made up of the data set with fixing predetermined time period signal parameter from a plurality of data-signals.In above-mentioned example, utilize according to sampling system of the present invention to allow in a plurality of vision signals, and do not require that they are synchronous according to the bit rate in their the instantaneous codec complexity dynamic assignment multiplexed data stream.

Fig. 1 is the block diagram according to multiplex system of the present invention;

Fig. 2 is the block diagram that can be used in the channel processor in the multiplex system shown in Figure 1;

Fig. 3 is the block diagram that can be used in the part of the mpeg encoder in the channel processor shown in Figure 2;

Fig. 4 is the block diagram that can be used in the bit rate distributor in the multiplex system shown in Figure 1;

Fig. 5 is the more detailed block diagram that can be used in the complexity analyzing device in the channel processor shown in Figure 2; And

Fig. 6,7 and 8 is expression sequential charts to the sampling of complexity information.

Fig. 1 is the block diagram in conjunction with multiplex system of the present invention.In Fig. 1, all signal paths all are expressed as single-signal-line.But, those skilled in the art will be appreciated that represented signal path can transmit multistation digital signal, or parallel convey, signal path can be made up of a plurality of holding wires in this case, or serial transfer, signal path can be the forms data line and/or comprise data and clock cable in this case.From this figure, deleted for simplicity and understood other control and clock signal path that the present invention has nothing to do.

In Fig. 1, a plurality of inputs 5 are coupled to the source (not shown) of the vision signal (passage 1-passage K) that will transmit together on a data link.These a plurality of inputs 5 are connected to the corresponding data input of corresponding a plurality of channel processors 10.Each data output end of a plurality of channel processors 10 is connected to multiplexer (MUX) 20 corresponding data input 1-K.The data output end of multiplexer 20 is connected to the output 15 of multiplex system.Output 15 is connected to the application circuit (not shown) that is used for transmitting multiplexed data flow (multiplexed data) on transmission link.

In a plurality of channel processors 10 each also comprises a complexity output and a control input end.The corresponding complexity output of each is connected to the corresponding complexity input of bit rate distributor 30 in a plurality of channel processors, and the corresponding quota output of bit rate distributor 30 is connected to the corresponding control input end of a plurality of channel processors 10.

During work, each channel processor receives the signal of representing next quota period allocated to give its bit rate in its control input end.This channel processor will be encoded to digitally encoded signal with the bit rate that distributes at the signal in next quota cycle of its data input pin then.Encoded data signals offers the corresponding input of multiplexer 20.Multiplexer 20 is operated in known manner, will being multiplexed data flow from the signal combination of all channel processors.Still in a known way multiplexed data flow is offered the circuit that comprises the data link that is used to transmit then.

In cataloged procedure, channel processor 10 produces the be encoded signal of codec complexity of signal of expression at its complexity output.Bit rate distributor 30 receives the signal from the complexity output of channel processor 10, and dynamically regulates the bit rate quota in next quota cycle in a plurality of channel processors 10 according to all complexity signals.In a preferred embodiment, complicated signal is distributed higher bit rate relatively than not too complicated signal dynamics.The distinct methods of determining the vision signal complexity and distributing bit rate according to this complexity is described below.

Fig. 2 is the block diagram that can be used on the channel processor in the multiplex system shown in Figure 1.In Fig. 2, represent with identical label with the similar parts of parts among Fig. 1, and be not explained in detail hereinafter.Data input pin 5 is connected to the video signal source (not shown) in Fig. 2.Data input pin 5 is connected to the data input pin and the complexity analyzing device 16 of constant bit rate encoders (CBR) 14.The data output end of CBR encoder 14 is connected to the input of multiplexer (MUX) 20 (Fig. 1).The control input end of channel processor 10 (control) is connected to the quota input Q of CBR encoder 14.The output of complexity analyzing device 16 is connected to the complexity output (complexity) of channel processor 10.

During work, complexity analyzing device 16 is analyzed the complexity of the vision signal of data input pin 5.Output at complexity analyzing device 16 produces the signal of representing the input signal complexity.This complexity representation signal is provided to bit rate distributor 30 (Fig. 1).Respond this complexity signal (and those signals of other channel processor 10), bit rate distributor 30 provides the signal of representing the bit rate of distributing to this channel processor 10 to this channel processor 10 control input end (control) of (with other channel processor 10).CBR encoder 14 provides data path at its data input pin and generation between the data output end with the output signal of Constant Bit Rate coding.Set Constant Bit Rate according to the signal that is input to quota input Q from bit rate distributor 30 from the control input end (control) of channel processor 10.

Might complexity analyzing device 16 at the circuit that carries out also using when it is analyzed in the CBR encoder 14.In this case, as shown in phantom in Figure 2, data directly offer complexity analyzing device 16 in CBR encoder 14.This data of CBR encoder 14 can be replenished the data from input 5, or substitute it fully, and the complexity analyzing device directly is not connected with data input pin 5 in this case.

In a preferred embodiment, each CBR encoder 14 is the standard announced according to Motion Picture Experts Group (MPEG) encoders to video signal compression and coding, is referred to as mpeg encoder.Fig. 3 is the block diagram of the part of expression one mpeg encoder 14.Below the known tip assemblies of mpeg encoder 14 will be described in detail.Mpeg encoder is comprised with understand other parts that the present invention has nothing to do, left out them for simplicity in the figure.

In Fig. 3, the data input pin 5 of mpeg encoder 14 (data input) is connected to video signal source (not shown) to be compressed and coding.Input 5 is connected to the input of frame buffer 41.Frame buffer 41 comprises a plurality of frame period buffers or delay line and a plurality of output, and this output produces each signal of the part of different but temporarily adjacent frame of expression or image.A plurality of outputs of frame buffer 41 are connected to the corresponding input of motion estimator 42.The output of motion estimator is connected to discrete cosine transform (DCT) circuit 43.The output of DCT circuit 43 is connected to the data input pin of variable quantization device (Qu) circuit 46.The output of variable quantization device circuit 46 is connected to the input of variable length coder (VLC) 47.The output of VLC47 is connected to the input of output buffer 48.The data output end of output buffer 48 is connected to the data output end (data output) of mpeg encoder 14.The data output end of mpeg encoder 14 (data output) is connected to the corresponding input of multiplexer 20 (Fig. 1).

The state output end of output buffer 48 is connected to the state input of bit rate adjuster 49.The control output end of bit rate adjuster 49 is connected to the control input end of variable quantization device 46.The quota input Q of mpeg encoder 14 is connected to the corresponding quota output of bit rate distributor 30.The quota input Q of mpeg encoder 14 is connected to the control input end of adjuster 49.

In when work, mpeg encoder 14 operate in a known way, so as to its input next by norm the vision signal in cycle compress with the determined bit rate of the signal of its Q input and encode.In following example, the mpeg encoder to the encoding video signal that is divided into the group of being made up of 12 images or frame (GOP) is described.Yet should understand the image among the GOP or the quantity of frame may change.In addition, in following example, suppose that the bit rate of each mpeg encoder is assigned as every GOP renewal once, promptly the quota cycle is the GOP cycle.But, will also be understood that quota also may be different in the cycle, and itself in addition can change in time.

Frame buffer 41 receives in mode described below and storage representation need carry out 12 frame partial data among the demonstration GOP that just is carried out coding of estimating motion.These data offer motion estimator 42.In a preferred embodiment, first in 12 images or the frame is used as reference frame (I frame), and through motion estimator to DCT circuit 43.For remaining frame, each piece that relatively is called in the mpeg standard document in each image of macro block or the pieces that a plurality of 16 pixels in the frame multiply by 16 row produces motion vector in motion estimator 42, or they are separately from previous frame (P frame), perhaps from previous frame and the two interpolation of subsequent frame (B frame).As mentioned above, frame buffer 41 is preserved the required data of motion estimator, to realize from previous frame or from the valuation of previous frame and subsequent frame interpolation.Then the motion vector of the concrete frame that is produced with just compared by the real data in the frame of valuation, produce the differences in motion value signal, and offer DCT circuit 43.

In DCT circuit 43, according to the mpeg standard document, take advantage of 16 row macro blocks and be divided into piece (four luminance block that six 8 pixels are taken advantage of 8 row from 16 pixels of the spatial data of I frame from the differences in motion value signal of P frame and B frame, and the chrominance block of two double samplings), be called macro block at the remainder of this application.Each macro block is carried out discrete cosine transform.Resulting 8 take advantage of 8 DCT coefficients to offer variable quantization device 46 subsequently.8 take advantage of 8 coefficients be quantized, with zigzag order scanning and be provided to VLC47.DCT coefficient after the quantification utilizes the run-length encoding method to encode in VLC47 with other supplementary of representing GOP (with the relating to parameters of coding GOP), and is provided to output buffer 48.

Known control VLC47 output bit rate and to keep the institute of mpeg encoder 14 to distribute the direct mode of Constant Bit Rate thus be to control the quantification progression that is used to quantize each DCT coefficient block in the variable quantization device 46 (or in other words, quantization step).The control signal that offers variable quantization device 46 from bit rate adjuster 49 is carried out this controlled function.At one is that quota from the cycle between the continuous bit rate quota update signal of bit rate distributor 30 (Fig. 1) is in the cycle, bit rate adjuster 49 offers control signal variable quantization device 46 in known manner, it will change among the GOP per 16 and take advantage of 16 macro blocks to be carried out the quantification progression of quantification, so as to keep this quota cycle distribute bit rate.In following described mode, according to the codec complexity value of the vision signal of every passage in a plurality of passages, the bit rate of bit rate adjuster 49 is distributed in each GOP cycle and changes in this example.

In a preferred embodiment, bit rate distributor 30 (Fig. 1) is to have the computer system that is connected to the connector of various circuit blocks in a plurality of channel processors 10.Fig. 4 is the hardware block diagram that constitutes bit rate distributor 30.In Fig. 4, microprocessor (μ P) 31 is connected to read/writable memory device (RAM) 32 by computer system bus 35, read-only memory (ROM) 33 and I/O (I/O) controller 34.Also have other computer system part,, do not illustrate in the drawings in order to simplify such as mass storage device and user terminal.I/O controller 34 has the input (complexity) of a plurality of corresponding complexity outputs that are connected to a plurality of channel processors 10 (Fig. 1) and is connected to a plurality of outputs (by norm) of the corresponding quota input of a plurality of channel processors 10.

Microprocessor 31, RAM32, ROM33 and I/O controller 34 are in a known way as computer working, execution is stored in the program among the ROM33, store and retrieve the data among the RAM32, and receive data and transmit data to these devices from the device that attaches to I/O controller 34.The data of representing the present encoding complexity of the vision signal of just encoding in a plurality of channel processors 10 (Fig. 1) are to receive at the corresponding output of I/O controller 34 from these channel processors through " complexity " input in mode described below.For example poll, interruption untill further notice are received this data to microprocessor 31 in a known way.Microprocessor 31 machine system bus 35 is as calculated retrieved these signals from I/O controller 34, determine the position quota in next quota cycle of every encoder, and will represent that in next quota cycle the signal of these quotas offers a plurality of channel processors 10 through " by norm " output.

For each image of GOP or all macro blocks in the frame, be used for determining that the best approach of the codec complexity of the vision signal of encoding with mpeg encoder 14 (Fig. 3) is to utilize per 16 to take advantage of the quantitative calibration factor of 16 macro blocks (to be marked as Q _MB) and the figure place of this macro block that is used to encode (be marked as T _MB).Fig. 5 is the bit rate adjuster 49 and the block diagram of generation according to the complexity analyzing device 16 (Fig. 2) of the codec complexity representation signal of this method of mpeg encoder 14 (Fig. 3).For simplifying this figure, various clocks and control signal have been deleted among Fig. 5.Yet those signals that need and their required sequential and voltage characteristic are intelligible.

Complexity analyzing device 16 shown in Figure 5 is examples that only are used to as shown in phantom in Figure 2 from the complexity analyzing device of the information of CBR encoder 14.In Fig. 5, bit rate adjuster 49 has the state input T of the state output end that is connected to output buffer 48 (Fig. 3) _MBThe control output end Q of bit rate adjuster 49 _MBBe connected to the control input end of variable quantization device 46 (Fig. 3).Bit rate adjuster 49 also has the control input end (Q) of the corresponding quota output that is connected to bit rate distributor 30 (Fig. 1).

The state input T of bit rate adjuster 49 _MBBe also connected to the first input end of first adder 92.The output of first adder 92 is connected to the input of first latch 93.The output of first latch 93 is connected to the first input end of multiplier 94 and second input of first adder 92.The output of multiplier 94 is connected to the input of second latch 95.The output of second latch 95 is connected to codec complexity output X _PicCodec complexity output X _PicBe connected to the corresponding complexity input of bit rate distributor 30 (Fig. 1).

The control output end Q of bit rate adjuster 49 _MBAlso be coupled to the first input end of second adder 96.The output of second adder 96 is coupled to the input of the 3rd latch 97.The output of the 3rd latch 97 is coupled to the molecule input N of divider 98 and second input of second adder 96.The output of divider 98 is coupled to second input of multiplier 94.Register 99 has the output that is coupled to divider 98 denominator input D.

During work, for each macro block, bit rate adjuster 49 produces the quantitative calibration factor signal Q of variable quantization device 46 in known manner according to present bit speed quota and the figure place that is used for previous image encoding _MB, receive expression from output buffer 48 then and be used for figure place T this macroblock coding _MBSignal.Variable quantization device 46 (Fig. 3) is according to the quantitative calibration factor Q _MBQuantize the DCT coefficient in each macro block.The quantitative calibration factor Q _MBRepresent quantization step, or the percentage of the whole dynamic range of DCT coefficient in each quantized level.The Q of big value _MBThere is bigger quantization step in expression, and therefore, quantized level is less.Otherwise, the Q of little value _MBThere is less quantization step in expression, and therefore, quantized level is more.In a preferred embodiment, Q _MBIt is one five integer (having the numerical value between 1 to 31).

The average quantization scale factor of all macro blocks (is marked as Q in a complete image or frame _Pic) be calculated as follows.In the beginning of each frame or image, responding a reset signal (not shown) is clearly zero with latch 93 and 97.The combination of second adder 96 and the 3rd latch 97 as an accumulator job so that continuously will be from the macro block quantitative calibration factor Q of bit rate adjuster 49 _MBSummation.Simultaneously, the combination of the first adder 92 and first latch 93 as accumulator work with continuously to so far being used for figure place summation to image or frame coding.

All macro blocks in handling frame or image (are indicated as N _MBQuantity) after, latch 97 comprises all macro block quantitative calibration factor Q that bit rate adjuster 49 produces _MBSum, latch 93 comprise all T that are used for image or frame coding _PicSum.Divider 98 produces all macro block quantitative calibration factor Q in image or the frame _MBSum is by macroblock number N in image or the frame _MBThe merchant who removes.This merchant is the average quantization scale factor Q in this frame or the image _PicMultiplier 94 produces Q _PicAnd T _PicLong-pending, it (is indicated as X for the codec complexity of this image _Pic), i.e. X _Pic=T _Pic* Q _PicWhen image or frame end, the response clock signal (not shown) is with codec complexity signal X _PicBe latched in second latch 95.Repeat above-mentioned circulation for each image in the vision signal of just encoding or frame then.

Then with codec complexity X _PicBe provided to the complexity input of the I/O controller 34 of bit rate distributor 30 (Fig. 4) from latch 95, remain processing, to obtain the codec complexity of GOP.The codec complexity of GOP (is indicated as X _GOP) be the X of all images among this GOP _PicAnd.(square journey (1)). μ P31 is as retrieving each X from I/O controller 34 _PicValue and in GOP on all frames or the image to the accumulator of their summations.

The total maintenance of the quantity of frame or image (being indicated as N) is constant among the GOP.When N is constant, can on the basis of mobile window, calculate X _GOP, add the codec complexity value X of last image _Pic, and deduct among the GOP codec complexity value of image the earliest.In this case, the X that after each frame or image, can obtain upgrading _GOPValue.But N can change.If N changes, then the X of the GOP of corresponding redetermination _GOPMust pass through codec complexity value X from the new quantity of previous image among the redetermination GOP _PicThe summation and calculated, as equation (1).

As mentioned above, different passages are possible with different frames or image rate operation, and for example, standard video frame rates (in the U.S.) is per second 29.97 frames, and it is per second 24 frames for film image, and it is per second 15 frames for cartoon.Also having a kind of may be image or the frame that different passages have varying number among the GOP.Therefore, might have the different GOP time cycles by different passages.In order under this condition, accurately to divide coordination to give passage, by every passage (is marked as GOP from the GOP complexity value of equation (1) divided by GOP time cycle of this passage _Time), in this case the GOP codec complexity value of a plurality of passages in bit rate distributor 30 by time normalization.(square journey (2)).Normalized then GOP $\mathrm{Xnor}{m}_{\mathrm{GOP}}=\frac{X_{\mathrm{GOP}}}{{\mathrm{GOP}}_{\mathrm{time}}}---\left(2\right)$ The codec complexity value (is marked as Xnorm _GOP) be used in different passages, dividing coordination (bit).To discuss the sampling sequential and the generation of value by norm of the complexity value of this system below in more detail.

Return referring to Fig. 5, as mentioned above, for each macro block, bit rate adjuster 49 produces the quantitative calibration factor signal Q of variable quantization device 46 _MB, receive expression from output buffer 48 then and be used for figure place T this macroblock coding _MBSignal.These signals also can directly offer the I/O controller 34 in the bit rate distributor 30 (Fig. 4).The codec complexity value that but μ P31 internal calculation is suitable then (from equation (1) or equation (1) and (2)).

And, in order to simplify transmission, can be to each image X _PicThe codec complexity value carry out no-load voltage ratio and calculate.In a preferred embodiment, this value is become eight-digit number behind multiplier 94.Then the value after this no-load voltage ratio is sent to bit rate distributor 30 (Fig. 4).Owing to other reason,, also might wish the image complexity value X of this computer system with a file such as allowing under the situation that N changes calculation code complexity value again _PicFor example be kept in the mass storage (not shown).Store 8 X of one hour _PicValue will take 108 kilobytes (kB) for normal video, take 86kB for film.

In the following discussion, X ⁱRepresent current obtainable X from the i channel processor _GOP(if all passages have the same GOP time cycle) or Xnorm _GOPIn suitable one.Bit rate distributor 30 (Fig. 1) is according to the codec complexity value X that comes all K channel processor of a plurality of channel processors 10 of self-forming ⁱProduce corresponding quota (Q) signal of the distribution that can put in place in the transmission link of representing next quota cycle.Scheduled transmission link bit rate (being marked as R) from multiplexer 20 (Fig. 1) output distributes in a plurality of channel processors 10, and therefore i channel processor receives and be indicated as R ⁱBit rate distribute.

Be used for distributing the bit rate of transmission link to be for a kind of method of different passages, according to the current obtainable codec complexity X in previous GOP cycle of all channel processors 10 (Fig. 1) ⁱ(on mobile window basis, linear distribution as mentioned above).In the method, each processor i receives the same ratio R of total bit capacity R ⁱAs this encoder X ⁱCodec complexity to provide total coding complexity of all encoders.(square journey (3)).Yet, have been found that to exist the lower limit bit rate to distribute, below this bit rate distributes again $R^i=\frac{X^i}{\underset{j=1}{\overset{k}{\mathrm{\Σ}}}{X}^j}R---\left(3\right)$ The quality of existing image descends suddenly.In addition, in the embodiment shown, the bit rate in next quota cycle distributes the complexity that depends on from previous GOP to measure.Like this, if the scene change of existence from the simple image to the complicated image, because the distribution of new sight is based on previous, simple sight, it may be not enough that branch is used in the position that new, complicated sight is encoded.

Be used for distributing the bit rate of transmission link to guarantee the minimum bit rate of each encoder i is distributed RG for the other method of different passages ⁱ, and distribute remaining bit linearly as equation (3).(square journey (4)).Depend on $R^i=R{G}^i+\frac{X^i}{\underset{j=1}{\overset{K}{\mathrm{\Σ}}}{X}^j}[R-\underset{j=1}{\overset{k}{\mathrm{\Σ}}}R{G}^j]---\left(4\right)$ The expection total complexity of the video by channel transfer and/or the passage price that the vision signal supplier is proposed, every passage can have the minimum bit rate of different assurances.

Also have and a kind ofly be used for distributing the position of transmission link to provide weighted factor P for every encoder i for the method for different passages ⁱ, and according to using weighted factor P ⁱThe codec complexity value X of weighting ⁱDivide coordination pari passu.(square journey (5)).As the assurance smallest allocation method of equation (4), weighted factor P ⁱMay depend on by $R^i=\frac{P^i{X}^i}{\underset{j=1}{\overset{K}{\mathrm{\Σ}}}{P}^i{X}^j}R---\left(5\right)$ The expection total complexity of the vision signal of channel transfer and/or the passage price that the vision signal supplier is proposed.

The method for optimizing that divides coordination to give different passages in transmission link is the combining of smallest allocation method of weight assignment method and the assurance of equation (4) of equation (5).In this method, guarantee smallest allocation, and on the basis of weighting ratio, distribute remaining position every passage.(square journey (6)).As mentioned above, protect $R^i=R{G}^i+\frac{P^i{X}^i}{\underset{j=1}{\overset{k}{\mathrm{\Σ}}}{P}^j{X}^j}[R-\underset{j=1}{\overset{K}{\mathrm{\Σ}}}{\mathrm{RG}}^j]---\left(6\right)$ The smallest allocation of card and weighted factor may depend on the expection total complexity of the vision signal by channel transfer and/or the passage price that the vision signal supplier is proposed.

Might distribute R according to the further selected position of other parameter of system ⁱFor example, found to exist a upper limit bit rate apportioning cost, can't see the improvement of reproduced picture quality more than the value at this.Therefore, to distribute be waste to the transmission link meta in the position that surpasses this upper limit apportioning cost.In addition, the operator of transmission link can implement maximum bit rate distribution R to every passage _Max(it can react above-mentioned upper limit bit rate apportioning cost) and/or minimum bit rate distribute R _Min

In addition, make the stable maximum of bit rate control in order to make bit rate control the possibility minimum of fluctuation, at a maximal increment that can apply increase α and/or reduce β the cycle, the bit rate in cycle distributed by norm to next by norm from passage.As mentioned above, the maximal increment that the numerical value of upper limit bit rate apportioning cost, minimum and maximum bit rate distribute and increase and reduce, can be different for different passages, and can be depending on the expection total complexity of the vision signal by this channel transfer and/or vision signal supplier's passage price.In addition, increase and the minimum and maximum increment that reduces might dynamically change according to the empty or full degree of buffer in the passage.

And bit rate that also can further selected distribution is so that provide buffer management, for example guarantees that the input buffer of the output buffer of CBR encoder 10 (Fig. 1) and corresponding receiver decoder (not shown) can overflow or underflow.If control coded buffer size E does not then need obviously as shown in inequality (7) $E\≤D\frac{R_{\min }}{R_{\max }}---\left(7\right)$ Buffer management, wherein D is the decoding buffer sizes of fixing.If select the coded buffer size according to inequality (7), bit rate distributes can be from R _MinChange to R _MaxAnd the overflow or the underflow of the buffer that can not cause encoding or decode.But this method has too limited the size of coded buffer, has therefore too limited the flexibility of rate controlled.

A kind of buffer management scheme of replacement is current, the instantaneous bit rate that is suitable for and utilize buffer management, rather than preset parameter R _MinAnd R _MaxBecause selecting the decoding buffer sizes can handle with maximum rate R _MaxThe data of transmission, the bit rate distribution always can increase (to the maximum R of system _Max), and the decoding buffer is overflowed.Yet, have the instantaneous minimum bit rate that must keep, to guarantee that the data in coded buffer were transferred to the decoding buffer before its decode time.Therefore, must dynamic calculation guarantee to decode buffer not the minimum bit rate of underflow distribute.

In dynamic calculation should the minimum bit rate be distributed, divide timing when reducing bit rate, must consider that new definite coded buffer is big or small and in some previous time amount, be placed on data volume in the coded buffer.Be appointed as E _nThe new coded buffer size of determining of n frame determine that according to equation (8) wherein Δ is a system $E_n=\mathrm{\Δ}{R}_{\mathrm{new}}=\frac{R_{\mathrm{new}}}{R_{\max }}D---\left(8\right)$ Be that frame of video is when arriving encoder and the constant time delay of this frame between when being presented on the decoder time of delay; D is the decoding buffer sizes of fixing; And R _NewBe that the new bit rate that proposes distributes.This buffer sizes is guaranteed will not have overflow or underflow in the Code And Decode buffer under the stable state that new bit rate distributes.

But, as mentioned above,, then there is the change-over period that equals system delay time Δ if the bit rate of proposition distribution newly reduces, wherein may have too many position and in coded buffer, consequently can not successfully arrive decoder than lower rate transmissions with new.Be used for a kind of suggesting method that the bit rate of selected new proposition distributes and be at first the volume check of the system delay time Δ previous frame that is indicated as Г is indicated as the actual figure place of putting into coded buffer (buffer is saturated) of e.The saturated number of largest buffer with previous Г frame (is indicated as e then _{Max, Г}) with the new coded buffer size E that determines that obtains by equation (8) _nCompare.Guarantee that then the bit rate that reduces of minimum that successfully is transferred to the passage i of receiver decoder from all of previous Г frame distributes R _ReduceProvide by equation (9).

If this restriction puts on multiplexer system, then after having calculated bit rate according to equation (3), (4), (5) or (6) and distributing, check that these bit rate branches are equipped with and determine whether they drop in the current upper and lower bound of this passage.At first, the upper and lower bound of every passage i is determined.Any quota cycle k (is expressed as R ⁱ _{The upper limit}[k]) upper limit bit rate distribute to be minimum in following: the maximum on the previous quota cycle k-1 allowed to increase distribution; Distribute the limit with maximum bit rate.(square journey (10)).The lower limit of any quota cycle k

Rate is distributed R ⁱ _{Lower limit}[k] is following middle maximum: minimum bit rate distributes the limit; Minimum on the previous quota cycle k-1 allows distribution that reduces and the bit rate that is reduced by the minimum that equation (9) obtains to distribute.(square journey (11)).Carry out the adjustment that the passage bit rate distributes then.

If any passage distribute bit rate to surpass arbitrary limit value, then the bit rate of this passage distributes and is set to this limit value, and redistributes available residue bit rate in other passage.For example, if as calculating with equation (3), (4), (5) or (6), distribute to the upper limit of the bit rate of a passage i greater than this passage, calculate as equation (10), then the bit rate of passage i is set at this upper limit R ⁱ _{The upper limit}[k].If instead the lower limit that bit rate is calculated less than equation (11) then is set at bit rate this lower limit R ⁱ _{Lower limit}[k].(square journey (12)).

If any bit rate of the qualification operation change of equation (10), (11) and (12) distributes, then in the passage that does not limit, redistribute the remaining bit rate that utilizes according to equation (3), (4), (5) or (6).The limit in relative then equation (10), (11) and (12) is checked these passages once more.Repeating this circulation distributes up to finishing all bit rates.In the above-described embodiments, the codec complexity cycle is to move on the window basis GOP cycle that image is one by one determined one, and it is that the variation from a quota cycle to next quota cycle generally speaking should less enough time intervals during bit rate in the passage distributed.Therefore, equation (10), (11) and (12) should seldom be quoted.

If passage just operate with the different GOP time cycles, the sequential of codec complexity sampling and be complicated based on the updated space rate generation by norm of codec complexity.There are two kinds of methods that produce the bit rate quota allocation under the sampling of precision encoding complexity and this situation.In first method, calculate the constant quota cycle by this way, promptly each passage has the quota cycle of equal amount in every GOP.In the method, sampling number and quota cycle can change from channel-to-channel among every GOP, and still, for any passage, this sampling and the quantity in quota cycle are constant in the GOP.In the second approach, get a sample, whenever any passage begins to produce new the distribution once new GOP, and consideration is from the length computation of the time cycle of the previous current sampling of the sampling figure place with new quota allocation.

Fig. 7 is that expression utilizes the sequential chart that first method is sampled and quota upgrades in system.In order to simplify this figure, only show two passages.In Fig. 7, passage 1 is the example of a passage of the normal video of the frame rate (in the U.S.) of transmission with per second 30 frames.Passage 2 is examples of a passage of the film of the frame rate of transmission with per second 24 frames.Suppose that each GOP of each passage has 12 frames.Passage 1 per 0.4 second beginning one new GOP like this, or 2.5 GOP of per second, and passage 2 began a new GOP or 2 GOP of per second in per 0.5 second.Selected sampling rate is per 0.1 second sample.Therefore, in passage 1, in each GOP, exist four samples and quota to upgrade, in passage 2, in each GOP, exist five samples and quota to upgrade.Represent sample time ts with vertical dotted line.Because the time cycle Δ t between the sample is constant (0.1 second), above-mentioned equation (3) can without any modification be used to calculate the bit rate of next sampling period to equation (12) and distribute.These bit rates distribute and can add up and be used in the channel processor 10 (Fig. 1) according to the known arrangement that is referred to as " mark and funnel (token and leaky bucket) ".

Fig. 8 is the sequential chart that expression utilizes codec complexity value sampling in the system of above-mentioned second method and quota to upgrade.Each passage shown in Fig. 8 is propagated identical signal with Fig. 7.In Fig. 8, when no matter when arbitrary passage begins a new GOP, obtain sample from the present encoding complexity value of all passages.Produce new the distribution according to these sample values with from the time cycle Δ t that last sample begins.These sampling times are expressed as vertical dotted line t1-t8 in Fig. 8, t2 wherein, and t3, t4, t6 and t8 are corresponding to the beginning of GOP in the passage 1, and t1, t3, t5 and t7 are corresponding to the beginning of GOP in the passage 2.Though t3 represents the sampling time corresponding to the beginning of GOP in passage 1 and the passage 2, do not require this appearance constantly.

At each sampling time, to the present encoding complexity value in all passages (from former GOP, can be on mobile window basis one by one image ground obtain) sample.Equation (3) to equation (12) can be used for calculating next bit rate quota ratio, but when the actual number of bits of determining to can be used for distributing, the time quantum Δ t that begins from last sample must take in.In order suitably to compensate different sample cycles, obtainable bit rate R total in equation (3) to (12) substitutes with the figure place (being appointed as C) that can be used for distributing, and it is the product that always can obtain bit rate R and the Δ t of sample cycle, i.e. C=R Δ t.Then equation (3) is distributed to each channel processor 10 (Fig. 1) to the figure place that equation (12) calculates, it utilizes " mark and funnel " scheme to add up as mentioned above and uses the position of being distributed.When the vision signal from different passages 5 has different GOP during the time cycle, each in above-mentioned two kinds of methods will accurately distribute bit rate to give each channel processor 10.

If all passages are with identical frame rate work, and have identical frame number in a GOP, promptly all passages have identical GOP time cycle GOP _TimeThen can simplify the sampling sequential of codec complexity value and the generation of different passage updated space rate quotas.Fig. 6 is a codec complexity sample and the sequential chart that upgrades sequential by norm in this system of expression.In Fig. 6, each horizontal line is corresponding to respective channel 1-K.Begin the moment of the coding of I frame from the upwardly extending short vertical line representative of horizontal line from this passage, it is considered to the beginning of the GOP of this passage.The time cycle GOP of GOP _TimeIn all passages, equate, but as can be seen, the time started of the GOP of each passage is different.In fact, have found that the GOP of each passage preferably has different zero-times, the coding of I frame can be not overlapping like this.This complexity that has increased through different passages changes.

Found that these frames are inessential from different GOP as long as consider I frame, P frame and the B frame of similar number when calculation code complexity value.Therefore, as with shown in the solid line that extends through all channel time axles, can side by side obtain the sample of codec complexity value any time in GOP from all passages.Can produce renewal and transmission backward channel processor 10 (Fig. 1) of the bit rate quota of all passages then from this sample.

According to the above-mentioned multiplex system of having put system description in the lump.But.A plurality of channel processors 10 can be placed on the position far away of off normal rate distributor 30 and multiplexer 20.In a kind of like this system, between encoder and bit rate distributor, set up communication link.In this case, some bit position that transmits between processor 10 and multiplexer can be exclusively used in the complexity transmission of Information of processor.

Claims (8)

1, a kind of parameter sampling apparatus comprises:

A plurality of data signal sources (5), each data-signal comprises the alphabetic data group, every group of data in all described data-signals have identical fixedly predetermined time period, and comprise the alphabetic data piece;

A plurality of parameters are determined circuit (16), and each responds a corresponding described data-signal, produce the sequential signal (complexity) with numerical value of the signal parameter of each described alphabetic data piece in the corresponding described data-signal of representative;

A plurality of accumulators (31), each responds a corresponding described parameter representation signal (complexity), is used for preserving the signal of the parameter value that adds up of representing corresponding described each group of data-signal;

A data sampler (31) is coupled to described a plurality of accumulator, is used for the described parameter representation signal that adds up from all described accumulators is side by side sampled basically.

2, device as claimed in claim 1, wherein: described a plurality of accumulators (31) and described sampling of data device (31) are comprised in one to have and is coupled to the computer system (31 that relevant parameter is determined a plurality of inputs (complexity) of circuit, 32,33,34) in.

3, device as claimed in claim 1, wherein: each in described a plurality of accumulators (31) comprises:

Be used for the value of each sequence parameter representation signal (complexity) is produced mutually the circuit (31) of the described parameter value that adds up;

Be used for when sampling, the described parameter value that adds up being offered the circuit (34) of described accumulator by described sampling of data device; And

Be used for immediately the described parameter value that adds up being reset to zero circuit (31) after providing circuit by sampling described.

4, device as claimed in claim 1, wherein:

Every group of data comprise the described alphabetic data piece of a predetermined quantity; And

In described a plurality of accumulator (31) each comprises:

Be used for to store the memory (32) that each organizes the signal parameter value (complexity) of the alphabetic data piece of predetermined quantity described in data to time sequencing farthest from nearest;

Be used to preserve the circuit (31) of the described parameter value that adds up;

Be used for value and the described parameter value addition that adds up, and the described parameter value that adds up deducted the circuit (31) of described signal parameter value (complexity) farthest signal parameter representation signal (complexity); And

Be used for giving up described signal parameter value farthest (complexity) from described memory (32), and in described memory the value of the described signal parameter representation signal of storage as the circuit (31) of described nearest signal parameter value.

5, device as claimed in claim 1, wherein

Each described data signal source (5) produces vision signal, and described data set is made up of the order video frame of pre-determined constant quantity, and described data block is made up of described frame of video; And

Each described parameter determines that circuit (16) comprises a circuit (16) of codec complexity that is used for determining described in the described vision signal each frame of one.

6, a kind of parameter sampling apparatus comprises:

A plurality of data signal sources (5), each data-signal comprises the alphabetic data group, every group in all described data-signals has same fixing predetermined time period, and comprises the alphabetic data piece;

Respond the application circuit (14,20) of a described a plurality of data-signal and a control signal (control);

A plurality of parameters are determined circuit (16), and each responds in the described data-signal corresponding one, are used for producing the sequential signal (complexity) of the numerical value of the signal parameter with corresponding each the described order piece of described data-signal of representative;

A plurality of accumulators (31), each responds a corresponding described parameter representation signal (complexity), is used to preserve the signal of representing the parameter value that adds up;

Be coupled to the sampling of data device (31) of described a plurality of accumulator (31), be used in fact side by side to the described parameter representation signal sampling that adds up from all described accumulators (31); And

Respond the control-signals generator (31) of the described parameter representation signal that adds up of having sampled, be used for producing described control signal according to the described value that adds up the parameter representation signal.

7, device as claimed in claim 6, wherein:

Described application circuit comprises:

Data multiplexer (20) with a plurality of data input pins; And

A plurality of controlled constant bit rate encoders (14), be coupling between the corresponding input (I-K) of corresponding data signal source and described data multiplexer (20), corresponding quota control signal (control) of each response is used for producing the encoded signals of representative from the data-signal of corresponding data signal source (5) with the bit rate by described quota control signal control; And

Described control-signals generator (31) produces a plurality of quota control signals (control) according to described a plurality of parameter representation signals (complexity).

8, device as claimed in claim 6, wherein said a plurality of accumulator, described sampling of data device (31) and described control-signals generator (31) are comprised in one to be had and is coupled to the computer system (31-34) that relevant parameter is determined a plurality of inputs (complexity) of circuit (16) and is coupled to a plurality of outputs (by norm) of described application circuit (14,20).

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