CN114928433A - Low data overhead frame synchronizer - Google Patents
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Abstract
The low-data-overhead frame synchronizer disclosed by the invention has the advantages of low data overhead and low implementation complexity. The invention is realized by the following technical scheme: the frame head detection module carries out frame synchronization code group identification on a search frame head according to the matching correlation of the search fault-tolerant threshold, identifies the starting moment of a digital information sequence, generates a data frame starting pulse aligned with first bit data in a data frame, and triggers a signal to start a search state and finish caching the data frame in the period from the search state to a check state; the state transition control module generates a trigger pulse by utilizing the rising edge of the locking state indicating signal, informs the data output control module, reads out the frame data from the data cached in the data caching module, and fills in information such as time codes and the like according to the specific protocol requirement; before frame synchronization, the data packing module adopts a ping-pong read-write operation mechanism to extract the cache data in the data cache module, and packs all data frames in a search stage and a check stage before establishing the frame synchronization state and sends the data frames to upper computer software.
Description
Technical Field
The invention mainly relates to the communication application field related to telemetering, data transmission and the like, in particular to a frame synchronizer realizing method for processing digital equipment with frame structure information to keep synchronization when channel error codes are serious and reducing data overhead before synchronization.
Background
Synchronization is a very important issue in communication systems. The digital communication system comprises carrier synchronization, bit synchronization and frame synchronization. The frame synchronization is mainly used to identify the frame structure start position of the receiving end data stream, so as to know where the data stream with a specific structure starts, and then perform subsequent information processing based on the structure, such as descrambling, packet decoding, and the like. Synchronization, which allows a communication system to have a uniform time stamp, is an important guarantee that data transmission is reliable between systems. Since the modern digital communication equipment generally adopts the parallel technology, a parallel frame synchronization system needs to be designed. In order to improve transmission efficiency, it is often necessary to combine several low-speed digital signals into one high-speed digital signal for transmission through a high-speed channel. The equipment implementing this function is called a digital multiplex system. Frame synchronization is an important component in digital multiplex systems. Theoretical and engineering practices have demonstrated that: the technical performance of the frame synchronization system largely determines the technical performance of the entire digital multiplexing apparatus. The digital multiplex system includes two parts, i.e., a transmitting end and a receiving end, which are generally called a multiplexer and a demultiplexer. In order to obtain and maintain the phase relationship between the frame state of the demultiplexer and the frame state of the multiplexer so as to implement the demultiplexing correctly, the digital multiplexing system often inserts a frame synchronization code for synchronization while combining the low-speed digital signal into the high-speed signal at the transmitting end; at the receiving end, the demultiplexer detects the frame synchronization code in the digital signal at the transmitting end. Since the data stream is a digital information group consisting of several symbols. When both communication parties transmit data streams, the task of frame synchronization is to identify the start and stop time of digital information groups based on bit synchronization information and generate a frame synchronization signal, which is a timing pulse sequence consistent with the start and stop time. It can be seen that frame Synchronization is usually implemented by inserting an Attached Synchronization Marker (ASM) between data code groups at a transmitting end, and identifying the frame Synchronization headers at a receiving end. For example, in the telemetry channel synchronization and channel coding standard of the spatial data Consultation Committee (CCSDS) (CCSDS131.0-B-3), a frame synchronization header having a length from 32 bits to 192 bits is recommended for block codes having different frame lengths and coding gains in order to realize a frame synchronization function with excellent performance. Two important performance indicators for measuring the frame synchronization system are the average synchronization acquisition Time (TASC) and the average synchronization retention time. Due to the existence of false alarm and false leakage, the difference of different parallel frame synchronization systems in the average synchronization capturing time is caused. Since only one state machine is used for protection after synchronization, there is no difference in average synchronization retention time. The average synchronization acquisition time of the frame synchronization system should be as small as possible. However, the performance and the area overhead are in a pair of contradiction, and the area overhead is often larger for a system with good performance.
The bit error rate of modern digital communication systems is generally low. For example, 10G Ethernet protocol specifies an average bit error rate of 10 at the physical layer -12 . However, signal fading, i.e. an increased error rate, sometimes occurs in a communication system, and the signal fading usually causes the performance of the frame synchronization system to deteriorate. Some frame synchronization systems have good performance at low bit error rates and degrade dramatically at high bit error rates, which should be avoided as much as possible.
Therefore, based on the Maximum Likelihood (ML) principle, a frame synchronization strategy with strong robustness necessarily needs to detect based on continuous multi-frame data. The classic frame synchronization strategy adopts a mode based on state transition among a search state, a check state, a locking state and a loss state. The classical frame synchronization implementation method has the advantages and has limitations in certain specific scenes: for example, under the threshold noise ratio condition, it is usually necessary to set a larger number of check frames to ensure that reliable frame synchronization is established, but this also increases the overhead of frame synchronization — the data frame before locking is used as the overhead required for establishing locking and is not reported to the upper layer as effective information. This is not a problem in communication systems where the data transmission rate is high and the requirement for effective data volume is not severe, but when the data transmission rate is low (e.g. 32bps code rate in deep space sounding), the transmission time of one frame may reach 2 minutes or even longer, and such overhead becomes non-negligible. Furthermore, if the application scenario requires the data amount of the valid data, the overhead may become difficult to tolerate, for example, at key stages such as probe landing or orbit change in the measurement and control communication process, the data amount that can be acquired on the ground is very small due to factors such as low data transmission rate and limited communication time, and the system needs as much valid data as possible to perform state judgment to assist in decision making.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide the low-data overhead frame synchronizer which has the advantages of low data overhead, good universality, low complexity and settable synchronization establishment and maintenance time. A frame synchronization method compatible with existing conventional frame synchronizers.
In order to achieve the above object, the present invention provides a low data overhead frame synchronizer, comprising: the system comprises a frame head detection module, a state transfer control module, a data output control module, a data cache module and a frame data packaging module which are sequentially connected in series according to the data flow direction, and is characterized in that the frame head detection module carries out frame synchronization code group identification on a search frame head according to the matching correlation of a search fault-tolerant threshold, identifies the starting moment of a digital information sequence, generates a data frame starting pulse aligned with first bit data in a data frame, takes the starting pulse as a trigger signal for caching the data before establishing a frame synchronization state, and is used for enabling the data cache module to start caching the data frame during the period from the completion of the search state to the check state; after the state transition control module is converted from the checking state to the locking state, a trigger pulse is generated by utilizing the rising edge of the locking state indicating signal to inform a data output control module, frame data are stored in a data cache module for data reading, if the locking is not established and the searching state is recovered, a cache address is reset, when the state is indicated to be the searching state, if a data starting pulse is obtained, 1 st frame data are recorded from an address 0 of a cache region, and then each frame data is stored from a starting address 2048 (N-1) respectively until all data frames in the checking state are stored, so that invalid data before a frame header is searched and stored next time are ensured to be covered; after receiving the frame synchronization locking pulse, the data output control module starts a reading process, reads out each frame of data stored in the cache of the data cache module from an initial address 2048 × 8 (N-1) according to the specified data bit clock beat, sends the data to the frame packing module for packing, and after receiving the frame header pulse indication, the frame packing module stores the data in the cache region of the data cache module by using the data bit clock and fills information such as time codes according to the specific protocol requirement; the data packaging module before frame synchronization adopts a ping-pong read-write operation mechanism to extract the cache data in the data cache module, and packages all data frames in a search stage and a check stage before establishing a frame synchronization state and sends the data frames to upper computer software, wherein N is 1,2 and 3 ….
Compared with the prior art, the invention has the following beneficial effects:
the invention aims to reduce data overhead while ensuring frame synchronization performance, and sequentially connects the frame header detection module, the state transfer control module, the data output control module and the frame packing module in series according to the data flow direction, the design logic is clear and concise, the synchronization establishing time, the synchronization maintaining time and the out-of-step probability can be flexibly set, the invention can be completely compatible with the functional logic of the traditional frame synchronizer, excessive realization resources can not be increased, and the hardware realization complexity is low. The method has the advantages of flexible configuration and strong anti-interference capability. The data frame storage function before frame synchronization is established can be started or closed through the control of an upper computer.
The invention adopts a frame head detection module to search a frame head according to a fault-tolerant threshold, identifies the starting moment of a digital information sequence and generates a frame starting pulse aligned with a first information bit in a data frame; the module calculates the Hamming distance between the current received data sequence and the preset frame synchronous word, compares the Hamming distance with a fault tolerance threshold and judges whether a frame header is searched; the frame synchronization code group pattern, the frame synchronization code group length and the fault tolerance threshold can be flexibly configured, can adapt to various variable frame structures and synchronization codes, and can adapt to single frame and multiframe structures.
The present invention employs a state transition control module to perform state machine control among a search state, a check state, a lock state, and an out-of-sync state, as shown in fig. 2. When a frame header meeting the fault tolerance threshold is searched, the frame data is switched into a checking state, the frame data is sent to a packaging module and a data caching module by a data output control module at the same time, wherein the packaging module only processes the output data after the locking state, and the data caching module caches the data frame before the frame synchronization state is established (the searching state is completed to the checking state). After the data frame is shifted to the checking state, if the setup data frames are detected continuously, the data frame is shifted to the locking state, and if the invalid data frames are detected, the data frame is shifted to the searching state. The data frame in the checking state period is also sent to the packing module and the data caching module by the data output control module at the same time, the packing module does not process the data frame, and the data caching module caches the data frame.
After the state is checked by the state transfer control module and converted into the locking state, the rising edge of the locking indication signal is used for generating a trigger pulse to inform the data cache module, the data in the cache is read out and sent to the data packaging module before frame synchronization. All effective data of a search stage and a check stage before the frame synchronization state is established can be kept on the premise of not changing a frame synchronization strategy, so that more effective data are provided, for example, in key stages such as detector landing or orbit change in the measurement and control communication process, the data volume which can be received by the ground is very small due to factors such as low data transmission rate and limited communication time, and therefore the effective data before the frame synchronization is established can be provided, and more effective information is provided for decision making.
The invention comprehensively considers the false leakage probability related to channel error code and the false alarm probability related to an Additional Synchronization Mark (ASM) code type, adopts a data output control module to start a reading flow after receiving a frame synchronization locking pulse, reads out data in a cache according to a specified data bit clock beat, sends N frame data in a check state to a frame packing module for packing, utilizes a data bit clock to store the data in a cache region of a data cache module after the frame packing module receives a frame header pulse indication, and fills time code information according to specific protocol requirements. And after synchronization is established, synchronization can be kept for a long time, so that telemetering data can be continuously and reliably recorded. These data frames are discarded as data overhead during the frame sync establishment during the operation of the conventional frame synchronizer. In some application scenarios, the data frames can provide timely and effective information for the measurement and control communication system, and have high value. Simulation and actual measurement results show that the comprehensive frame synchronization scheme can keep effective frame data before the establishment of the synchronization state, and the frame synchronization performance is consistent with that of the basic frame synchronization scheme.
The invention adopts a ping-pong read-write operation mechanism for the data packaging module before frame synchronization, and reports the data frame to the upper computer software according to the specified data format before the frame synchronization state is established from the data caching module. The module and the conventional frame synchronization packaging module work independently in parallel, so that the conventional frame synchronization establishing logic cannot be influenced.
Drawings
FIG. 1 is a schematic diagram of the operation of the low data overhead frame synchronizer of the present invention;
FIG. 2 is a schematic diagram illustrating a detection frame synchronization state transition of the frame header detection module of FIG. 1;
FIG. 3 is a timing diagram illustrating the operation of the first frame reporting function;
FIG. 4 is a schematic diagram of address allocation of the data cache module of FIG. 1.
Detailed Description
See fig. 1. In an exemplary preferred embodiment described below, a low data overhead frame synchronizer comprises: and the frame header detection module, the state transfer control module, the data output control module, the data cache module and the frame data packaging module are sequentially connected in series according to the data flow direction. The frame head detection module carries out frame synchronization code group identification on a search frame head according to the matching correlation of the search fault tolerance threshold, identifies the starting moment of a digital information sequence, generates a data frame starting pulse aligned with first bit data in a data frame, and takes the starting pulse as a trigger signal for caching the data before establishing a frame synchronization state, so that the data caching module starts caching the data frame from the completion of the search state to the verification state; after the state transition control module is converted from the checking state to the locking state, a trigger pulse is generated by utilizing the rising edge of the locking state indicating signal to inform a data output control module, frame data are stored in a data cache module for data reading, if the locking is not established and the searching state is recovered, a cache address is reset, when the state is indicated to be the searching state, if a data starting pulse is obtained, 1 st frame data are recorded from an address 0 of a cache region, and then each frame data is stored from a starting address 2048 (N-1) respectively until all data frames in the checking state are stored, so that invalid data before a frame header is searched and stored next time are ensured to be covered; after receiving the frame synchronization locking pulse, the data output control module starts a reading process, reads out each frame of data stored in the cache of the data cache module from an initial address 2048 × 8 (N-1) according to the specified data bit clock beat, sends the data to the frame packing module for packing, and after receiving the frame header pulse indication, the frame packing module stores the data in the cache region of the data cache module by using the data bit clock and fills information such as time codes according to the specific protocol requirement; the data packaging module before frame synchronization adopts a ping-pong read-write operation mechanism to extract the cache data in the data cache module, and packages all data frames in a search stage and a check stage before establishing a frame synchronization state and sends the data frames to upper computer software, wherein N is 1,2 and 3 ….
Aiming at the problem that the processing of frame data before synchronization cannot affect the conventional frame synchronization logic, the output data stream of the data output control module is sent to a frame synchronization packaging process and two parallel independent processing processes of data caching and packaging before frame synchronization.
See fig. 2. The frame header detection module searches a frame header in a received data sequence by taking the length of a frame synchronization code group as the length of a sliding window in a search state, determines to find the frame synchronization code group when the Hamming distance between the data sequence in the sliding window and the frame synchronization code group meets a preset fault-tolerant threshold, and if one frame header is searched, switches to a check state, and independently sets the fault-tolerant threshold and the frame length as interval detection frame synchronization code groups in the check state; and the frame header detection module is switched into a locking state after continuously detecting the setup frame headers in the checking state, and returns to the searching state again if an invalid frame header which does not meet the fault tolerance threshold is monitored midway. And after the frame header detection module enters the locking state, continuously detecting the frame synchronization code group by taking the set frame length as an interval, if the valid frame synchronization code group is detected, continuously keeping the locking state, otherwise, entering the out-of-step state, if the invalid frame header is continuously detected for hold-1 time under the out-of-step state, entering the searching state, and otherwise, returning to the locking state. In an alternative embodiment, the frame sync word decision error-tolerant bit number in each state can be set, and the detection frame number setup and the hold value can be set.
See fig. 3. The data output control module operates the time sequence in the time sequence chart according to the reporting function of the first frame, and from the time sequence searched to the first frame synchronous word, aligns the frame head pulse under the time sequence with the rising edge of the first information bit in the data frame, and transmits the data to the post-processing module according to two branches, wherein the first branch is a branch transmitted to the frame packing module or formed by post-modules including decoding, descrambling and the like, the second branch is a branch specially used for processing the data before the locking state, and when the module of the first branch is used for processing, the module only processes the data frame in the locking state by combining the current state of the state transfer control module; and the second branch can buffer the data frames in the searching state and the checking state, and the frame packing module packs and outputs the data frames after the frame synchronization state is established.
The data buffer module in the second branch mainly includes buffer space and control logic for writing/reading data into/from the buffer space. When the state is indicated as a search state, if a data start pulse is obtained, recording the 1 st frame data from the address 0 of the buffer area, then storing each frame data from the start address 2048 × 8 (N-1) respectively until all data frames in the check state are stored, starting a reading process after the data output control module receives the frame synchronization locking pulse, reading each frame data in the buffer from the start address 2048 × 8 (N-1) respectively according to the specified data bit clock beat, and sending the frame data to a frame packing module for packing, wherein N is 1,2,3 …. If the locking is not established and the searching state is recovered, the write address is reset to ensure that the previous invalid data is covered when the frame header is searched for storage next time.
After receiving the frame header pulse indication, the frame packing module stores the data into its internal buffer area by using the data bit clock, and fills in information such as time code according to the specific protocol requirement; the data packaging module before frame synchronization adopts a ping-pong read-write operation mechanism to package all data frames in a search stage and a check stage before establishing a frame synchronization state and send the data frames to upper computer software for external sending or disk storage. The upper computer is provided with a switch, and can flexibly start or close the data sending or storing function before frame synchronization.
See fig. 4. The data buffer module divides a storage area by the length of data of each row 1 frame, performs address allocation according to the longest frame length of 2048 bytes, namely 16384 bits as a unit, and the length can be adjusted according to actual requirements. The addressing in the writing and reading operations of the buffer data is convenient by taking a frame as a unit.
The frame head detection module sets 0 and 1 with equal probability characteristic in the data stream, if the frame head position is not the present frame head position, the false alarm probability P of the frame head is judged A ：
Calculating the frame synchronization false locking probability P caused by false alarm of continuous a frames WS ：
Then, the decision fault-tolerant bit number in each state and the state transition frame number between each state in the frame synchronization strategy are adjusted to adapt to the synchronization requirements under various channel conditions.
The state transfer control module controls the data flow such as serial/parallel, parallel/serial conversion, matching identification of synchronous code groups, frame complementing, negation and the like according to the data flow identified by the frame header detection module, provides single frame, multiframe synchronous signals and word synchronous signals of data, and provides required frame matching state signals.
The data output control module divides the working state of frame synchronization into a capture state and a tracking state, controls the data stream and outputs corresponding synchronization signals, detects single frames/sub-frames in parallel in the capture and tracking states, adaptively switches the threshold of frame headers and judges the capture desynchronizing threshold, adjusts the threshold according to the capture and tracking states of the system, performs matching correlation and threshold judgment, performs frame supplementing correction processing on the data frames after frame synchronization, and realizes capture, tracking, frame supplementing and negation of the frames. To adapt to different synchronous code groups and fault tolerance requirements. Improving system performance. The single frame/sub-frame parallel detection can reduce recapture caused by single frame or sub-frame loss, and improve the out-of-step recapture speed. For the positive synchronous code group loss in the fault-tolerant range, the false out-of-step discrimination capability of the system can be improved through the frame supplementing correction processing.
The data output control module outputs a control signal after receiving the frame synchronization locking pulse, starts a reading flow, reads data in a cache according to a specified data bit clock beat, sends out a frame header pulse before locking, uses the frame header pulse in combination with a frame synchronization locking state, sends a first frame to the frame packing module for packing, and stores the data in a cache region of the data cache module by using the data bit clock after the frame packing module receives an indication of the frame header pulse, and fills time code information according to a specific protocol requirement; the method adopts a ping-pong read-write operation mechanism to convert the configured length information into the initial time information of the synchronous signal, the table is looked up to output single-frame, multi-frame and word synchronous signals, the data under the locking state condition is reported through a data reporting interface channel between the table and an upper computer, a switch is provided, the data sending or storing function before frame synchronization can be started or closed, and the data reporting and storing functions of the two branches are independently decoupled.
The above detailed description of the embodiments of the present invention, and the detailed description of the embodiments of the present invention used herein, is merely intended to facilitate the understanding of the methods and apparatuses of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A low data overhead frame synchronizer comprising: the system comprises a frame head detection module, a state transfer control module, a data output control module, a data cache module and a frame data packaging module which are sequentially connected in series according to the data flow direction, and is characterized in that the frame head detection module carries out frame synchronization code group identification on a search frame head according to the matching correlation of a search fault-tolerant threshold, identifies the starting moment of a digital information sequence, generates a data frame starting pulse aligned with first bit data in a data frame, takes the starting pulse as a trigger signal for caching the data before establishing a frame synchronization state, and is used for enabling the data cache module to start caching the data frame during the period from the completion of the search state to the check state; after the state transition control module is converted from the checking state to the locking state, a trigger pulse is generated by utilizing the rising edge of the locking state indicating signal to inform a data output control module, frame data are stored in a data cache module for data reading, if the locking is not established and the searching state is recovered, a cache address is reset, when the state is indicated to be the searching state, if a data starting pulse is obtained, 1 st frame data are recorded from an address 0 of a cache region, and then each frame data is stored from a starting address 2048 (N-1) respectively until all data frames in the checking state are stored, so that invalid data before a frame header is searched and stored next time are ensured to be covered; after receiving the frame synchronization locking pulse, the data output control module starts a reading process, reads out each frame of data stored in the cache of the data cache module from an initial address 2048 × 8 (N-1) according to the specified data bit clock beat, sends the data to the frame packing module for packing, and after receiving the frame header pulse indication, the frame packing module stores the data in the cache region of the data cache module by using the data bit clock and fills information such as time codes according to the specific protocol requirement; the data packaging module before frame synchronization adopts a ping-pong read-write operation mechanism to extract the cache data in the data cache module, and packages all data frames in a search stage and a check stage before establishing a frame synchronization state and sends the data frames to upper computer software, wherein N is 1,2 and 3 ….
2. The low data overhead frame synchronizer of claim 1 wherein: and the frame header detection module searches frame headers in the received data sequence by taking the length of the frame synchronization code group as the length of a sliding window in a search state, judges that the frame synchronization code group is found when the Hamming distance between the data sequence and the frame synchronization code group in the sliding window meets a preset fault-tolerant threshold, and switches to a check state if one frame header is searched, and independently sets the length of the fault-tolerant gate frame as an interval detection frame synchronization code group in the check state.
3. The low data overhead frame synchronizer of claim 2 wherein: the frame header detection module is switched into a locking state after continuously detecting setup frame headers in a checking state, and returns to a searching state again if an invalid frame header which does not meet the fault tolerance threshold is monitored midway; after the frame header detection module enters a locking state, the frame header detection module continues to detect a frame synchronization code group by taking the set frame length as an interval, if a valid frame synchronization code group is detected, the locking state is continuously maintained, otherwise, the frame header detection module enters a loss gait, if an invalid frame header is continuously detected for hold-1 time in the loss gait state, the frame header detection module enters a searching state, otherwise, the frame header detection module returns to the locking state, wherein a setup value is the number of data frames needing to be detected in the checking state and can be configured as a frame synchronizer parameter, and a hold value is the number of the invalid frame headers needing to be continuously detected when the frame header detection module returns to the searching state from the synchronization state and can be configured as a frame synchronizer parameter.
4. The low data overhead frame synchronizer of claim 1 wherein: and the data output control module operates the time sequence in the time sequence chart according to the reporting function of the first frame, aligns the frame head pulse of the time sequence lower frame with the rising edge of the first information bit in the data frame from the first frame synchronous word searching, and transmits the data to the post-processing module according to the two branches.
5. The low data overhead frame synchronizer of claim 5 wherein: the first branch is transmitted to a frame packing module or a branch consisting of a post-stage module including decoding and descrambling, the second branch is a branch specially used for processing data before the locking state, and the module of the first branch only processes the data frame in the locking state by combining the current state of a state transition control module when processing; and the second branch can buffer the data frames in the searching state and the checking state, and the frame packing module packs and outputs the data frames after the frame synchronization state is established.
6. The low data overhead frame synchronizer of claim 5 wherein: the data caching module in the second branch circuit comprises a caching space and control logic for writing/reading data into/from the caching space; when the state is indicated as a search state, if a data start pulse is obtained, 1 st frame data is recorded from an address 0 of a buffer area, and then each frame data is stored from a start address 2048 × 8 (N-1) until all data frames in the check state are stored.
7. The low data overhead frame synchronizer of claim 6 wherein: after receiving the frame synchronization locking pulse, the data output control module starts a reading process, reads out each frame data in the cache from the start address 2048 × 8 (N-1) according to the clock beat of the specified data bit, and sends the frame data to the frame packing module for packing, and if the locking is not established and the searching state is restored, the write address is reset to ensure that the previous invalid data is covered when the next frame header is searched for storage, wherein N is 1,2, and 3 ….
8. The low data overhead frame synchronizer of claim 1 wherein: after the frame packing module receives the frame header pulse indication, the data bit clock is utilized to store the data into an internal cache region, and time code information is filled according to the specific protocol requirement; the data packaging module before frame synchronization adopts a ping-pong read-write operation mechanism to package all data frames in a search stage and a check stage before establishing a frame synchronization state and send the data frames to upper computer software for external sending or disk storage.
9. The low data overhead frame synchronizer of claim 1 wherein: the data buffer module divides a storage area by the length of data of 1 frame of each row, performs address allocation according to the longest frame length of 2048 bytes, namely 16384 bits as a unit, and performs addressing when writing and reading the buffer data by taking the frame as a unit.
10. The low data overhead as set forth in claim 1A frame synchronizer, characterized by: the frame head detection module sets 0 and 1 with equal probability characteristic in the data stream, if the frame head position is not the present frame head position, the false alarm probability P of the frame head is judged A ：
Calculating the frame synchronization false locking probability P caused by false alarm of continuous a frames WS ：
And average probability of lock entry P SL ：
Then, the decision fault-tolerant bit number in each state and the state transition frame number among each state in the frame synchronization strategy are adjusted to adapt to the synchronization requirements under various channel conditions.
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