CN114902562A - Circuit and method for generating temperature-stable clock using common oscillator - Google Patents
Circuit and method for generating temperature-stable clock using common oscillator Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L1/00—Stabilisation of generator output against variations of physical values, e.g. power supply
- H03L1/02—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only
- H03L1/022—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature
- H03L1/027—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature by using frequency conversion means which is variable with temperature, e.g. mixer, frequency divider, pulse add/substract logic circuit
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
- H03L7/0994—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising an accumulator
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/50—All digital phase-locked loop
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Abstract
The present disclosure provides a circuit for generating a temperature-stabilized clock, the circuit comprising a first crystal oscillator, a second crystal oscillator, an input for a reference clock source, a clock output, a first phase acquisition circuit coupled to the first crystal oscillator and the second crystal oscillator, a second phase acquisition circuit coupled to the input for the reference clock source and the second crystal oscillator, a first DPLL coupled to the first phase acquisition circuit, a crystal oscillator variation estimator coupled to the first DPLL, a second DPLL coupled to the second phase acquisition circuit and comprising: a phase-frequency detector having an input coupled to the second phase acquisition circuit; a loop filter; a frequency subtractor having an input coupled to the loop filter and an input coupled to the crystal oscillator variation estimator; and a DCO coupled to the frequency subtractor and driving an input of the phase-frequency detector.
Description
Cross Reference to Related Applications
Priority is claimed for this application from U.S. provisional patent application serial No. 62/959,074, filed on 9/2020 and U.S. non-provisional patent application serial No. 16/816,113, filed on 11/3/2020, the contents of each of these patent applications being incorporated herein by reference in their entirety.
Background
The invention relates to clock generation. More particularly, the present invention relates to a circuit and method for generating a temperature-stable clock using a common oscillator.
Many circuit applications require stable frequency and low jitter characteristics of clock circuits. The cost of the temperature compensated crystal oscillator (TCXO) and/or oven controlled crystal oscillator (OCXO) currently required to meet such demands is high. It would therefore be advantageous to provide a solution that allows replacing either the TCXO or the OCXO with a common crystal oscillator (XO).
Disclosure of Invention
In accordance with one aspect of the present invention, a circuit for generating a temperature-stabilized clock includes a first crystal oscillator, a second crystal oscillator, an input for a reference clock source, a clock output, a first phase acquisition circuit coupled to an output of the first crystal oscillator and an output of the second crystal oscillator, a second phase acquisition circuit coupled to the input for the reference clock source and an output of the second crystal oscillator, a first digital phase-locked loop (DPLL) coupled to an output of the first phase acquisition circuit, a crystal oscillator variation estimator coupled to an output of the first DPLL, and a second DPLL coupled to an output of the second phase acquisition circuit, the second DPLL comprising: a phase-frequency detector having a first input coupled to the output of the second phase acquisition circuit; a loop filter; a frequency subtractor having a first input coupled to the output of the loop filter and a second input coupled to the output of the crystal oscillator variation estimator; and a Digitally Controlled Oscillator (DCO) coupled to an output of the frequency subtractor, an output of the DCO being coupled to the second input of the phase-frequency detector and to the clock output.
According to one aspect of the invention, the circuit further comprises a synthesizer coupled to the output of the DCO and driving a clock output.
According to one aspect of the invention, the DCO is a software DCO.
According to one aspect of the invention, the first crystal oscillator and the second crystal oscillator are provided in a single package.
According to an aspect of the invention, the crystal oscillator variation estimator comprises a multiplier having an input coupled to the output of the first DPLL and a second input coupled to a memory storing polynomial coefficients generated during initial production and characterization of the first and second crystal oscillators obtained by curve fitting of a frequency variation of the second crystal oscillator with temperature variation with respect to a frequency difference between the first and second crystal oscillators.
According to one aspect of the invention, the memory is one of a non-volatile memory and a one-time programmable memory.
According to one aspect of the invention, the first crystal oscillator, the second crystal oscillator, and the memory are disposed in a single package.
According to an aspect of the invention, the crystal oscillator variation estimator comprises a multiplier having an input coupled to the output of the first DPLL and a second input coupled to a memory storing polynomial coefficients generated during initial production and characterization of the first and second crystal oscillators obtained by curve fitting of a frequency variation of the second crystal oscillator with temperature variation with respect to a frequency difference between the first and second crystal oscillators.
According to one aspect of the invention, the first DPLL is a high bandwidth DPLL and the second DPLL is a low bandwidth DPLL.
According to one aspect of the invention, the loop filter has one of a 1 st order and a 2 nd order low pass characteristic.
According to one aspect of the invention, a method for generating a temperature-stabilized clock comprises: providing a first crystal oscillator and a second crystal oscillator; providing a memory storing temperature characterizing polynomial coefficients generated during initial production and characterization of the first and second crystal oscillators obtained by curve fitting of the frequency variation of the second crystal oscillator with temperature variation with respect to the frequency difference between the first and second crystal oscillators with temperature variation; measuring a phase difference between the first crystal oscillator and the second crystal oscillator; phase locking a high bandwidth first Digital Phase Locked Loop (DPLL) to the measured phase difference between the first crystal oscillator and the second crystal oscillator; estimating a frequency variation of the second crystal oscillator in response to frequency information based on the measured phase difference and in response to the stored temperature characterizing polynomial coefficients; providing a reference clock signal from a reference clock source; measuring a phase difference between the reference clock signal and the second crystal oscillator; phase locking a second DPLL to the phase difference between the reference clock signal and the second crystal oscillator; adjusting the frequency of the second DPLL by the estimated frequency variation of the second crystal oscillator; and providing an output from the second DPLL.
According to one aspect of the invention, the method further includes providing an output of the second DPLL to a frequency synthesizer.
According to one aspect of the invention, providing the first crystal oscillator and the second crystal oscillator comprises providing the first crystal oscillator and the second crystal oscillator in the same package.
According to one aspect of the invention, measuring the phase difference between the first crystal oscillator and the second crystal oscillator comprises measuring the phase difference between the first crystal oscillator and the second crystal oscillator in a first phase acquisition circuit.
According to one aspect of the invention, measuring the phase difference between the reference clock signal and the second crystal oscillator comprises measuring the phase difference between the reference clock signal and the second crystal oscillator in the second phase acquisition circuit.
In accordance with one aspect of the invention, adjusting the frequency of the second DPLL with the estimated temperature-dependent frequency variation of the second crystal oscillator includes adjusting the frequency of the second DPLL using a frequency subtractor circuit.
In accordance with an aspect of the invention, providing the output of the second DPLL comprises providing the output of the second DPLL from a digitally controlled oscillator in the second DPLL.
According to one aspect of the invention, the method further comprises providing the output of the numerically controlled oscillator to a synthesizer.
Drawings
The invention will be explained in more detail below with reference to embodiments and the accompanying drawings, in which:
FIG. 1 is a block diagram of a circuit for generating a temperature stable, low jitter, any frequency clock using a common oscillator, according to one aspect of the present invention; and is
FIG. 2 is a flow diagram showing an illustrative method for generating a temperature stable, low jitter, any frequency clock using a common oscillator in accordance with an aspect of the present invention.
Detailed Description
Those of ordinary skill in the art will realize that the following description is illustrative only and is not intended to be in any way limiting. Other embodiments will readily occur to those skilled in the art.
The present invention allows the use of a common oscillator that does not have high frequency stability with temperature variations, while maintaining low jitter performance, to generate a temperature stable clock. According to the present invention, a frequency stability result of about 300 parts per billion (ppb) with a 0.2 ℃/minute temperature change over the temperature range of-40 ℃ to 85 ℃ may be achieved when using a first XO14 and a second XO 16 each having a frequency stability of about 10 parts per million (ppm) to about 300ppm disposed in the same package. For the purposes of the present invention, a temperature stable clock signal is one that has a frequency stability of no greater than about 400 ppb. According to the present invention, a jitter of about 150 femtoseconds (fs) RMS may be achieved when using a first XO14 and a second XO 16 disposed in the same package, each of the first XO and the second XO having a jitter of about 50fs to about 150fs RMS. For the purposes of the present invention, the low-jitter output clock signal from the clock generation circuit is a low-jitter output clock signal having a maximum value of about 250fs RMS, and as disclosed herein, is achieved when a synthesizer is employed to generate the output clock.
To achieve such high stability over temperature, the invention can be implemented as part of the synthetic firmware of the timing device and can generate clocks of any frequency. The present invention utilizes the unique characteristic that the frequency difference between two crystal oscillators (XOs) is linear with temperature to predict the temperature characteristic of one of the two oscillators with temperature. Each crystal oscillator is first characterized as a function of temperature and then the appropriate polynomial coefficients representing the characterization are stored for use in the present invention. Specifically, the polynomial coefficient is obtained by curve fitting of the temperature-dependent frequency variation of the second XO 16 with respect to the frequency difference between the first XO14 and the second XO 16 which varies with temperature. The frequency difference between the two oscillators is transferred to a relatively high bandwidth DPLL (on the order of about 20Hz to about 100 Hz) and is used with stored polynomial coefficients to replicate the temperature-dependent frequency drift of the second XO 16 used as the master clock. The replicated frequency drift with temperature will be used to compensate for the actual frequency drift with temperature. The master clock on line 28 is being used to synthesize the clock to be programmed to output any frequency. A temperature change of each of the two crystal oscillators (the first XO14 and the second XO 16) causes a change in the frequency of the output of each of the two crystal oscillators. The present invention predicts the temperature-based variation of the second XO 16 serving as the master clock based on the frequency difference between the two crystal oscillators and corrects the output clock frequency accordingly, thereby minimizing the variation of the output clock frequency with the temperature variation. Using these common XOs with a jitter of about 50fs RMS to about 150fs RMS as described herein allows synthesizing a clock signal with a jitter of less than about 150fs RMS to about 250fs RMS when using a synthesizer to generate the output clock.
One useful application of the present invention is as a companion oscillator for a network-synchronized PLL, but the present invention can be extended to stand-alone TCXOs or OCXOs as alternatives. The present invention replaces the expensive TCXO or OCXO with a common inexpensive XO crystal oscillator and provides faster start-up time and consumes less power than the TCXO or OCXO.
The present invention may utilize programmable system on a chip (SoC) based PLL circuitry to process common oscillator signals and generate a temperature stable clock.
Referring initially to fig. 1, a block diagram illustrates a circuit 10 for generating a temperature-stabilized, low-jitter clock using a common oscillator in accordance with an aspect of the present invention. The circuit 10 includes an oscillator module 12 that includes a first crystal oscillator (XO)14 and a second XO 16 disposed in a single package. As will be understood by those of ordinary skill in the art, each of the first XO14 and the second XO 16 is typically in the form of a module including a crystal, as well as a driver and decoupling capacitors (not explicitly shown). Each of the first XO14 and the second XO 16 is capable of generating a clock having a specific frequency and a prescribed accuracy (about 10ppm to 300 ppm). Frequency stability over temperature is an important property of oscillators used as clock sources for synthesizers generating high temperature stable clocks, and common crystals do not have great frequency stability over temperature (typically hundreds of ppm: -40 ℃ to 85 ℃ in the following industrial temperature range). Temperature Controlled XOs (TCXOs), which typically have a temperature sensor and a control circuit that corrects for frequency variations due to temperature variations, and constant temperature XOs (OCXOs), which have an oven to keep the temperature of the XO constant, exhibit improved stability over temperature variations. The present invention allows the use of crystal oscillators XO14 and XO 16 while providing temperature dependent output clock frequency stability that is typically required using TCXOs or OCXOs.
The clock generation circuit 18 includes a first phase acquisition module 20 and a second phase acquisition module 22. The first phase acquisition module 20 receives the output of the first XO14 on line 24 and the second phase acquisition module 22 receives a reference clock signal from a reference clock source 26 (shown in phantom as being external to the clock generation circuit 18 and provided by the user). The input reference clock source should have a frequency within the telecommunications range (i.e., between about 0.5Hz and 1 GHz) and may be sourced from a primary reference source (e.g., an atomic clock or GPS). When the reference clock source 26 is present, the output of the clock generation circuit 18 is frequency and phase locked with respect to the reference clock source 26.
In accordance with one aspect of the invention, the master clock signal from the output of the second XO 16 on line 28 is used as the basis for the comparison in the first phase acquisition module 20 and the second phase acquisition module 22. The first phase acquisition module 20 measures the phase difference between the output of the first XO14 and the master clock on line 28 and outputs information about the measured phase difference. The second phase acquisition module 22 measures the phase difference between the output of the input reference clock source and the master clock on line 28 and outputs information about the measured phase difference. Circuits for providing this function are known in the art. According to the present invention, the first phase acquisition block 20 and the second phase acquisition block 22 are able to compare the input clock signal with the master clock signal on line 28 even if the input clock signal and the master clock signal do not have the same nominal frequency. For example, the master clock signal on line 28 may be 20MHz and the input reference clock signal may be at 19.44MHz or 1.544MHz or any frequency.
The master clock 28 provides nominal frequency information to a first digital phase-locked loop (DPLL) 30. The output of the first phase acquisition module 20 is presented to the first DPLL 30 to lock the output to the phase difference generated by the first phase acquisition circuit 20. The first DPLL 30 has a low-pass transfer function (angular frequency in the range of about 20Hz to about 100 Hz) with a relatively high bandwidth. The output of the first DPLL 30 is frequency information representing the frequency difference between the first XO14 and the second XO 16. The master clock 28 also provides nominal frequency information for the second DPLL 32. The output of the second phase acquisition module 22 is presented to the second DPLL 32 to lock the output to the phase difference generated by the second phase acquisition circuit 22. The second DPLL 32 has a low-pass transfer function (angular frequency in the range of about 0.001Hz to about 0.3 Hz) with a relatively low bandwidth.
The frequency information at the output of the first DPLL 30 representing the frequency difference between the first XO14 and the second XO 16 is presented to an XO variation estimator 34. The XO variation estimator 34 is a module that estimates the frequency variation of the master clock signal output from the second XO 16 on the line 28 and provides the estimated frequency variation information to the second DPLL 32 to correct the output frequency of the second DPLL 32 so that the frequency variation of the master clock signal output from the second XO 16 on the line 28 due to temperature variations is cancelled.
The input to the XO variation estimator 34 is frequency information representing the frequency difference between the first XO14 and the second XO 16, which is provided by the phase acquisition module 20 and passed through the first DPLL 30. The high bandwidth of the first DPLL 30 provides a fast response to changes in frequency difference due to sudden temperature changes. XO variation estimator 34 includes a multiplier 36 that multiplies the frequency difference information from first DPLL 30 with polynomial coefficients generated during initial production and characterization of the package including XOs 14 and 16 and stored in memory 38. In some embodiments of the invention, memory 38 may be a non-volatile memory (NVM) or a one-time programmable (OTP) memory, and in some embodiments of the invention, memory 38 may be included in package 12 including first XO14 and second XO 16. The polynomial coefficient is obtained by curve fitting of the temperature-dependent frequency variation of the second XO 16 with respect to the frequency difference between the first XO14 and the second XO 16 which varies with temperature. In embodiments of the invention using the Microchip Vectron PX-502-.
The second DPLL 32 includes a phase detector (PFD)40 (implemented, for example, as a subtractor), a loop filter 42, a frequency subtractor 46, and a Digitally Controlled Oscillator (DCO)44 (which may be a Software DCO (SDCO) in some implementations). In the presence of the reference clock signal, phase detector 40, in conjunction with loop filter 42, converts the phase difference between reference clock source 26 and master clock 28 into frequency information related to the frequency difference between reference clock source 26 and master clock 28. The second DPLL 32 has the ability to subtract the frequency between the loop filter 42 and the XO variation estimator 34 by a frequency subtractor 46. The output of the loop filter 42 is fed to a first input of a frequency subtractor 46 and the output of the XO variation estimator 34 is fed to a second input of the frequency subtractor 46. By subtracting the output of the XO change estimator 34 from the output of the loop filter 42, any changes in the frequency of the master clock signal on the master clock signal output line 28 due to temperature changes are compensated for. When the reference clock 26 is present, the output of the clock generation circuit 18 follows the reference clock, and the compensation provided by the frequency subtractor 46 will minimize any drift in the output clock 48 due to changes in the master clock caused by temperature changes, i.e., minimize the drift generation of the output of the clock generation circuit 18. When the reference clock signal is no longer present, the output of loop filter 42 depends only on master clock 28 and will have all of the frequency variations exhibited by master clock 28 as a function of temperature. These frequency variations are compensated in frequency subtractor 46 to improve the holding temperature stability of clock generation circuit 18.
The loop filter 42 is the module that primarily determines the transfer function-or loop bandwidth-of the second DPLL 32 (the transfer function of the second DPLL 32 is also affected by other modules, such as the DCO44, but these modules are considered immutable and are typically ignored for the purpose of specifying the loop bandwidth). The loop filter 42 is preferably a low pass filter with a 3dB attenuation point at a given bandwidth frequency. It typically has a 1 or 2 order low pass characteristic.
In some embodiments, the DCO44 may be implemented in software. As is well known in the art, the DCO44 is typically comprised of an accumulator having as its output a Frequency Control Word (FCW) from a programmable register internal to the DCO. The FCW determines the nominal frequency of the clock at the DCO output. In addition to the FCW, the DCO44 includes another control input for fine tuning the DCO output frequency, and the input is shown in fig. 1 as being driven by the output of the frequency subtractor 46. Thus, when the optional synthesizer 52 is not used, the output of the DCO44 is a temperature compensated output clock signal that can be used as the output 48 of the clock generation circuit 18 via the dashed connection 50.
The output of the DCO44 may optionally be presented to a synthesizer 52 shown in dashed lines. Synthesizer 52 is a module that synthesizes an output clock signal on clock output line 48 at a desired frequency from the master clock on line 28. The desired output clock signal is phase and frequency locked to the output of the DCO 44. In essence, synthesizer 52 performs low-jitter frequency conversion between the master clock signal on line 28 and the desired output frequency, allowing any frequency within the telecommunications range (e.g., between about 0.5Hz and about 1 GHz) with low phase noise (low jitter) to be generated on its output at clock output line 48. The phrase "any frequency" as used herein should be interpreted to mean any frequency within the telecommunications range (e.g., between about 0.5Hz and about 1 GHz).
In embodiments where the DCO44 is configured as a hardware element, the present invention provides a frequency output from the DCO44 or optional synthesizer 52 that is highly frequency stable over temperature using a common oscillator that does not have high frequency stability over temperature. When the DCO44 is implemented as software DCO (sdco), the present invention provides a clock output from the synthesizer 52.
The master clock signal from the second XO 16 on line 28 is connected to and drives each internal block in circuit 18. When used in a circuit, the master clock signal on line 28 is connected to a synthesizer 52. The output clock 48 is always dependent on the master clock because it is synthesized directly from the master clock on line 28 using synthesizer 52 or the hardware version of DCO 44. In implementations where the output clock 50 is driven by the synthesizer 52, fine frequency control of the synthesizer 52 relative to the phase and frequency difference between the reference clock source 26 and the master clock 28 is performed by the output of the DCO 44. The fine frequency control of the synthesizer 52 by the DCO44 is related to the frequency variation in the master clock 28 caused by temperature fluctuations compensated by the XO variation estimator 34 when the reference clock source 26 is no longer present. In embodiments of the invention that do not employ the synthesizer 52, the invention provides high frequency stability over temperature as disclosed herein, but does not provide sufficiently low jitter required by most telecommunications applications. The use of a conventional synthesizer will provide low jitter as disclosed herein.
Once the DPLL 32 is locked to the reference clock source 26 using the second phase acquisition circuit 22, the output clock 48 will have stability inherited from the input reference clock source 26. Using the present invention, the temperature variation of the master clock signal on line 28 from the second XO 16 will be removed, thereby minimizing the drift generation of the output clock 48. With the reference clock source 26 no longer present, the stability of the output on the clock output line 48 is determined only by the stability of the master clock signal on line 28. Using the present invention, the temperature variation of the master clock signal on line 28 from the second XO 16 will be removed, allowing the output clock 48 to have good stability even in the absence of the reference clock source 26.
Referring now to fig. 2, a flow chart illustrates an illustrative method 60 for generating a temperature-stabilized low-jitter clock using a common oscillator in accordance with an aspect of the present invention. The method begins at reference numeral 62.
At reference numeral 64, a first crystal oscillator and a second crystal oscillator are provided. In some embodiments of the invention, the first crystal oscillator and the second crystal oscillator may be disposed together in the same package.
At reference numeral 66, a memory is provided (e.g., in the same package as the first and second crystal oscillators) that stores temperature characterization polynomial coefficients generated during initial production and characterization of the first and second crystal oscillators obtained by curve fitting of the frequency change of the second crystal oscillator as a function of temperature to the frequency difference between the first and second crystal oscillators as a function of temperature.
At reference numeral 68, the phase difference between the first crystal oscillator and the second crystal oscillator is measured, for example, in a first phase acquisition circuit. At reference numeral 70, a high bandwidth first Digital Phase Locked Loop (DPLL) is phase locked to the measured phase difference between the first crystal oscillator and the second crystal oscillator.
At reference numeral 72, a frequency change of the second crystal oscillator is estimated in response to frequency difference information representing a frequency difference between the first crystal oscillator and the second crystal oscillator, and in response to a temperature characteristic of the frequency of the second crystal oscillator relative to the frequency difference between the first crystal oscillator and the second crystal oscillator over temperature.
At reference numeral 74, a reference clock signal is provided to a clock generation circuit.
At reference numeral 76, the phase difference between the reference clock signal and the second crystal oscillator is measured, for example in a second phase acquisition circuit.
At reference numeral 78, the second DPLL is phase-locked to a phase difference between the reference clock signal and the second crystal oscillator. At reference numeral 80, the frequency of the second DPLL is adjusted (e.g., using a frequency subtractor) by the estimated temperature-varying frequency variation of the second crystal oscillator (obtained by, for example, an XO variation estimator). At reference numeral 82, the output of the second DPLL is provided as a clock output.
The output of the second DPLL may optionally be provided to a frequency synthesizer at reference numeral 84 to provide the ability to generate a low jitter clock output having a desired frequency. The method ends at reference numeral 86.
The present invention allows the generation of a temperature stable clock of any frequency, since the clock generation circuit can generate a clock having any frequency within the telecommunications range based on the master clock signal on line 28. The present invention provides clock stability comparable to that achieved using a temperature compensated crystal oscillator as the master clock for the same clock generation circuit. In contrast to using a significantly more expensive TCXO or oven controlled crystal oscillator (OCXO), the present invention provides a cost effective solution to generate any frequency clock that is temperature stable using two inexpensive oscillators. Furthermore, prior art applications requiring both high frequency stability and good jitter require the use of very expensive low jitter TCXOs or OCXOs. The solution provided by the present invention satisfies both low jitter and temperature stability requirements using two common oscillators, which are significantly cheaper than the two prior art solutions described above. The invention can be further extended for use with any two oscillating means whose frequency difference has a fixed well-defined relationship to the temperature change if the temperature change can be measured and characterized to produce the appropriate polynomial coefficients. Such oscillating devices may be, but are not limited to, micro-electro-mechanical systems (MEMS).
The present invention may be employed in frequency synthesis firmware using an additional PLL (first DPLL 30) to correct for frequency variations with temperature variations. The frequency difference between the two crystal oscillators is then measured in the clock generation circuit using existing hardware (first phase acquisition circuit 20 and second phase acquisition circuit 22) and then passed to the first DPLL 30, which is used to perform compensation for the frequency due to changes in the main clock frequency caused by temperature changes. The polynomial coefficients for replicating one of the oscillator temperature changes with respect to the frequency difference between the two oscillators can be stored in a small memory (OTP, EEPROM or Flash) during characterization of the oscillators.
The present invention allows packaging using groupings of different parts. Two crystal oscillators (or resonators) can be packaged in one package with a driver and a small memory. The master clock signal on line 28 of the second XO 16 of the dual oscillator (dual XO) device is fed to the oscillator input of the synthesizer 52 and the output of the first XO14 on line 24 is fed to one of the inputs of the first phase acquisition circuit 20. This solution requires a relatively simple dual XO temperature characterization to obtain the required polynomial coefficients.
In another variation, multiple dies of the clock generation circuit (including the non-volatile memory) and the resonator and passive components may be provided in one package. The polynomial coefficients may be stored in non-volatile memory for storage of other processor code. This solution is compact but presents the challenge of characterizing the oscillator at multiple temperature points due to the high cost of the tester required to test complex packages, which includes clock generation circuitry employing multiple dies with a larger number of I/O pins that can be mounted on a single test board for testing, as compared to testers for XO TCXOs or OCXOs with 4 to 6I/O pins.
In another variation, a prepackaged and characterized dual XO containing a small memory for coefficients is packaged in one package with a clock generation circuit die. This is a compact solution requiring a simple characterization procedure for the crystal oscillator, but increases the complexity of the packaging because the prepackaged dual XO is not small enough to fit easily in another package.
While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art that many more modifications than mentioned above are possible without departing from the inventive concepts herein. Accordingly, the invention is not limited except as by the spirit of the appended claims.
Claims (18)
1. A circuit for generating a temperature-stabilized clock, the circuit comprising:
a first crystal oscillator;
a second crystal oscillator;
an input for a reference clock source;
a clock output terminal;
a first phase acquisition circuit coupled to an output of the first crystal oscillator and an output of the second crystal oscillator;
a second phase acquisition circuit coupled to the input for the reference clock source and an output of the second crystal oscillator;
a first digital phase-locked loop (DPLL) coupled to an output of the first phase acquisition circuit;
a crystal oscillator variation estimator coupled to an output of the first DPLL; and
a second DPLL coupled to an output of the second phase acquisition circuit, the second DPLL comprising:
a phase-frequency detector having a first input coupled to the output of the second phase acquisition circuit;
a loop filter;
a frequency subtractor having a first input coupled to the output of the loop filter and a second input coupled to the output of the crystal oscillator variation estimator; and
a Digitally Controlled Oscillator (DCO) coupled to an output of the frequency subtractor, an output of the DCO coupled to a second input of the phase-frequency detector and to the clock output.
2. The circuit of claim 1, further comprising a synthesizer coupled to the output of the DCO and driving the clock output.
3. The circuit of claim 1, wherein the DCO is a software DCO.
4. The circuit of claim 1, wherein the first and second crystal oscillators are provided in a single package.
5. The circuit of claim 1, wherein the crystal oscillator variation estimator comprises a multiplier having one input coupled to the output of the first DPLL and a second input coupled to a memory storing polynomial coefficients generated during initial production and characterization of the first and second crystal oscillators obtained by curve fitting of frequency variation of the second crystal oscillator with temperature variation with respect to frequency differences between the first and second crystal oscillators.
6. The circuit of claim 5, wherein the memory is one of a non-volatile memory and a one-time programmable memory.
7. The circuit of claim 5, wherein the first crystal oscillator, the second crystal oscillator, and the memory are disposed in a single package.
8. The circuit of claim 1, wherein the crystal oscillator variation estimator comprises a multiplier having one input coupled to the output of the first DPLL and a second input coupled to a memory storing polynomial coefficients generated during initial production and characterization of the first and second crystal oscillators obtained by curve fitting of frequency variation of the second crystal oscillator with temperature variation relative to a frequency difference between the first and second crystal oscillators.
9. The circuit of claim 1, wherein the first DPLL is a high bandwidth DPLL and the second DPLL is a low bandwidth DPLL.
10. The circuit of claim 1, wherein the loop filter has one of a 1 st order and a 2 nd order low pass characteristic.
11. A method for generating a temperature-stabilized clock, the method comprising:
providing a first crystal oscillator and a second crystal oscillator;
providing a memory storing temperature characterization polynomial coefficients generated during initial production and characterization of the first and second crystal oscillators obtained by curve fitting of the temperature-dependent frequency variation of the second crystal oscillator to the frequency difference between the first and second crystal oscillators as a function of temperature;
measuring the phase difference between the first crystal oscillator and the second crystal oscillator;
phase-locking a high-bandwidth first digital phase-locked loop (DPLL) to the measured phase difference between the first crystal oscillator and the second crystal oscillator;
estimating a frequency variation of the second crystal oscillator in response to frequency information based on the measured phase difference and in response to the stored temperature characterizing polynomial coefficients;
providing a reference clock signal from a reference clock source;
measuring the phase difference between the reference clock signal and the second crystal oscillator;
phase-locking a second DPLL to the phase difference between the reference clock signal and the second crystal oscillator;
adjusting the frequency of the second DPLL by the estimated change in frequency of the second crystal oscillator; and
providing an output from the second DPLL.
12. The method of claim 11, further comprising providing the output of the second DPLL to a frequency synthesizer.
13. The method of claim 11, wherein providing the first and second crystal oscillators comprises providing the first and second crystal oscillators in the same package.
14. The method of claim 11, wherein measuring the phase difference between the first and second crystal oscillators comprises measuring the phase difference between the first and second crystal oscillators in a first phase acquisition circuit.
15. The method of claim 11, wherein measuring the phase difference between the reference clock signal and the second crystal oscillator comprises measuring the phase difference between the reference clock signal and the second crystal oscillator in a second phase acquisition circuit.
16. The method of claim 11, wherein adjusting the frequency of the second DPLL with temperature-varying frequency variations estimated by the second crystal oscillator comprises adjusting the frequency of the second DPLL using a frequency subtractor circuit.
17. The method of claim 11, wherein providing the output of the second DPLL comprises providing the output of the second DPLL from a digitally controlled oscillator in the second DPLL.
18. The method of claim 18, further comprising providing the output of the digitally controlled oscillator to a synthesizer.
Applications Claiming Priority (5)
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| US202062959074P | 2020-01-09 | 2020-01-09 | |
| US62/959,074 | 2020-01-09 | ||
| US16/816,113 US10992301B1 (en) | 2020-01-09 | 2020-03-11 | Circuit and method for generating temperature-stable clocks using ordinary oscillators |
| US16/816,113 | 2020-03-11 | ||
| PCT/CA2020/000105 WO2021138730A1 (en) | 2020-01-09 | 2020-08-20 | Circuit and method for generating temperature-stable clocks using ordinary oscillators |
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| CN114902562A true CN114902562A (en) | 2022-08-12 |
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| CN202080091631.2A Pending CN114902562A (en) | 2020-01-09 | 2020-08-20 | Circuit and method for generating temperature-stable clock using common oscillator |
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| CN (1) | CN114902562A (en) |
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| US11811415B2 (en) | 2021-06-18 | 2023-11-07 | Bae Systems Information And Electronic Systems Integration Inc. | Direct digital synthesizer with frequency correction |
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| US10992301B1 (en) | 2021-04-27 |
| WO2021138730A8 (en) | 2022-09-15 |
| DE112020006469T5 (en) | 2022-11-03 |
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