CN114826381A - Satellite-borne regenerative forwarding demodulation and modulation system - Google Patents
Satellite-borne regenerative forwarding demodulation and modulation system Download PDFInfo
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Abstract
The invention provides a satellite-borne regenerative forwarding demodulation and modulation system, which comprises a power supply conversion circuit, a demodulation and modulation circuit and a power supply control circuit, wherein the power supply conversion circuit is used for converting the voltage of an external input power supply into high-precision voltage values required by each circuit according to a certain time sequence; the high-speed ADC circuit is used for completing real-time acquisition of the intermediate frequency modulation signal, converting the intermediate frequency modulation signal into high-speed modulation digital information and sending the high-speed modulation digital information to the SRAM type FPGA circuit; the configuration circuit is used for loading, dynamic refreshing and on-orbit reconstruction of SRAM type FPGA circuit configuration information, receiving remote control signals and acquiring remote measurement signals; the SRAM type FPGA circuit is loaded with a receiving, regenerating and forwarding FPGA program; and the high-speed DAC circuit is used for performing digital-to-analog conversion on the processed high-speed modulation data output by the SRAM type FPGA circuit and converting the processed high-speed modulation data into an intermediate frequency modulation signal for output. The invention can realize data transmission with various rates, automatically learn and train by receiving data, realize extraction of the codebook, complete data comparison and error correction and increase the transmission bandwidth between satellites to be more than Gbps.
Description
Technical Field
The invention relates to the technical field of satellite-borne regenerative forwarding demodulation and modulation systems, in particular to a satellite-borne regenerative forwarding demodulation and modulation system.
Background
The inter-satellite communication system is used for finishing interaction, forwarding and communication of data among satellites, is a necessary component of satellite networking, and therefore effective data can be downloaded by satellites in a ground visual range in a centralized mode.
At present, an inter-satellite communication system adopts a transparent forwarding mode, only data receiving and power amplification are completed and data are forwarded, more noise signals are introduced after the data are processed in a series of steps, and the quality is poor, so that the data transmission rate is not high, and only Mbps data transmission is supported.
With the development of satellite technology, the low-orbit networking satellite constellation becomes a main development and application direction in the aerospace field. At least hundreds of Mbps or even Gbps data are interacted among satellites in a low-orbit networking satellite constellation, an existing inter-satellite communication system is limited by transmission rate and cannot meet data interaction among the satellites in the low-orbit networking satellite constellation, so that a renewable forwarding demodulation modulation unit is needed to be researched to improve the data transmission rate of the inter-satellite communication system and meet the requirement of future high-speed satellite networking communication, wherein the renewable forwarding technology refers to the technology of carrying out receiving, demodulating, decoding, recovering and correcting errors on the data and then carrying out modulation and transmission, and lossless transmission of the data can be realized.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a satellite-borne regenerative forwarding demodulation and modulation system.
The invention provides a satellite-borne regenerative forwarding demodulation and modulation system, which comprises a power supply conversion circuit, an interface circuit, a configuration circuit, an SRAM type FPGA circuit, a high-speed ADC circuit and a high-speed DAC circuit, wherein,
the power supply conversion circuit is used for converting the voltage of an external input power supply into high-precision voltage values required by the interface circuit, the configuration circuit, the SRAM type FPGA circuit, the high-speed ADC circuit and the high-speed DAC circuit according to a certain time sequence;
the high-speed ADC circuit is used for completing real-time acquisition of the intermediate frequency modulation signal, converting the intermediate frequency modulation signal into high-speed modulation digital information and sending the high-speed modulation digital information to the SRAM type FPGA circuit;
the configuration circuit is used for loading, dynamically refreshing and reconstructing on-track of the configuration information of the SRAM type FPGA circuit, receiving the remote control signal, analyzing the control working state, acquiring the remote measurement signal of the SRAM type FPGA circuit and sending the remote measurement signal;
the SRAM type FPGA circuit is loaded with a receiving, regenerating and forwarding FPGA program, and when the receiving, regenerating and forwarding FPGA program is executed, the operation completed comprises the following steps:
remote control and telemetry communication with the configuration circuit;
receiving baseband high-speed serial data sent by an interface circuit, completing serial-parallel conversion, clock locking and synchronization, comma detection and decoding, converting the baseband high-speed serial data into parallel data, processing the parallel data by a digital modulation module, and outputting the parallel data to a high-speed DAC circuit;
receiving high-speed modulation digital information output by a high-speed ADC circuit, completing digital AGC control, coasts ring carrier synchronization, BPSK, QPSK and 8PSK demodulation, Gardner bit synchronization, phase ambiguity resolution, frame header detection and output, sending the output high-speed modulation digital information into a data comparison and error correction module for preliminary processing, outputting the preliminarily processed high-speed modulation digital information through a receiving signal output port of an interface circuit for subsequent processing, and outputting the preliminarily processed high-speed modulation digital information to a high-speed DAC circuit after being processed by a digital modulation module;
the interface circuit is used for receiving baseband high-speed serial data input from the outside, performing conversion processing on the baseband high-speed serial data and sending the baseband high-speed serial data to the SRAM type FPGA circuit, receiving a demodulation signal demodulated and output by the SRAM type FPGA circuit, and converting the demodulation signal into a high-speed serial signal to output;
and the high-speed DAC circuit is used for performing digital-to-analog conversion on the processed high-speed modulation digital information output by the SRAM type FPGA circuit and converting the converted high-speed modulation digital information into an intermediate frequency modulation signal for output.
Optionally, the data comparison and error correction module is configured to complete LDPC decoding of the primarily processed high-speed modulated digital information, automatic codebook training learning and comparison, data error correction, and effective data extraction.
Optionally, the digital modulation module is configured to complete synchronization judgment and synchronization padding frame processing of a data frame of the preliminary high-speed serial data, data scrambling, channel coding, BPSK, QPSK, 8PSK constellation mapping, digital shaping filtering, and CIC decimation filtering, and output the I/Q quadrature modulation and DDR data to the high-speed DAC circuit.
Optionally, the interface circuit comprises a high-speed serial interface FPGA program, wherein,
when the high-speed serial interface FPGA program is executed, the high-speed parallel data is converted into serial sending data, the received high-speed serial data is converted into the high-speed parallel data for data processing, and the high-speed serial interface FPGA program adopts an 8-Bit/10-Bit coding and decoding mode.
Optionally, the configuration circuit includes an antifuse FPGA and a parallel FLASH, the antifuse FPGA loads the configuration information stored in the parallel FLASH into the SRAM-type FPGA circuit, and the configuration circuit communicates with other units through the communication circuit.
Optionally, the configuration circuit is further loaded with a configuration FPGA program, and when the FPGA configuration program is executed, the configuration circuit is configured to complete loading, dynamic refreshing, and on-track reconstruction of the SRAM-type FPGA circuit configuration information, receive the remote control signal, analyze the control operating state, acquire the telemetry signal of the SRAM-type FPGA circuit, and send the telemetry signal.
Optionally, the high-speed ADC circuit includes a first sampling clock circuit and a high-speed ADC chip, where the first sampling clock circuit is composed of a crystal oscillator and a phase-locked source, the crystal oscillator provides a crystal oscillator signal for the phase-locked source, and the phase-locked source performs phase locking on the crystal oscillator signal to generate a clock signal and outputs the clock signal to the high-speed ADC chip.
Optionally, the high-speed DAC circuit includes a second sampling clock circuit and a high-speed DAC chip, and the second sampling clock circuit generates a clock signal output to the high-speed DAC chip.
Optionally, the power conversion circuit includes a plurality of power circuits and a plurality of voltage stabilizing circuits, input ends of the power circuits and the voltage stabilizing circuits are connected to an external power supply, and output ends of the power circuits and the voltage stabilizing circuits are connected to the interface circuit, the configuration circuit, the SRAM type FPGA circuit, the high-speed ADC circuit, and the high-speed DAC circuit.
Compared with the prior art, the invention has the following beneficial effects:
the satellite-borne reproducible forwarding demodulation and modulation system provided by the invention has the advantages that the demodulation and modulation system has full-digital demodulation, decoding, data comparison, error correction and modulation, and can realize the functions of multiple coding modes, multiple modulation modes and multiple rate data transmission; BPSK, QPSK, 8PSK demodulation can be realized, LDPC decoding can be realized, automatic learning training can be carried out through received data, extraction of a codebook is realized, data comparison and error correction are completed, integrated transmission among satellites, ground and relays can be met, and the transmission bandwidth among satellites is increased to be more than Gbps.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
fig. 1 is a schematic architecture diagram of a satellite-borne regenerative forwarding demodulation and modulation system provided in the present invention;
FIG. 2 is a schematic diagram of a power conversion circuit provided in the present invention;
FIG. 3 is a schematic diagram of an interface circuit provided by the present invention;
FIG. 4 is a schematic diagram of a configuration circuit provided by the present invention;
FIG. 5 is a schematic diagram of an SRAM type FPGA circuit provided by the present invention;
FIG. 6 is a schematic diagram of a high speed ADC circuit according to the present invention;
fig. 7 is a schematic diagram of a high-speed DAC circuit according to the present invention.
In the figure: 1. a power supply conversion circuit; 2. an SRAM type FPGA circuit; 3. a high-speed DAC circuit; 4. an interface circuit; 5. a configuration circuit; 6. high speed ADC circuitry.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
As shown in fig. 1, the demodulation and modulation system for satellite-borne regenerative forwarding in the present invention may include a power conversion circuit 1, an interface circuit 4, a configuration circuit 5, an SRAM type FPGA circuit 2, a high-speed ADC circuit 6, and a high-speed DAC circuit 3, wherein,
the power supply conversion circuit 1 is used for converting the voltage of an external input power supply into high-precision voltage values required by the interface circuit 4, the configuration circuit 5, the SRAM type FPGA circuit 2, the high-speed ADC circuit 6 and the high-speed DAC circuit 3 according to a certain time sequence;
the high-speed ADC circuit 6 is used for completing the real-time acquisition of the intermediate frequency modulation signal, converting the intermediate frequency modulation signal into high-speed modulation digital information and sending the high-speed modulation digital information to the SRAM type FPGA circuit 2;
the configuration circuit 5 is used for loading, dynamically refreshing and reconstructing on-track of configuration information of the SRAM type FPGA circuit 2, receiving a remote control signal, analyzing a control working state, acquiring and sending a remote measurement signal of the SRAM type FPGA circuit 2, wherein the remote control signal and the remote measurement signal are baseband data generally;
the SRAM type FPGA circuit 2 is loaded with a receiving, regenerating and forwarding FPGA program, and when the receiving, regenerating and forwarding FPGA program is executed, the operations to be completed include:
remote control and telemetry communication with the configuration circuit 5;
receiving baseband high-speed serial data sent by the interface circuit 4, completing serial-parallel conversion, clock locking and synchronization, comma detection and decoding, converting the baseband high-speed serial data into parallel data, wherein the parallel data is generally 16 bits, outputting the parallel data to a high-speed DAC circuit after being processed by a digital modulation module, outputting 16 paths of parallel data, and outputting the parallel data after the parallel-serial conversion, wherein 8-Bit/10-Bit coding is required;
receiving high-speed modulation digital information output by the high-speed ADC circuit 6, completing digital AGC control, coasts ring carrier synchronization, BPSK, QPSK and 8PSK demodulation, Gardner bit synchronization, phase ambiguity resolution, frame header detection and output, sending the output high-speed modulation digital information into a data comparison and error correction module for preliminary processing, outputting the preliminarily processed high-speed modulation digital information through a receiving signal output port of an interface circuit for subsequent processing, and outputting the preliminarily processed high-speed modulation digital information to the high-speed DAC circuit 3 after being processed by the digital modulation module;
the data comparison and error correction module is used for completing LDPC decoding of high-speed modulation digital information subjected to preliminary processing, automatic codebook training learning and comparison, data error correction and effective data extraction.
The digital modulation module is used for completing synchronous judgment and synchronous filling frame processing of a data frame of preliminary high-speed modulation digital information, data scrambling, channel coding, BPSK, QPSK, 8PSK constellation mapping, digital forming filtering and CIC extraction filtering, and I/Q quadrature modulation and DDR data are output to the high-speed DAC circuit 3;
the FPGA of the SRAM type FPGA circuit 2 can be Virtex-7 series FPGA, the FPGA has low core voltage, large current and high requirements on ripples, noise and the like of a power supply, and a high-speed ADC chip and a high-speed DAC chip require mixed power supply of digital voltage and analog voltage, require extremely low noise of the power supply and have high requirements on power-on time sequence. The power supply conversion circuit converts a positive 5.5V power supply into a plurality of different output voltages through a multi-channel power supply conversion chip, a low-dropout linear regulator, a high-precision voltage monitoring circuit and a high-current and high-suppression power supply filter network, and meets the power supply requirements of Virtex-7 series FPGA, high-speed ADC chips and high-speed DAC chips.
An interface circuit 4 for receiving externally input baseband high-speed serial data, performing conversion processing, sending the baseband high-speed serial data to the SRAM-type FPGA circuit 2, receiving a demodulation signal demodulated and output by the SRAM-type FPGA circuit 2, and converting the demodulation signal into a high-speed serial signal for output;
and the high-speed DAC circuit 3 is used for performing digital-to-analog conversion on the processed high-speed modulation data output by the SRAM type FPGA circuit 2 and converting the processed high-speed modulation data into an intermediate frequency modulation signal for output.
Referring to fig. 2, in practical applications, the power conversion circuit 1 may convert a 5.5V power into a digital power and an analog power, the power conversion circuit generally includes a plurality of power circuits and a plurality of voltage stabilizing circuits, the input terminals of the power circuits and the voltage stabilizing circuits are connected to an external power, the output terminals of the power circuits and the voltage stabilizing circuits are connected to the interface circuit 4, the configuration circuit 5, the SRAM-type FPGA circuit 2, the high-speed ADC circuit 6, and the high-speed DAC circuit 3, wherein the power circuit may adopt a power chip of model HNFA0516 to convert a 5.5V power into +1.0V, the power supply capacity reaches 32A, the power chips of the HNFA0516 may select a corresponding number according to needs to meet the power supply requirements of the SRAM-type FPGA circuit, the voltage stabilizing circuit may adopt a plurality of sets of serial RSS 8 voltage stabilizing chips and RSW1101, in this embodiment, the RSS 8 voltage stabilizing chip may convert a 5.5V power into + 0501.5V power, The voltage of +3.3VD, +1.5V, +3.3VD, +1.8V, +4.0V produces ultra-low noise +1.2V, +2.5V, +3.3V power through RSW1101 steady voltage chip, voltage stabilizing circuit still includes independent RSS0508 steady voltage chip, independent RSS0508 steady voltage chip can convert the power of 5.5V into +1.8V, voltage stabilizing circuit still includes RSW1201 steady voltage chip, RSW1201 steady voltage chip can convert the power of 5.5V into the power of +5.0V, each power finishes the power-on sequence control through enable end and Powergood pin of above-mentioned each chip, the power that each chip produced is exported to each circuit after the power filter network of the high current, high suppression degree.
Referring to fig. 3, in practical applications, the interface circuit 4 generally includes two clock amplification circuits, wherein the clock amplification circuit selects ADCLK925AF/QMLR, which can amplify the GTX channel output signal of the SRAM-type FPGA circuit to meet the requirement of long-distance transmission; the 2711 signals output by other units can be amplified and sent to a GTX channel of an SRAM type FPGA circuit for receiving, the interface circuit also comprises a high-speed serial interface FPGA program, wherein,
when the FPGA program is executed, the baseband high-speed serial data is converted into serial sending data, the received high-speed modulation digital information is converted into high-speed parallel data for data processing, the high-speed serial interface FPGA program adopts an 8-Bit/10-Bit coding and decoding mode, the problem that the level of the TLK2711 circuit is not matched with that of the SRAM type FPGA interface is effectively solved, and long-distance single-unit signal transmission can be realized.
Referring to fig. 4, in practical application, the configuration circuit 5 generally includes an antifuse FPGA and a parallel FLASH, the antifuse FPGA loads configuration information stored in the parallel FLASH into the SRAM-type FPGA circuit 2, and the configuration circuit communicates with other units through a communication circuit, and further includes a power-on reset circuit, a reference crystal oscillator, an AD telemetry acquisition circuit, an RSS422 circuit, and the like. The anti-fuse FPGA selects AX500-1PQ208I of Actel company to complete loading and dynamic refreshing of configuration information of the SRAM type FPGA circuit 2, complete remote control and remote measurement acquisition, and carry out remote control and remote measurement communication through an RSS422 circuit. A512M chip VDRF512M16VS56IB8V90 is selected as the parallel FLASH, the quality level is an enterprise SS level, and the parallel FLASH is used for storing configuration information of an SRAM type FPGA. The reference crystal oscillator is ZA70CB3-16.000MHz to provide a reference clock for the work of the AX500 chip, the power-on reset circuit is realized by adopting an RC delay reset circuit and a reverse trigger, the anti-fuse FPGA is reset at the power-on moment, the AD telemetering acquisition circuit adopts a CAST-level chip B128S102RH to acquire the junction temperature and other analog quantities of the module, and a digital signal is sent to the AX500 chip. The RSS422 circuit adopts JSR26CLV32F and JSR26CLV31AF to realize remote control and telemetry communication;
the configuration circuit 5 is also loaded with a configuration FPGA program, when the FPGA configuration program is executed, the configuration circuit is used for completing the loading, dynamic refreshing and on-track reconstruction of the SRAM type FPGA circuit configuration information, receiving a remote control signal, analyzing a control working state, collecting and sending a remote measurement signal of the SRAM type FPGA circuit 2, and loading a configuration file for a receiving regeneration forwarding FPGA to start the work of the receiving regeneration forwarding FPGA; refreshing the SRAM type FPGA circuit 2 according to the received refresh enabling signal; receiving remote control information sent from the outside through an RSS422 circuit, analyzing an instruction, and sending the instruction to an SRAM type FPGA circuit 2; and the telemetering information such as the working state and the like sent by the SRAM type FPGA circuit 2 and the telemetering signals sent by the AD telemetering acquisition circuit are packed according to a frame format and sent out of the configuration circuit through the RSS422 circuit.
Referring to FIG. 5, the SRAM type FPGA circuit 2 is mainly composed of XC7VX690T-3FFG1761I from Xilinx corporation. The SRAM type FPGA circuit includes an FPGA software: and receiving the regeneration forwarding FPGA. The receiving, regenerating and forwarding FPGA mainly completes remote control and remote measurement communication with the configuration circuit; receiving high-speed modulation digital information sent by an interface circuit, completing serial-parallel conversion, clock locking and synchronization, comma detection, 8-Bit/10-Bit decoding, converting the digital information into 16-Bit parallel data, and outputting the data to a high-speed DAC circuit after digital modulation; receiving high-speed modulation digital information output by a high-speed ADC circuit, completing digital AGC control, coasts ring carrier synchronization, BPSK, QPSK, 8PSK demodulation, Gardner bit synchronization, phase ambiguity resolution, frame header detection and output, sending output data into a data comparison and error correction for data processing, performing subsequent processing through an interface circuit output unit, and outputting the output data to a high-speed DAC circuit after digital modulation; data comparison and error correction: completing LDPC decoding of data, automatic training learning and comparison of a codebook, data error correction, effective data extraction, and data output to an interface circuit or digital modulation; digital modulation: finishing high-speed data frame synchronization judgment and synchronous filling frame processing, data scrambling, channel coding, BPSK, QPSK, 8PSK constellation mapping, digital shaping filtering and CIC extraction filtering, and outputting I/Q quadrature modulation and DDR data to a high-speed DAC circuit; data transmission: and 8-Bit/10-Bit coding is carried out on the 16 paths of parallel data to be sent, and the data are output after parallel-serial conversion.
Referring to fig. 6, in practical application, the high-speed ADC circuit 6 mainly includes a high-speed ADC chip, a crystal oscillator, a PDRO (phase locked source), and a BALUN, where the high-speed ADC chip is an enterprise V-class chip EV12AQ600 of E2V; BALUN selects BAL-0006SMG of Marki company, crystal oscillator selects 100MHz, PDRO output is 6.4GHz, high-speed ADC chip receives 6.4GHz clock, receives intermediate frequency modulation signal, converts analog signal into 32-channel digital signal, transmits to GTX channel of SRAM type FPGA circuit 2 through high-speed serial port, and transmits 1/32 of sampling clock to SRAM type FPGA circuit 2 for data processing.
Referring to fig. 7, in practical application, the high-speed DAC circuit 3 mainly includes a high-speed DAC chip, a crystal oscillator, a PDRO, and a BALUN. The high-speed DAC chip is an enterprise V-level chip EV10DS130AMGS9NB1 of E2V company; BALUN is the BAL-0003SMG product of Marki company. The crystal oscillator adopts 100MHz, and the PDRO output is 3 GHz; the high-speed DAC circuit 3 converts the input working clock into a differential signal through the BALUN, and inputs the differential signal to the DAC chip, which is the working clock of the DAC chip. The high-speed DAC circuit divides the frequency of the received working clock by 8 and outputs the divided frequency to the SRAM type FPGA circuit 2 as a main clock for data processing of the SRAM type FPGA circuit 2, and the high-speed DAC circuit 3 receives signals such as high-speed differential data and the like output by the SRAM type FPGA circuit 2 to perform digital-to-analog conversion, converts the signals into differential analog signals and converts the differential analog signals into intermediate-frequency analog signals through a BALUN (BALUN transformer). The working clock of the high-speed DAC circuit is 3GHz, and the output intermediate-frequency analog signal is 2.4 GHz.
The crystal oscillator provides a crystal oscillator signal for the phase-locked source, and the phase-locked source performs phase locking on the crystal oscillator signal so as to generate a clock signal and output the clock signal to the high-speed ADC chip.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (9)
1. The demodulation and modulation system for satellite-borne reproducible forwarding is characterized by comprising a power supply conversion circuit, an interface circuit, a configuration circuit, an SRAM type FPGA circuit, a high-speed ADC circuit and a high-speed DAC circuit,
the power supply conversion circuit is used for converting the voltage of an external input power supply into high-precision voltage values required by the interface circuit, the configuration circuit, the SRAM type FPGA circuit, the high-speed ADC circuit and the high-speed DAC circuit according to a certain time sequence;
the high-speed ADC circuit is used for completing real-time acquisition of intermediate frequency modulation signals, converting the intermediate frequency modulation signals into high-speed modulation digital information and sending the high-speed modulation digital information to the SRAM type FPGA circuit;
the configuration circuit is used for loading, dynamically refreshing and reconstructing the configuration information of the SRAM type FPGA circuit on track, receiving a remote control signal, analyzing a control working state, collecting a remote control signal of the SRAM type FPGA circuit and sending the remote control signal;
the SRAM type FPGA circuit is loaded with a receiving, regenerating and forwarding FPGA program, and when the receiving, regenerating and forwarding FPGA program is executed, the operation completed comprises the following steps:
remotely and telemetrically communicating with the configuration circuit;
receiving baseband high-speed serial data sent by the interface circuit, completing serial-parallel conversion, clock locking and synchronization, comma detection and decoding, converting the baseband high-speed serial data into parallel data, processing the parallel data by a digital modulation module, and outputting the parallel data to the high-speed DAC circuit;
receiving high-speed modulation digital information output by the high-speed ADC circuit, completing digital AGC control, coasts ring carrier synchronization, BPSK, QPSK and 8PSK demodulation, Gardner bit synchronization, phase ambiguity resolution, frame header detection and output, sending the output high-speed modulation digital information into a data comparison and error correction module for preliminary processing, outputting the preliminarily processed high-speed modulation digital information through a receiving signal output port of the interface circuit for subsequent processing, and outputting the preliminarily processed high-speed modulation digital information to the high-speed DAC circuit after being processed by the digital modulation module;
the interface circuit is used for receiving baseband high-speed serial data input from the outside, performing conversion processing on the baseband high-speed serial data, sending the baseband high-speed serial data to the SRAM type FPGA circuit, receiving a demodulation signal demodulated and output by the SRAM type FPGA circuit, and converting the demodulation signal into a high-speed serial signal for outputting;
and the high-speed DAC circuit is used for performing digital-to-analog conversion on the processed high-speed modulation digital information output by the SRAM type FPGA circuit and converting the converted high-speed modulation digital information into an intermediate frequency modulation signal for output.
2. The on-board regenerative forwarding demodulation and modulation system according to claim 1, wherein: the data comparison and error correction module is used for completing LDPC decoding, automatic codebook training learning and comparison, data error correction and effective data extraction of the primarily processed high-speed modulation digital information.
3. The on-board regenerative forwarding demodulation and modulation system according to claim 1, wherein: the digital modulation module is used for completing synchronous judgment of a data frame of the preliminary high-speed serial data, synchronous filling frame processing, data scrambling, channel coding, BPSK, QPSK, 8PSK constellation mapping, digital shaping filtering and CIC extraction filtering, I/Q quadrature modulation and DDR data output to the high-speed DAC circuit.
4. The on-board regenerative forwarding demodulation and modulation system according to claim 1, wherein: the interface circuit includes a high-speed serial interface FPGA program, wherein,
when the high-speed serial interface FPGA program is executed, converting high-speed parallel data into serial sending data, receiving high-speed serial data and converting the high-speed serial data into the high-speed parallel data for data processing, wherein the high-speed serial interface FPGA program adopts an 8-Bit/10-Bit coding and decoding mode.
5. The on-board, regenerable-to-forward demodulation and modulation system of claim 1, wherein the configuration circuit comprises an antifuse FPGA and a parallel FLASH, the antifuse FPGA loads configuration information stored in the parallel FLASH into the SRAM-type FPGA circuit, and the configuration circuit communicates with other units through a communication circuit.
6. The on-board demodulation and modulation system for reproducible forwarding according to claim 2, wherein the configuration circuit is further loaded with a configuration FPGA program, and when the FPGA configuration program is executed, the configuration circuit is configured to complete loading, dynamic refreshing and on-track reconstruction of the configuration information of the SRAM-type FPGA circuit, receive a remote control signal and analyze a control operation state, and collect and transmit a telemetry signal of the SRAM-type FPGA circuit.
7. The on-board demodulation and modulation system according to claim 6, wherein the high-speed ADC circuit comprises a first sampling clock circuit and a high-speed ADC chip, wherein the first sampling clock circuit is composed of a crystal oscillator and a phase-locked source, the crystal oscillator provides a crystal oscillator signal for the phase-locked source, and the phase-locked source phase-locks the crystal oscillator signal to generate a clock signal and outputs the clock signal to the high-speed ADC chip.
8. The on-board regenerative forwarding demodulation modulation system according to claim 1 wherein the high-speed DAC circuit comprises a second sampling clock circuit and a high-speed DAC chip, the second sampling clock circuit generating a clock signal output to the high-speed DAC chip.
9. The satellite-borne reproducible forwarding demodulation and modulation system according to claim 1, wherein the power conversion circuit comprises a plurality of power circuits and a plurality of voltage stabilizing circuits, the input ends of the power circuits and the voltage stabilizing circuits are connected to an external power supply, and the output ends of the power circuits and the voltage stabilizing circuits are connected to the interface circuit, the configuration circuit, the SRAM type FPGA circuit, the high-speed ADC circuit and the high-speed DAC circuit.
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