CN114816273A

CN114816273A - Adaptive optimal configuration method, device and medium for Norflash

Info

Publication number: CN114816273A
Application number: CN202210736672.3A
Authority: CN
Inventors: 汪季英; 董宗宇
Original assignee: Hangzhou Youzhilian Technology Co ltd
Current assignee: Hangzhou Youzhilian Technology Co ltd
Priority date: 2022-06-27
Filing date: 2022-06-27
Publication date: 2022-07-29
Anticipated expiration: 2042-06-27
Also published as: CN114816273B

Abstract

The embodiment of the invention discloses a method, a device and a medium for adaptive optimal configuration of Norflash; the method can comprise the following steps: establishing a project for realizing the function of the Norflash carried on the SOC based on the debugging function of the SRAM so as to compile and obtain a debugging file comprising the optimal configuration parameters corresponding to the Norflash; after power-on starting, correspondingly entering a bootrom program execution stage, storing the debugging file in a memory and the head of a Norflash storage space by running the bootrom program; after the application program is powered on and started, correspondingly entering an application program execution stage, writing the debugging file stored at the head of the storage space of the Norflash into a memory to configure the Norflash and the corresponding QSPI bus according to the optimal configuration parameters in the debugging file, so that when the application program runs, the Norflash runs in an XIP mode based on the optimal configuration parameters.

Description

Adaptive optimal configuration method, device and medium for Norflash

Technical Field

The embodiment of the invention relates to the technical field of chips, in particular to a method, a device and a medium for adaptive optimal configuration of an encoding type flash memory Norflash.

Background

The Norflash memory is characterized by an on-chip execution (XIP), i.e., during execution of an application program, a processor can directly fetch instructions from the Norflash memory for subsequent decoding and execution without reading the instructions or codes into a system RAM.

In order to be compatible with various types of Norflash in use, the conventional scheme at present sets a configuration parameter by default so as to satisfy the requirement that the Norflash of various types can run in the XIP mode.

However, for each type of Norflash, taking a queue serial peripheral interface (QSPI, Quad SPI) in a peripheral circuit as an example, default configuration parameters set by a register of a corresponding QSPI are only used for satisfying that the corresponding Norflash operates in an XIP mode, and cannot be enabled to operate in an optimal configuration. Therefore, in the conventional scheme, even if the Norflash can operate in the XIP mode, the operation speed is still low.

Disclosure of Invention

In view of this, embodiments of the present invention are to provide a method, an apparatus, and a medium for adaptive optimal configuration of Norflash; the Norflash can be operated in the XIP mode under the condition of optimal configuration, so that the operation speed of the Norflash in the XIP mode is increased.

The technical scheme of the embodiment of the invention is realized as follows:

in a first aspect, an embodiment of the present invention provides a method for adaptive optimal configuration of an encoded flash memory Norflash, where the method includes:

establishing a project for realizing the function of the Norflash loaded on the SOC based on the debugging function of the SRAM so as to compile and obtain a debugging file comprising the optimal configuration parameters corresponding to the Norflash;

after power-on starting, correspondingly entering a bootrom program execution stage, storing the debugging file in a memory and the head of a storage space of the Norflash by running the bootrom program;

after the power-on starting, correspondingly entering an application program execution stage, writing the debugging file stored at the head of the storage space of the Norflash into a memory to configure the Norflash and the corresponding QSPI bus according to the optimal configuration parameters in the debugging file, so that when the application program runs, the Norflash runs in an XIP mode based on the optimal configuration parameters.

In a second aspect, an embodiment of the present invention provides an apparatus for adaptive optimal configuration for Norflash, where the apparatus includes: the system comprises a creation part, a bootrom program execution part and an application program execution part; wherein the content of the first and second substances,

the creation part is configured to create a project for realizing the function of the Norflash loaded on the System On Chip (SOC) based on the debugging function of the Static Random Access Memory (SRAM) so as to compile and obtain a debugging file including the optimal configuration parameters corresponding to the Norflash;

the bootrom program execution part is configured to store the debugging file in a memory and the head of a storage space of the Norflash by running a bootrom program corresponding to entering a bootrom program execution stage after being powered on and started;

the application program execution part is configured to, after the application program is powered on and started, write the debugging file stored at the head of the storage space of the Norflash into a memory corresponding to an application program execution stage to configure the Norflash and the corresponding QSPI bus according to optimal configuration parameters in the debugging file, so that when the application program runs, the Norflash runs in an XIP mode based on the optimal configuration parameters.

In a third aspect, an embodiment of the present invention provides a computer storage medium storing a program for adaptive optimal configuration for Norflash, where the program for adaptive optimal configuration for Norflash implements the method steps for adaptive optimal configuration for Norflash in the first aspect when executed by at least one processor.

The embodiment of the invention provides a method, a device and a medium for adaptive optimal configuration of Norflash; establishing a project for the Norflash loaded on the SOC by utilizing a function of loading and debugging codes at the SRAM, and compiling to obtain a debugging file comprising the optimal configuration parameters corresponding to the Norflash; and then copying the debugging file to the head of the storage space of the Norflash through a bootrom program when the power is on and started, so that when the application program is executed, the debugging file stored at the head of the storage space of the Norflash is written into a memory to optimally configure the Norflash and a corresponding QSPI bus, and therefore when the application program is executed, the Norflash runs in an XIP mode under the condition of optimal configuration, and the running speed of the Norflash in the XIP mode is further improved.

Drawings

Fig. 1 is a schematic diagram of a system on chip that can be applied to the technical solution described in the embodiment of the present invention.

Fig. 2 is a schematic flowchart of a method for adaptive optimal configuration of Norflash according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a Norflash memory address according to an embodiment of the present invention.

Fig. 4 is a schematic diagram of an apparatus configured for adaptive optimal Norflash according to an embodiment of the present invention.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

Referring to fig. 1, there is shown the composition of an exemplary (and simplified) System On Chip (SOC) 100 that can be adapted for use with the solutions set forth in the embodiments of the present invention. Note that the composition shown in fig. 1 is only one example of possible SOC compositions, and embodiments of the present disclosure may be implemented in any of a variety of SOC compositions as desired.

As shown in fig. 1, SOC 100 includes: the processor 110, the on-chip memory 120, the off-chip memory 130, and various buses, of course, in the specific implementation process, those skilled in the art may add adaptable components on the basis of the structure shown in fig. 1 according to the needs of an actual scenario, and details of this embodiment of the present invention are not described here.

In some examples, the Processor 110 may be a general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components. The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The content disclosed in connection with the embodiments of the present invention may be directly embodied as the execution of the hardware decoding processor, or may be implemented by the combination of hardware and software modules in the decoding processor.

In some examples, the on-chip Memory 120 may include a Read-Only Memory (ROM) 121 and a Random Access Memory (RAM) 122; the processor 110 may be connected to the on-chip memory 120 via an on-chip bus 140. It should be noted that, in general, the processor 110, the on-chip memory 120, and the on-chip bus 140 may be referred to as an SOC chip in some implementations, as shown in fig. 1.

In some examples, the off-chip memory 130 may include a coded Flash memory (Norflash) 131, and may also include a storage Flash memory (NAND Flash) 132 in some other examples; processor 110 may be coupled to off-chip memory 130 via an off-chip bus 150, such as Norflash 131 via QSPI bus 151.

In some examples, the processor 110 may include a QSPI controller 111 capable of performing read and write operations with the Norflash 131, and may further include a bootrom program 112 for booting up and upgrading the SOC 100.

For SOC 100 shown in fig. 1, processor 110 enables Norflash 131 to implement XIP mode of operation via QSPI bus 151 via QSPI controller 111. However, manufacturers are not even compatible with the Norflash 131 types of manufacturers, so that in the conventional chip design process, a default configuration parameter is set in the QSPI register that can be called by the QSPI controller 111, so that the finally designed SOC 100 can meet the requirement that the Norflash of various types can be operated in the XIP mode.

On the other hand, the various types of Norflash correspond to optimal configuration parameters, such as the maximum clock of the QSPI bus, and fast read and write command words, and the optimal configuration parameters can enable the various types of Norflash to achieve the optimal operation effect, and the optimal configuration parameters corresponding to the various types of Norflash are different. Therefore, the default configuration parameters adopted in the conventional scheme only satisfy the condition that various types of Norflash can operate in the XIP mode, but cannot enable various types of Norflash to operate in the XIP mode under the optimal configuration. For example, in the default configuration parameters adopted in the conventional scheme, the QSPI register usually does not set the maximum frequency division that the corresponding QSPI bus can actually reach, and the read-write command words are basic read-write command words rather than fast read and write command words, which results in the condition that the best performance of Norflash is sacrificed for realizing compatibility. Therefore, the embodiment of the invention is expected to provide a scheme for adaptive optimal configuration of Norflash, which can enable Norflash to operate in an XIP mode under the condition of optimal configuration compared with the conventional scheme, thereby improving the operating speed of Norflash in the XIP mode. Based on this, referring to fig. 2 in conjunction with the SOC 100 shown in fig. 1, a method for adaptive optimal configuration for Norflash according to an embodiment of the present invention is shown, which may be applied to the exemplary SOC 100 shown in fig. 1, and the method may include:

s201: creating a project for realizing the function of the Norflash loaded on the SOC 100 based on the debugging function of a Static Random-Access Memory (SRAM) so as to compile and obtain a debugging file including the optimal configuration parameters corresponding to the Norflash;

s202: after power-on starting, correspondingly entering a bootrom program execution stage, storing the debugging file in a memory and the head of a storage space of the Norflash by running the bootrom program;

s203: after the power-on starting, correspondingly entering an application program execution stage, writing the debugging file stored at the head of the storage space of the Norflash into a memory to configure the Norflash and the corresponding QSPI bus according to the optimal configuration parameters in the debugging file, so that when the application program runs, the Norflash runs in an XIP mode based on the optimal configuration parameters.

For the technical scheme shown in fig. 2, a project is created for the Norflash loaded on the SOC by using a function of loading and debugging codes at the SRAM, so as to compile and obtain a debugging file including optimal configuration parameters corresponding to the Norflash; and then copying the debugging file to the head of the storage space of the Norflash through a bootrom program when the power is on and started, so that when the application program is executed, the debugging file stored at the head of the storage space of the Norflash is written into a memory to optimally configure the Norflash and a corresponding QSPI bus, and therefore when the application program is executed, the Norflash runs in an XIP mode under the condition of optimal configuration, and the running speed of the Norflash in the XIP mode is further improved.

For the technical solution shown in fig. 2, in some possible implementation manners, the creating, by the SRAM-based debug function, a project for implementing a Norflash function loaded on the SOC 100 to compile a debug file including optimal configuration parameters corresponding to the Norflash, includes:

determining optimal configuration parameters of the Norflash loaded on the SOC, wherein the optimal configuration parameters at least comprise: the optimal clock frequency of the QSPI bus of the Norflash and the fast read and write command words of the Norflash;

establishing engineering on the Norflash through the SRAM to realize initialization, chip signals and read-write erasing functions of the Norflash;

and debugging the engineering related to the Norflash, establishing the engineering according to the correct interface function after confirming that the interface function related to the Norflash is correct, and compiling by combining the optimal configuration parameters to obtain an axf file comprising the optimal configuration parameters corresponding to the Norflash.

For the above implementation, it should be noted that, for Norflash, the optimal configuration includes the maximum clock corresponding to QSPI and fast read and write command words. In the current Norflash chips on the market, some basic command names are the same, such as reading deviceid 0x9F, read data 0x03, write enable 0x06, read status, etc., but the Norflash chip models are different for fast read/write command words, such as dual read/write and quad read/write. Specifically, after the Norflash chip is fixedly mounted on the SOC 100, the optimal clock frequency of the Norflash fast read/write command word and the QSPI bus can be determined based on the connection of the QSPI bus and the chip manual of the Norflash mounted on the SOC 100. For example, taking a non-flash chip of the winbond W25Q64JV model as an example, the bus is QSPI, and the optimal configuration can be determined as follows: the QSPI bus clock is divided by 4 of the system clock, the fastest Read command word is Fast Read queue I/O (0xEB), and the Fast write command word is queue Input Page Program (0x 32). After the optimal configuration parameters are determined, engineering can be established through the SRAM to realize the functions of initialization, chip model, reading, writing, erasing and the like of Norflash, debugging is carried out, after the interface function of Norflash is confirmed to have no problem through debugging, the interface functions are additionally engineered, and the axf file with redirection is recompiled. The axf file now includes the optimal configuration parameters described above.

For the technical solution shown in fig. 2, in some possible implementations, after the power-on startup, corresponding to entering a bootrom program execution phase, the step of storing the debug file in a memory and a header of a storage space of the Norflash by running the bootrom program includes:

after power-on starting, determining the pin level of BOOT0, and entering the bootrom program when the pin level is low;

reading the debugging file from the SRAM according to the function that the bootrom program can jump to the SRAM;

and storing the debugging file in a memory and an address header 1M of a storage space of the Norflash.

For the foregoing implementation, in some examples, the storing the debug file in a memory and at an address header 1M of a storage space of the Norflash includes:

storing the debugging file in a memory,

loading the optimal configuration parameters in the debugging file when the bootrom program is executed through the debugging file in the SOC execution memory;

and the bootrom program writes the debugging file into an address header 1M of a storage space of the Norflash according to the quick write command word in the optimal configuration parameters.

For the above implementation and examples thereof, it should be noted that, after the SOC 100 is powered on and started, the level on the BOOT0 pin is read first, and if the level is low, a BOOT program is entered; if the level is high, the XIP mode is performed, that is, the application program in Norflash is run. The implementation and the example thereof correspondingly illustrate that the bootrom program stage is entered, that is, the BOOT0 pin is at low level; at this time, the bootrom program phase is expected to be upgraded for the application program and store the application program in a specified position of the storage space of the Norflash chip. For example, if the address of Norflash chip at address 00 corresponds to the mapped address of 0x09000000 in the processor, the range is 64M, and the XIP mode boot code is usually run from the code at 0x09100000, then 1M space before the XIP mode boot code can store the aforementioned debug file obtained by executing S201.

In addition, the execution process of the bootrom program is to finally program the bin file of the application program to the corresponding Norflash address, and then, by the above example, after the optimal configuration parameters are loaded, the bootrom program can store the application program in the Norflash according to the optimal configuration parameters, thereby completing the execution process of the bootrom program. In detail, except that the address header 1M of the Norflash memory space stores the debug file, and the XIP mode start code starts at 0x09100000, as shown in fig. 3, the address of the Norflash memory space can be used for storing the execution file of the application program from 2M, specifically, the bootrom program uses the loaded optimal configuration parameters to burn the bin file content of the application program to the corresponding Norflash according to the hex file information, and the address is stored at the address after the 2M space.

For the above implementation and examples thereof, it should be further noted that, in the specific implementation process, the bootrom program cannot determine the signal of the external Norflash chip before being solidified, so that the fast read/write command word cannot be determined. The implementation mode and the example thereof utilize the dynamic loading of the axf file, and the optimal configuration parameters of the axf file are applied to the process of burning the debugging file and the application program to the Norflash, so that the writing speed of the high bootrom can be provided.

For the technical solution shown in fig. 2, in some possible implementations, after the power-on startup, corresponding to entering an application program execution phase, writing the debug file stored in the head of the storage space of the Norflash into a memory to configure the Norflash and the corresponding QSPI bus according to optimal configuration parameters in the debug file, so that when the application program runs, the Norflash runs in an XIP mode based on the optimal configuration parameters, including:

after power-on starting, determining the pin level of BOOT0, and when the pin level is high level, indicating that the application program is executed;

copying a debugging file stored at the head part 1M of the storage space of the Norflash to a memory through sequential addressing, and configuring the Norflash and a corresponding QSPI bus according to the optimal configuration parameters by utilizing the loading function of the debugging file;

when the position of the application program in the storage space of the Norflash is sequentially addressed, the Norflash runs in an XIP mode based on the optimal configuration parameters to execute the application program.

For the above implementation, specifically, in the design of the application program, the axf file stored at address 00 of norfalse needs to be copied to the memory; then, calling an interface of the QSPI by using the function of a dynamic loader of the axf file to optimally configure the QSPI; it should be noted that, when the QSPI is optimally configured, the interrupt needs to be turned off, so that the execution speed of the XIP mode can be increased.

In addition to the above, the advantages of the above technical solution and the implementation manner and example thereof can be explained by a comparative experiment in which the mapping space of the processor 110 for the Norflash 131 externally connected to the QSPI interface 151 is set to start from 0x09000000 and range is 64M. The XIP start code is run from the code at 0x09100000, and the previous 1M address (0x 09000000 to 0x090 FFF) is used to store the axf file of the optimal configuration parameters of the Norflash, so that it is recommended that at least 2Mbytes and more are needed for the external Norflash space to meet the execution requirement of the application, and in the comparative experiment, the external Norflash chip is of the type winbond W25Q64 JV.

In conventional approaches, the default configuration of the QSPI controller 111 of the processor 110 is as follows: QSPI clock configuration is 8 frequency division of a system clock, a Read command word of the QSPI is Read Data (03h) of a single line, and SPI bus transmission is actually adopted; in connection with what is stated in the foregoing example, these configuration parameters, although not the optimal configuration parameters of the winbond W25Q64JV model Norflash chip, still enable the signal Norflash chip to operate in XIP mode.

By adopting the scheme provided by the embodiment of the invention, the optimal configuration parameters in the axf file are loaded after the code is executed by virtue of the dynamic loading function of the configuration file, namely the axf file, so that the Read Data command word is changed into Fast Read queue I/O (EBh), and a QUAD-SPI bus is adopted. The maximum frequency of the QSPI clock is determined by debugging codes in the engineering started from the SRAM, and the maximum frequency of the QSPI clock is determined by 4 frequency division of a system clock through debugging verification. With the scheme provided by the embodiment of the invention, the execution speed of the XIP mode is 8 times that of the conventional scheme. Thereby the advantages of the aforementioned technical solution and its implementations and examples can be verified even more.

Based on the same inventive concept of the foregoing technical solution, referring to fig. 4, an apparatus 40 for adaptive optimal configuration for Norflash according to an embodiment of the present invention is shown, where the apparatus 40 may be applied to the SOC 100 shown in fig. 1, and the apparatus 40 includes: a creation section 401, a bootrom program execution section 402, and an application program execution section 403; wherein the content of the first and second substances,

the creating part 401 is configured to create a project for implementing a function of Norflash loaded on the system on chip SOC based on a debugging function of the static random access memory SRAM, so as to compile and obtain a debugging file including optimal configuration parameters corresponding to the Norflash;

the bootrom program executing part 402 is configured to, after being powered on and started, store the debug file in the memory and the head of the storage space of the Norflash by running the bootrom program, corresponding to entering a bootrom program executing stage;

the application program executing portion 403 is configured to, after power-on startup, write the debug file stored at the head of the storage space of the Norflash into the memory corresponding to entering an application program executing stage, so as to configure the Norflash and the corresponding QSPI bus according to the optimal configuration parameters in the debug file, so that when the application program runs, the Norflash runs in an XIP mode based on the optimal configuration parameters.

In some examples, the creation portion 401 is configured to:

In some examples, the bootrom program execution section 402 is configured to:

storing the debugging file in a memory,

In some examples, the bootrom program execution portion 402 is further configured to:

the bootrom program utilizes the loaded optimal configuration parameters to burn and write the bin file content of the application program to the corresponding Norflash according to the hex file information, and the address is stored at the address behind the 2M space;

in some examples, the application execution part 403 is configured to:

when the application program is sequentially addressed to the position of the application program in the storage space of the Norflash, the Norflash runs in an XIP mode based on the optimal configuration parameters to execute the application program.

It is understood that in this embodiment, "part" may be part of a circuit, part of a processor, part of a program or software, etc., and may also be a unit, and may also be a module or a non-modular.

In addition, each component in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit. The integrated unit can be realized in a form of hardware or a form of a software functional module.

Based on the understanding that the technical solution of the present embodiment essentially or partly contributes to the prior art, or all or part of the technical solution may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to execute all or part of the steps of the method of the present embodiment. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The present embodiment therefore provides a computer-readable medium, which stores a program for adaptive optimal configuration for Norflash, where the program for adaptive optimal configuration for Norflash, when executed by at least one processor, implements the method steps for adaptive optimal configuration for Norflash in the foregoing technical solutions.

It can be understood that the above exemplary technical solution of the apparatus 40 for adaptive optimal configuration of Norflash belongs to the same concept as the above technical solution of the method for adaptive optimal configuration of Norflash, and therefore, the above detailed contents of the technical solution of the apparatus 40 for adaptive optimal configuration of Norflash, which are not described in detail, can be referred to the above description of the technical solution of the method for adaptive optimal configuration of Norflash. The embodiments of the present invention will not be described in detail herein.

It should be noted that: the technical schemes described in the embodiments of the present invention can be combined arbitrarily without conflict.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A method for adaptive optimal configuration of an encoding type flash memory Norflash, the method comprising:

2. The method of claim 1, wherein the SRAM-based debug function creates a project for implementing a function of Norflash loaded on the SOC to compile a debug file including optimal configuration parameters corresponding to the Norflash, and comprises:

3. The method as claimed in claim 1, wherein the step of storing the debug file in the memory and the head of the storage space of the Norflash by running a bootrom program after the power-on start corresponding to entering the bootrom program execution phase comprises:

4. The method as claimed in claim 3, wherein the storing the debug file in the memory and at the address header 1M of the storage space of the Norflash comprises:

storing the debugging file in a memory,

5. The method of claim 3, further comprising:

and the bootrom program burns and writes the bin file content of the application program to the corresponding Norflash according to the hex file information by using the loaded optimal configuration parameters, and the address is stored to the address behind the 2M space.

6. The method as claimed in claim 1, wherein after the power-on start, in response to entering an application program execution phase, writing the debug file stored in the head of the Norflash memory space into a memory to configure Norflash and the corresponding QSPI bus according to optimal configuration parameters in the debug file, so that when the application program runs, the Norflash runs in an XIP mode based on the optimal configuration parameters, including:

7. An apparatus for adaptive optimal configuration for Norflash, the apparatus comprising: the system comprises a creation part, a bootrom program execution part and an application program execution part; wherein the content of the first and second substances,

the creating part is configured to create a project for realizing the function of the Norflash loaded on the System On Chip (SOC) based on the debugging function of the Static Random Access Memory (SRAM) so as to compile and obtain a debugging file comprising the optimal configuration parameters corresponding to the Norflash;

8. The apparatus according to claim 7, wherein the creation section is configured to:

9. The apparatus of claim 7, wherein the bootrom program execution section is configured to:

10. A computer-storage medium, characterized in that it stores a program for adaptive optimal configuration for Norflash, which when executed by at least one processor implements the method steps for adaptive optimal configuration for Norflash as claimed in any one of claims 1 to 6.