CN114791768A

CN114791768A - Computer system and electronic equipment based on brain-computer interface

Info

Publication number: CN114791768A
Application number: CN202210720719.7A
Authority: CN
Inventors: 施路平; 李鸿屹; 赵蓉; 马松辰
Original assignee: Tsinghua University
Current assignee: Tsinghua University
Priority date: 2022-06-24
Filing date: 2022-06-24
Publication date: 2022-07-26
Anticipated expiration: 2042-06-24
Also published as: WO2023246226A1; CN114791768B

Abstract

The invention relates to a computer system and electronic equipment based on a brain-computer interface, wherein the computer system comprises a plurality of acquisition devices, an external control circuit of a neuromorphic chip, the neuromorphic chip and feedback devices; the plurality of acquisition devices are used for acquiring a plurality of electrophysiological signals and sending the plurality of electrophysiological signals to the external control circuit; the external control circuit is used for converting the electrophysiological signals into a plurality of target signals capable of being processed by the neuromorphic chip and sending the target signals to the neuromorphic chip; the neuromorphic chip is used for processing each target signal to obtain a processing result of each target signal; integrating the processing results of all the target signals into a feedback result, and sending the feedback result to feedback equipment through an external control circuit; the feedback device is used for modulating the target brain area based on the feedback result. The disclosed embodiments can implement these multi-modal brain-computer interface algorithms with high efficiency and low latency.

Description

Computer system and electronic equipment based on brain-computer interface

Technical Field

The present disclosure relates to the field of electroencephalogram information processing system design technologies, and in particular, to a computer system and an electronic device based on a brain-computer interface.

Background

The brain-computer interface is a technology established between the brain and an external environment, so that the brain can communicate with the outside under the condition of not depending on peripheral nerve and muscle tissues, and specifically comprises two directions of brain control and brain control. In order to obtain effective neural signals at high temporal resolution and high spatial resolution, more and more brain-computer interfaces have a prominent multi-modal feature: and (4) integrating the neural signals from different brain areas and different acquisition methods to realize neural signal analysis. The multi-modal brain-computer interface has been developed for various applications including wheelchair control and unmanned aerial vehicle flight control. With the increasing use of artificial intelligence algorithms with significant demands on computing power for the analysis of brain-computer interface signals, how to implement these multi-modal brain-computer interface algorithms with high efficiency and low delay becomes an urgent problem to be solved.

Disclosure of Invention

The invention provides a computing system and electronic equipment based on a brain-computer interface, which can realize a multi-mode brain-computer interface algorithm with high efficiency and low delay.

According to an aspect of the present disclosure, there is provided a brain-computer interface based computing system comprising a plurality of acquisition devices, an external control circuit of a neuromorphic chip, and a feedback device; wherein, the first and the second end of the pipe are connected with each other,

the plurality of acquisition devices are used for acquiring a plurality of electrophysiological signals and sending the electrophysiological signals to the external control circuit;

the external control circuit is used for converting the electrophysiological signals into a plurality of target signals capable of being processed by the neuromorphic chip after receiving the electrophysiological signals and sending the target signals to the neuromorphic chip;

the neuromorphic chip is used for processing each target signal after receiving the plurality of target signals to obtain a processing result of each target signal; integrating the processing results of all target signals into a feedback result, and sending the feedback result to the feedback equipment through the external control circuit;

the feedback device is used for modulating the target brain area based on the feedback result.

In one possible implementation, the plurality of electrophysiological signals correspond to one or more signal classes.

In one possible implementation, the signal classes include one or more of brain electrical signals, brain magnetic signals, and local field potentials.

In one possible implementation, the plurality of electrophysiological signals correspond to one or more acquisition sites.

In one possible implementation, the acquisition site comprises one or more of a brain, a heart, and muscles, wherein the brain comprises a plurality of brain regions, each brain region representing an acquisition site.

In one possible implementation, the external control circuit is configured to convert the plurality of electrophysiological signals into a plurality of target signals capable of being processed by the neuromorphic chip, and includes:

the external control circuit is used for recoding any electrophysiological signal to obtain a target signal with a coding format matched with the neuromorphic chip.

In one possible implementation manner, the neuromorphic chip includes an integration module and a plurality of execution modules, each execution module corresponds to one neural network algorithm, and each execution module can process a target signal corresponding to one signal type and/or a target signal corresponding to one acquisition part;

the integration module is used for determining an execution module for processing the target signal from the execution modules according to the signal type and/or the acquisition part corresponding to the target signal after receiving any one target signal, and sending the target signal to the determined execution module;

the execution module is used for processing the target signal based on a corresponding neural network algorithm after receiving any one target signal to obtain a processing result of the target signal, and sending the processing result to the integration module.

In a possible implementation manner, the integration module is further configured to integrate the processing results corresponding to the same signal type into a first result, and integrate the first results corresponding to the signal types into the feedback result.

In a possible implementation manner, the integration module communicates with any one of the execution modules through a handshake protocol, and the inside of the integration module and the inside of any one of the execution modules communicate through a network on chip. :

according to an aspect of the present disclosure, there is provided an electronic device including an external control circuit of a neuromorphic chip and the neuromorphic chip; wherein the external control circuit is configured to receive a plurality of electrophysiological signals from an acquisition device, convert the plurality of electrophysiological signals to a plurality of target signals capable of being processed by the neuromorphic chip, and send the plurality of target signals to the neuromorphic chip; the neuromorphic chip is used for processing each target signal after receiving the plurality of target signals to obtain a processing result of each target signal; and integrating the processing results of all the target signals into a feedback result, and sending the feedback result to feedback equipment through the external control circuit.

In the embodiment of the disclosure, a high-efficiency and low-delay multi-modal brain-computer interface algorithm is realized based on a neuromorphic chip.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure.

FIG. 1 shows a schematic diagram of a processor of an embodiment of the disclosure.

Fig. 2 illustrates an architecture diagram of a brain-computer interface based computing system provided by an embodiment of the present disclosure.

Fig. 3 shows an architecture diagram of a brain-computer interface based computing system provided by an embodiment of the present disclosure.

Fig. 4 shows an implementation schematic diagram of an integration process provided by the embodiment of the present disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

The term "and/or" herein is merely an association relationship describing an associated object, and means that there may be three relationships, for example, a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, and may mean including any one or more elements selected from the group consisting of A, B and C.

Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.

With the intensive research of artificial intelligence algorithms and non-von neumann hardware architectures, many new types of hardware and systems, such as rapidly iteratively developed image processors (GPUs), multi-core chips, many-core chips, deep learning accelerators, neuromorphic chips, and general brain-like computing chips, have appeared. Unlike traditional Central Processing Units (CPUs), GPUs and other general-purpose processors with centralization features, neuromorphic chips featuring a many-core architecture have typical decentralization features. The neural morphological chip has important advantages when being used for brain simulation, neural engineering modeling and neural network acceleration, and the characteristics of the processor also provide optimization space for the support of a multi-modal brain-computer interface algorithm.

FIG. 1 shows a schematic diagram of a processor of an embodiment of the disclosure. The processor includes a plurality of computing cores.

In one possible implementation, as shown in fig. 1, the computing core includes a processing component and a storage component. The processing component comprises a dendrite unit, an axon unit, a cell body unit and a routing unit. The memory unit includes a plurality of memory cells.

In a possible implementation manner, a plurality of processors can be integrated into a brain-like computing chip, which is a neural morphological circuit integrated with a computer, and the processing mode of the brain is taken as a reference, so that the processing efficiency is improved and the power consumption is reduced by simulating the transmission and processing of information by neurons in the brain. Each processor can comprise a plurality of computing cores, and different tasks can be processed independently among the computing cores or the same task can be processed in parallel, so that the processing efficiency is improved. The computing cores can perform inter-core information transmission through the routing units in the computing cores.

Within the computing core, processing components and storage components may be provided. The processing means may comprise a dendrite unit, an axon unit, a soma unit and a routing unit. The processing component can simulate the processing mode of neurons of the brain on information, wherein a dendritic unit is used for receiving signals, an axonal unit is used for sending spike signals, a soma unit is used for integrated transformation of the signals, and a routing unit is used for information transmission with other computing cores. The processing unit in the computing core may perform read-write access on multiple storage units of the storage unit to perform data interaction with the storage unit in the computing core, and may respectively undertake respective data processing tasks and/or data transmission tasks to obtain data processing results, or perform communication with other computing cores. Wherein communicating with other computing cores includes communicating with other computing cores within the present processor, as well as communicating with computing cores within other processors.

In one possible implementation, the Membrane Potential (Membrane Potential) is the Potential difference created between two solutions separated by a Membrane. Communication between neural cells can be achieved using membrane potentials. Each computation core in the brain-like computation chip can simulate the mode of information transmission and processing by nerve cells in the brain by using membrane potential.

In one possible implementation, the Memory unit may be a Static Random Access Memory (SRAM). For example, an SRAM with a read/write width of 16B and a capacity of 12KB may be included. The third memory unit MEM2 may receive cell body unit read operation parameters for performing nonlinear operation, or may receive routing unit read routing table for data communication. The present disclosure does not limit the read and write width and capacity of the memory cell.

The embodiment of the present disclosure provides a brain-computer interface-based computing system, which is implemented based on a neuromorphic chip (e.g., a brain-like computing chip shown in fig. 1), so as to implement a brain-computer interface algorithm for performing multiple modalities with high efficiency and low delay.

Fig. 2 shows an architecture diagram of a brain-computer interface based computing system provided by an embodiment of the present disclosure. As shown in fig. 2, the computing system includes a plurality of acquisition devices 21, an external control circuit 22 of the neuromorphic chip, a neuromorphic chip 23, and a feedback device 24.

The acquisition device 21 may be used to acquire electrophysiological signals. In the disclosed embodiment, the computing system includes a plurality of acquisition devices 21, and a plurality of electrophysiological signals can be acquired by the plurality of acquisition devices 21. As shown in fig. 2, the computing system includes three acquisition devices 21 for acquiring three electrophysiological signals, which are: electrophysiological signals 1, 2 and 3. Here, the electrophysiological signal 1 represents an electroencephalogram acquired from the apical lobe region 1 of the brain, the electrophysiological signal 2 represents an electroencephalogram acquired from the frontal lobe region of the brain, and the electrophysiological signal 3 represents an electrocardiogram acquired from the heart.

It should be noted that fig. 2 is only an exemplary illustration of an acquisition device, and is not used to limit acquisition devices included in a computing system, the computing system may include more or less acquisition devices than the acquisition devices shown in fig. 2, the acquisition devices included in the computing system may be set as needed, and the embodiments of the present disclosure are not limited.

In one possible implementation, the plurality of electrophysiological signals may correspond to one or more signal classes. In one example, the signal classes may include one or more of brain electrical signals, brain magnetic signals, and local field potentials. The ElectroEncephaloGram signal may be an ElectroEncephaloGram (EEG) or the like, the magnetoencephalogram or the like, and the local field potential may be an ElectroCardioGram (ECG) or the like. For example, as shown in fig. 2, the signal types corresponding to the electrophysiological signals 1 and 2 are electroencephalogram signals (specifically, electroencephalogram), and the signal type corresponding to the electrophysiological signals 3 is local field potential (specifically, electrocardiogram).

In one possible implementation, the plurality of electrophysiological signals can correspond to one or more acquisition sites. In one example, the acquisition site may include one or more of the brain, heart, and muscle. For example, the plurality of electrophysiological signals may each correspond to a brain or each correspond to a heart or each correspond to a muscle, or a part of the plurality of electrophysiological signals corresponds to a brain and another part corresponds to a heart. In addition, portions of the plurality of electrophysiological signals correspond to other acquisition locations such as a wrist, ankle, or abdomen. For example, as shown in fig. 2, the corresponding collection sites of the electrophysiological signals 1 and 2 are the brain, and the corresponding collection site of the electrophysiological signal 3 is the heart.

In one possible implementation, one acquisition site may include multiple regions. For example, the brain may include multiple brain regions. In one example, consider a human having four lobes per hemisphere (where the frontal lobe is in the foremost part of the brain, the parietal lobe is in the upper part of the back of the frontal lobe, the temporal lobe is in the lower part of the back of the frontal lobe, and the occipital lobe is in the rearmost part of the brain), each lobe corresponding to a brain region, i.e., the brain may include four brain regions. Of course, in the embodiment of the present disclosure, based on the user requirement, the electrophysiological signals of a part of the four brain areas may be collected, and the electrophysiological signals of all of the four brain areas may also be collected, which is not limited in this embodiment of the present disclosure. For example, as shown in fig. 2, the collection site corresponding to the electrophysiological signal 1 is the apical lobe region of the brain, and the collection site corresponding to the electrophysiological signal 2 is the frontal lobe region of the brain.

After acquiring the electrophysiological signals, the acquisition device 21 can transmit the acquired electrophysiological signals to the external control circuit 22 of the neuromorphic chip.

The neuromorphic chip's external control circuitry 22 may be configured to receive the plurality of electrophysiological signals, and then convert the plurality of electrophysiological signals into a plurality of target signals capable of being processed by the neuromorphic chip 23. As shown in fig. 2, the neuromorphic chip's external control circuit 22 may convert the electrophysiological signal 1 into the target signal 1, the electrophysiological signal 2 into the target signal 2, and the electrophysiological signal 3 into the target signal 3.

In the disclosed embodiment, the target signal may represent a signal that can be processed by the neuromorphic chip 23, one electrophysiological signal corresponding to one target signal. In one example, the neuromorphic chip's external control circuitry 22 may be used to re-encode any one of the electrophysiological signals, resulting in a target signal with an encoding format that is compatible with the neuromorphic chip. Since the encoding format of the target signal is adapted to the neuromorphic chip 23, the target signal can be processed by the neuromorphic chip 23. For example, the target signal may be a pulse signal, and the recoding of the electrophysiological signal is to convert the electrophysiological signal into the pulse signal. The manner of re-encoding may refer to related technologies, which are not described herein again.

After the signal conversion is completed, the neuromorphic chip's external control circuitry 22 may send a plurality of target signals to the neuromorphic chip 23.

The neuromorphic chip 23 may be configured to, after receiving the plurality of target signals, process each target signal to obtain a processing result of each target signal; and integrating the processing results of the target signals into a feedback result. The structure of the neuromorphic chip 23 can be referred to fig. 1, and is not described herein again.

The neuromorphic chip 23 may process each received target signal to obtain a processing result of each target signal, and integrate the processing results of the target signals into a total feedback result. As shown in fig. 2, the neuromorphic chip 23 may process the target signal 1, the target signal 2, and the target signal 3, respectively, to obtain a processing result 1 of the target signal 1, a processing result 2 of the target signal 2, and a processing result 3 of the target signal 3, and integrate the processing results 1, 2, and 3 into a total feedback result.

In one possible implementation, the neuromorphic chip 23 may include an integrating module 231 and a plurality of executing modules 232. Each execution module 232 corresponds to a neural network algorithm, and each execution module 232 can process a target signal corresponding to one signal type and/or a target signal corresponding to one acquisition part. After receiving any one target signal, the integrating module 231 may be configured to determine, according to the signal type and/or the acquisition location corresponding to the target signal, an executing module 232 that processes the target signal from the multiple executing modules 232, and send the target signal to the determined executing module 232 for processing.

In the disclosed embodiment, different neural network algorithms are deployed in the form of data streams on the neuromorphic chip, each neural network algorithm being executed by one execution module 232. In the software view, each data stream running on the neuromorphic chip 23 is essentially a neural network algorithm, and after being processed by a compiler integrated with a neural network mapping algorithm, an execution program that can be deployed on the neuromorphic chip, i.e., the execution module 232, can be generated.

In the embodiment of the disclosure, the neural network algorithm corresponding to each execution module is configurable, and the processor and the computing core occupied by each execution module are also configurable. In this way, the computing system provided by the embodiment of the present disclosure may implement processing of electrophysiological signals of different signal types and different acquisition locations by configuring execution modules corresponding to different signal types and different acquisition locations, thereby implementing these multi-modal brain-computer interface algorithms with high efficiency and low delay.

In a possible implementation manner, the inside of the integrating module 231 and the inside of any one of the executing modules 232 communicate through a Network on Chip (NoC), and the integrating module 231 and any one of the executing modules 232 may communicate through a handshake protocol. The network on chip and the handshake protocol may refer to related technologies, which are not described herein again.

Each electrophysiological signal corresponds to a target signal, taking into account that each electrophysiological signal has a corresponding signal class and a corresponding acquisition site. Thus, each target signal has a corresponding signal type and a corresponding acquisition site, and the signal type and the corresponding acquisition site corresponding to the target signal coincide with the signal type and the corresponding acquisition site corresponding to the electrophysiological signal converted into the target signal. As shown in fig. 2, the signal type and the collection portion corresponding to the electrophysiological signal 1 are "electroencephalogram" and "apical lobe region of brain", respectively, and the signal type and the collection portion corresponding to the target signal 1 are "electroencephalogram" and "apical lobe region of brain", respectively.

Fig. 3 shows an architecture diagram of a brain-computer interface based computing system provided by an embodiment of the present disclosure. As shown in fig. 3, on the basis of fig. 2, the neuromorphic chip 23 includes an integrating module 231 and a plurality of executing modules 232. In fig. 3, it is assumed that the type and the collection portion of the target signal that can be processed by the execution module 232 (for convenience of description, the execution module a) in the upper left corner of the neuromorphic chip 23 are "electroencephalogram" and "brain apical lobe region", respectively, the type and the collection portion of the target signal that can be processed by the execution module 232 (for convenience of description, the execution module B) in the lower left corner are "electroencephalogram" and "brain frontal lobe region", respectively, and the type and the collection portion of the target signal that can be processed by the execution module 232 (for convenience of description, the execution module C) in the lower right corner are "electrocardiogram" and "heart", respectively. After receiving the target signal 1, the integration module 231 selects the execution module a to process the target signal 1 according to the signal type and the acquisition part corresponding to the target signal 1; after receiving the target signal 2, selecting an execution module B to process the target signal 2 according to the signal type and the acquisition part corresponding to the target signal 2; and after receiving the target signal 3, selecting the execution module C to process the target signal 3 according to the signal type and the acquisition part corresponding to the target signal 3.

Any one of the execution modules 232 may be configured to, after receiving any one of the target signals, process the target signal based on a neural network algorithm corresponding to the execution module 232 to obtain a processing result of the target signal, and send the processing result to the integration module 231. As shown in fig. 3, after receiving the target signal 1, the execution module a processes the target signal 1 based on the neural network algorithm corresponding to the execution module a to obtain a processing result 1. And after the execution module B receives the target signal 2, processing the target signal 2 based on a neural network algorithm corresponding to the execution module B to obtain a processing result 2. And after receiving the target signal 3, the execution module C processes the target signal 3 based on the neural network algorithm corresponding to the execution module C to obtain a processing result 3.

The integration module 231 may be configured to integrate the processing results from the respective execution modules 232 into a feedback result. Fig. 4 shows an implementation schematic diagram of an integration process provided by the embodiment of the present disclosure. As shown in fig. 4, on the basis of fig. 3, the execution module a sends the processing result 1 to the integration module 231; the execution module B sends the processing result 2 to the integration module 231; the execution module C sends the processing result 3 to the integration module 231. After that, the integration module 231 may integrate the processing result 1, the processing result 2, and the processing result 3 to obtain a feedback result.

In a possible implementation manner, the integration module 231 may be configured to integrate the processing results corresponding to the same signal type into a first result, and integrate the first results corresponding to the respective signal types into a feedback result. In fig. 4, the signal type corresponding to the execution module a and the execution module B is "electroencephalogram", and the signal type corresponding to the execution module C is "electrocardiogram", and therefore, the signal type corresponding to the processing result 1 and the processing result 2 is "electroencephalogram", and the signal type corresponding to the processing result 3 is "electrocardiogram". As shown in fig. 4, after receiving the processing result 1, the processing result 2 and the processing result 3, the integrating module 231 integrates the processing result 1 and the processing result 2 into a first result corresponding to the signal category of "electroencephalogram", and determines the processing result 3 as a first result corresponding to the signal category of "electrocardiogram"; then, the first result corresponding to the signal category "electroencephalogram" and the first result corresponding to the signal category "electrocardiogram" are integrated into a feedback result.

In the embodiment of the present disclosure, a hierarchical design is performed during processing result integration, and the processing result integration is performed according to signal categories, and then each signal category is integrated together. The hierarchical design considers the event triggering characteristic of the neuromorphic chip, so that the computing system provided by the embodiment of the disclosure can realize low power consumption when facing a complex multi-modal electrophysiological signal processing scene. It should be noted that the plurality of electrophysiological signals corresponding to different signal types and/or different corresponding acquisition locations are multi-modal electrophysiological signals.

It should be noted that the execution modules shown in fig. 3 and fig. 4 are only examples and are not used to limit the execution modules included in the neuromorphic chip, in practical applications, the neuromorphic chip may include more or less execution modules than the execution modules shown in fig. 3 and fig. 4, and the number and the types of the execution modules included in the neuromorphic chip are not limited in the embodiment of the present disclosure.

Fig. 4 also shows an example of a network structure of the neural network algorithm corresponding to the execution module, and the network structure of the neural network algorithm corresponding to the execution module is not limited in the embodiment of the present disclosure.

As shown in fig. 2, the neuromorphic chip 23, after obtaining the feedback results, may send the feedback results to the feedback device 24 via the neuromorphic chip's external control circuitry 22.

The feedback device 24 may be used to modulate the target brain region based on the feedback results. The target brain region may be any region of the brain. The target brain region can be set as desired. The feedback device 24 may be a neuromodulation device.

In contrast to pharmaceutical interventions, the feedback device-based interventions provided by embodiments of the present disclosure enable accurate localization of a target brain region within the brain. Common nerve regulation and control methods based on feedback equipment include but are not limited to a sub-convulsive electroshock therapy, an electrospasm therapy, a neurosurgical implantation therapy and the like, and a computing system provided by the embodiment of the disclosure can be well adapted to various nerve regulation and control equipment, so that a multi-modal and multi-level comprehensive synergistic treatment technology is provided for brain disease control and treatment.

The computing system provided by the embodiment of the disclosure can realize a closed-loop brain-computer interface based on a neuromorphic chip, so that a multi-modal brain-computer interface algorithm can be realized with high efficiency and low delay. The computing system provided by the embodiment of the disclosure can be used for epilepsy detection or drowsiness detection and the like, and has very important significance in promoting treatment of neurological diseases. Because the neural network algorithm executed by the execution module in the neuromorphic chip in the embodiment of the disclosure is configurable, the computing system provided by the embodiment of the disclosure has universality for other various brain-computer interface applications, and can realize multi-modal (corresponding to various signal types and various acquisition parts) brain-computer interface algorithms with high efficiency and low delay.

In addition, the computing system provided by the embodiment of the disclosure is suitable for parallel execution, cooperative modulation and optimization of brain-computer interface algorithms based on complex neural network tasks, especially hierarchical, multi-modal and multi-task neural networks. Meanwhile, in the embodiment of the disclosure, the multi-mode electrophysiological signals can be processed locally without transmitting the electrophysiological signals to a remote server, thereby reducing propagation delay and improving efficiency.

The embodiment of the present disclosure also provides an electronic device, which includes an external control circuit of a neuromorphic chip and the neuromorphic chip; the external control circuit is used for receiving a plurality of electrophysiological signals from the acquisition equipment, converting the electrophysiological signals into a plurality of target signals capable of being processed by the neuromorphic chip and sending the target signals to the neuromorphic chip; the neuromorphic chip is used for processing each target signal after receiving the plurality of target signals to obtain a processing result of each target signal; and integrating the processing results of all the target signals into a feedback result, and sending the feedback result to feedback equipment through the external control circuit.

The electronic equipment provided by the embodiment of the disclosure comprises the external control circuit of the neuromorphic chip and the neuromorphic chip, so that the electrophysiological signal processing process can be integrated into the electronic equipment in a localized, low-delay and low-power-consumption manner, a complex intelligent computing task is realized based on a single chip, the characteristics of irregular neural network computing and graph computing are fully utilized on the basis of ensuring low power consumption, and the processing capacity of the embedded electronic equipment is greatly improved

In a possible implementation manner, the electronic device may be a User Equipment (UE), a mobile device, a User terminal, a cellular phone, a cordless phone, a Personal Digital Assistant (PDA), a handheld device, a computing device, an in-vehicle device, a wearable device, or the like.

It is understood that the above-mentioned method embodiments of the present disclosure can be combined with each other to form a combined embodiment without departing from the logic of the principle, which is limited by the space, and the detailed description of the present disclosure is omitted. Those skilled in the art will appreciate that in the above methods of the specific embodiments, the specific order of execution of the steps should be determined by their function and possibly their inherent logic.

In addition, the descriptions of the neuromorphic chip and the external control circuit of the neuromorphic chip in the electronic device provided by the present disclosure may refer to corresponding records in the computing system, and are not repeated.

The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or improvements to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A computer system based on a brain-computer interface is characterized by comprising a plurality of acquisition devices, an external control circuit of a neuromorphic chip, the neuromorphic chip and a feedback device; wherein the content of the first and second substances,

2. The computing system of claim 1, wherein the plurality of electrophysiological signals correspond to one or more signal classes.

3. The computing system of claim 2, wherein the signal classes comprise one or more of brain electrical signals, brain magnetic signals, and local field potentials.

4. The computing system of claim 1, wherein the plurality of electrophysiological signals correspond to one or more acquisition sites.

5. The computing system of claim 4, wherein the acquisition site comprises one or more of a brain, a heart, and muscles, wherein the brain comprises a plurality of brain regions, each brain region representing an acquisition site.

6. The computing system of any one of claims 1 to 5, wherein the external control circuitry is configured to convert the plurality of electrophysiological signals into a plurality of target signals that can be processed by the neuromorphic chip, including:

7. The computing system of claim 1, wherein the neuromorphic chip comprises an integration module and a plurality of execution modules, each execution module corresponding to a neural network algorithm, each execution module capable of processing a target signal corresponding to a signal category and/or a target signal corresponding to an acquisition site;

8. The computing system of claim 7, wherein the integration module is further configured to integrate the processing results with the same corresponding signal class into a first result, and integrate the first results corresponding to the respective signal classes into the feedback result.

9. The computing system according to claim 7 or 8, wherein the integration module communicates with any one of the execution modules through a handshake protocol, and the inside of the integration module and the inside of any one of the execution modules communicate through a network on chip.

10. An electronic device, comprising an external control circuit of a neuromorphic chip and a neuromorphic chip; wherein the content of the first and second substances,

the external control circuit is used for receiving a plurality of electrophysiological signals from the acquisition equipment, converting the electrophysiological signals into a plurality of target signals capable of being processed by the neuromorphic chip and sending the target signals to the neuromorphic chip;

the neuromorphic chip is used for processing each target signal after receiving the plurality of target signals to obtain a processing result of each target signal; and integrating the processing results of all the target signals into a feedback result, and sending the feedback result to feedback equipment through the external control circuit.