CN114783491A

CN114783491A - Memory controller, operating method thereof and memory system

Info

Publication number: CN114783491A
Application number: CN202210307690.XA
Authority: CN
Inventors: 钱宇力; 罗文�; 谢超凡
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-03-25
Filing date: 2022-03-25
Publication date: 2022-07-22

Abstract

The embodiment of the invention provides a memory controller, an operation method thereof and a memory system, wherein the operation method of the memory controller comprises the following steps: receiving a first instruction; the first instruction indicates to program memory cells coupled by an Nth word line in a plurality of storage surfaces in one memory chip; n is a positive integer; determining that the N is less than or equal to a first preset value and the first buffer does not meet a preset condition; the first buffer is used for backing up data to be programmed into the memory cells coupled with the Nth word line of each memory surface; a second instruction is sent out; and the second instruction indicates that the memory cells coupled with the Nth word line of each of the plurality of memory surfaces are programmed in sequence in a single-side programming mode.

Description

Memory controller, operating method thereof and memory system

Technical Field

The embodiment of the invention relates to the technical field of semiconductors, in particular to a memory controller, an operation method thereof and a memory system.

Background

The memory system may be classified into a single Plane (Plane) type and a multi-Plane type according to a structural configuration of a memory cell array of the memory system. The memory system of the single storage surface type includes a storage surface; the memory system of the multi-plane type includes a plurality of planes. For a Multi-Plane type memory system, a Multi-Plane programming (english expression is Multi-Plane Program) mode may be employed to Program two or more planes of the memory system at the same time to improve programming efficiency.

The multi-Plane Programming mode is inherently capable of improving the Programming efficiency, but inevitably has a problem of adjacent Plane disturbance (NPD), for example, in the case of the multi-Plane Programming mode, if one storage Plane has a program failure (PSF), the program failure often occurs on other storage planes that are programmed simultaneously. Therefore, it is desirable to provide an operating method that reduces the adverse effect of the adjacent interference while ensuring a certain programming efficiency.

Disclosure of Invention

In order to solve the related technical problems, embodiments of the present invention provide a memory controller, an operating method thereof, and a memory system.

In a first aspect, an embodiment of the present invention provides a memory controller;

the memory controller is configured to:

receiving a first instruction; the first instruction indicates to program memory cells coupled to an Nth word line in a plurality of storage surfaces in one memory chip; n is a positive integer;

determining that the N is less than or equal to a first preset value and the first buffer does not meet a preset condition; the first buffer is used for backing up data to be programmed into memory cells coupled with the Nth word line of each storage surface;

a second instruction is sent out; the second instruction indicates that the memory cells coupled to the nth word line of each of the plurality of memory planes are programmed sequentially in a Single-Plane programming (english expression).

In the above scheme, the memory controller is configured to:

determining that a programming exception exists in a storage unit on an Nth word line in a first storage surface of a plurality of storage surfaces which are subjected to single-side programming;

a third instruction is sent out; and the third instruction indicates that the data of the memory unit with the abnormal programming in the first storage surface is recovered in a storage surface level Redundant Array of Independent Disks (RAID) mode.

In the above scheme, the memory controller is configured to:

determining that N is greater than a first preset value; and/or the first buffer meets a preset condition;

a fourth instruction is sent out; the fourth instruction indicates that the memory cells coupled by the Nth word line of each of the plurality of storage surfaces are programmed in a multi-surface programming mode.

In the above scheme, the memory controller is configured to:

determining that the N is less than or equal to a first preset value, and the first buffer meets a preset condition;

a fifth instruction is sent; the fifth instruction indicates that data in memory cells coupled to an Nth word line to be programmed to each memory surface are backed up to the first buffer;

a sixth instruction is sent; the sixth instruction indicates that the memory cells coupled to the Nth word line of each of the plurality of storage planes are programmed in a multi-plane programming manner.

In the above scheme, the memory controller is configured to:

determining that a programming exception exists in a memory cell coupled to the Nth word line in at least a first memory plane in the plurality of memory planes;

and issuing a seventh instruction, wherein the seventh instruction indicates that the data with the abnormal programming is recovered by using the data in the first buffer.

In the above scheme, the memory controller is configured to:

determining that the data of the memory cells coupled with the N-1 th word line in the first storage surface has an exception;

an eighth instruction is sent out; and the eighth instruction indicates that the data of the storage unit coupled with the (N-1) th word line in the first storage plane is recovered in a storage plane level Redundant Array of Independent Disks (RAID) mode.

In the above solution, the first buffer is disposed in the host or in the memory controller.

In the foregoing solution, the first buffer is disposed in the host, and the determining that the first buffer does not satisfy the preset condition includes:

and acquiring the capacity information of the first buffer, and determining that the first buffer does not meet the preset condition according to the capacity information.

In a second aspect, an embodiment of the present invention provides a memory system, including: a memory controller as claimed in any one of the above aspects and a plurality of memory chips coupled to the memory controller; wherein the content of the first and second substances,

each of the memory chips includes a plurality of memory planes, each of the memory planes including a plurality of word lines respectively coupled to a plurality of memory cells.

In the above scheme, the memory chip includes a three-dimensional NAND-type memory.

In the above scheme, the number of storage bits of each of the plurality of memory cells includes one or more bits.

In the above scheme, the number of storage bits of each of the plurality of storage units includes three bits.

In a third aspect, an embodiment of the present invention provides an operating method of a memory controller, where the method includes:

receiving a first instruction; the first instruction indicates to program memory cells coupled by an Nth word line in a plurality of storage surfaces in one memory chip; n is a positive integer;

determining that the N is less than or equal to a first preset value and the first buffer does not meet a preset condition; the first buffer is used for backing up data to be programmed into the memory cells coupled with the Nth word line of each memory surface;

a second instruction is sent out; and the second instruction indicates that the memory cells coupled with the Nth word line of each of the plurality of memory surfaces are programmed in sequence in a single-side programming mode.

In the above scheme, the method further comprises:

In the foregoing solution, the method further includes:

a fifth instruction is sent out; the fifth instruction indicates that data in memory cells coupled to an Nth word line to be programmed to each memory surface are backed up to the first buffer;

In the above scheme, the method further comprises:

determining that a programming exception exists in a memory cell coupled to an Nth word line in at least a first memory plane in the plurality of memory planes;

and issuing a seventh instruction, wherein the seventh instruction indicates that the data with the programming exception is recovered by using the data in the first buffer.

In the above scheme, the method further comprises:

In the foregoing solution, the first buffer is disposed in a host, and the determining that the first buffer does not satisfy the preset condition includes:

In the foregoing solution, the determining that the first buffer meets the preset condition includes:

and determining that the first buffer exists, wherein the storage space of the first buffer is greater than or equal to a second preset value.

In the above scheme, the method further comprises:

and acquiring the first preset value before receiving the first instruction.

The embodiment of the invention provides a memory controller, an operation method thereof and a memory system, wherein the memory controller is configured to: receiving a first instruction; the first instruction indicates to program memory cells coupled to an Nth word line in a plurality of storage surfaces in one memory chip; n is a positive integer; determining that the N is less than or equal to a first preset value and the first buffer does not meet a preset condition; the first buffer is used for backing up data to be programmed into memory cells coupled with the Nth word line of each storage surface; a second instruction is sent out; and the second instruction indicates that the memory cells coupled with the Nth word line of each of the plurality of memory planes are sequentially programmed in a single-side programming mode. In the embodiment of the invention, under the condition that N is determined to be less than or equal to the first preset value and the first buffer does not meet the preset condition, the memory cells coupled with the Nth word line of each memory surface in the plurality of memory surfaces are sequentially programmed in a single-surface programming mode, so that interference on data of adjacent memory surfaces when the programming of a single memory surface is abnormal can be avoided, and the effective recovery of abnormal data of a memory system is facilitated.

Drawings

FIG. 1 is a circuit diagram of a memory cell string of a memory system according to one embodiment of the invention;

FIG. 2 is a schematic diagram illustrating location partitioning of a memory system in the presence of data anomalies according to an embodiment of the present invention;

FIG. 3 is a block diagram of a method of operating a memory controller according to the present invention;

FIG. 4 is a flowchart illustrating a method for operating a memory controller according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of an exemplary system having a memory system in accordance with an embodiment of the present invention;

FIG. 6a is a schematic diagram of an exemplary memory card having a memory system in accordance with one embodiment of the present invention;

FIG. 6b is a schematic diagram of an exemplary Solid State Drive (SSD) with a memory system in accordance with an embodiment of the present invention;

FIG. 7 is a schematic diagram of an exemplary memory chip including an array of memory cells and peripheral circuitry, in accordance with an embodiment of the present invention;

FIG. 8 is a diagram of an exemplary memory controller according to an embodiment of the present invention.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention; that is, not all features of an actual embodiment are described herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. And the discussion of a second element, component, region, layer or section does not necessarily indicate that the invention does not necessarily involve the first element, component, region, layer or section.

Spatial relational terms such as "under … …," "under … …," "below," "under … …," "over … …," "above," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

So that the manner in which the features and aspects of the embodiments of the present invention can be understood in detail, a more particular description of the embodiments of the invention, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings.

The memory chip in the embodiment of the present invention includes, but is not limited to, a three-dimensional NAND-type memory, and for convenience of understanding, the three-dimensional NAND-type memory is taken as an example for description.

The three-dimensional NAND-type memory in the memory system has a variety of defects, some of which can be detected at the time of factory shipment, and some of which are exposed after the factory shipment as the usage environment changes. In practice, some memory cell arrays of three-dimensional NAND type memories may have structural weak points which may take a long time or require a large number of programming operations and erasing operations before developing and becoming defective. For example, memory cell arrays of three-dimensional NAND-type memories are subjected to high stress during program and erase cycles, and weak structures in some memory cell arrays of three-dimensional NAND-type memories can develop into defects after cycling.

When the three-dimensional NAND type memory is defective, a phenomenon of data loss may occur. If the defect is a Word Line (WL) short circuit, data in the memory cell corresponding to the entire WL may be damaged. Since each WL may correspond to a memory cell of a plurality of character strings, based on this, a phenomenon of a large amount of data loss may occur, thereby causing a malfunction to the memory system. This type of failure is generally defined as a reliability failure of the three-dimensional NAND-type memory, which may further cause failure of the memory system in the field.

As miniaturization of memory systems progresses, the density of memory chips in the memory systems increases, thereby promoting an increase in the number of memory planes included in each memory chip. As the number of memory planes under the same memory chip increases, there is a situation where resources are shared among multiple memory planes, for example, multiple memory planes share a row driver. Therefore, when a defect (for example, a word line short circuit) occurs in the three-dimensional NAND memory during the programming operation, a current leakage problem occurs, which results in that all data stored in the memory cells on the word line related to the current leakage in the memory plane are lost, and meanwhile, the data stored in the memory plane sharing the resources are also interfered, that is, adjacent plane interference occurs.

In order to more clearly describe the technical solution of the present invention, the following description is made of the components of the memory system.

The memory system includes a plurality of memory chips; each memory chip includes a plurality of memory planes, each memory plane including a plurality of word lines respectively coupled to a plurality of memory cells. In practical applications, the number of storage bits of each of the plurality of memory cells may include one or more bits.

When the number of memory bits per memory Cell includes one bit, the memory Cell may be a Single-Level Cell (SLC). Here, each memory cell can store one bit of data, i.e., only two memory states of 0 and 1. At this time, one physical page of the memory chip corresponds to one logical memory page.

When the number of storage bits of each memory Cell includes two bits, the memory Cell may be a two-Level Cell (MLC). Here, each memory cell can store two bits of data, and the memory states thereof are four kinds, 00, 01, 10, and 11. At this time, one physical Page of the memory chip corresponds to two logical memory pages, which can be divided into an Upper Page (english expression: Upper Page) and a Lower Page (english expression: Lower Page).

When the number of memory bits per memory Cell includes three bits, the memory Cell may be a Triple-Level Cell (TLC). Here, each memory cell can store three bits of data, and the storage states thereof are eight kinds, 000, 001, 010, 100, 011, 110, 101, and 111. At this time, one physical Page of the memory chip corresponds to three logical memory pages, and the three logical memory pages can be divided into an upper Page, a Middle Page (expressed as Middle Page), and a lower Page.

When the number of storage bits of each memory Cell includes four bits, the memory Cell may be a Quad-Level Cell (QLC). Here, each memory cell can store four bits of data, and the storage states thereof are sixteen kinds, 0000, 0001, 0010, 0100, 1000, 1100, 1010, 1001, 0011, 0101, 0110, 1101, 1110, 1011, 0111, and 1111. At this time, one physical Page of the memory chip corresponds to four logical memory pages, i.e., an upper Page, a middle Page, a Second lower Page (expressed as Second lower Page), and a lower Page.

Illustratively, as shown in tables 1 to 4, the memory system includes a plurality of memory chips, each of which includes 4 memory planes, i.e., memory plane 0, memory plane 1, memory plane 2, and memory plane 3; each memory plane includes a plurality of word lines, word line 1, word line 2; each word line is coupled with a plurality of memory units, and the memory units are divided into a plurality of storage groups (String); each word line corresponds to a plurality of storage groups, i.e., storage group 0, storage group 1, storage group 2, storage group 3, storage group 4, and storage group 5.

Three damaged data distributions shown in tables 1 to 3 are listed according to practical situations, and the memory chip is a TLC type memory chip.

Table 1 shows a case where the reach range is the smallest (case one), and in one multi-surface programming from the bank 0 to the bank 3 is performed for the upper, middle, and lower pages of the memory cells in the bank 2 in the 2 nd word line (WL2), a program state failure occurs in the upper, middle, and lower pages of the memory cells in the bank 2 in the 2 nd word line (WL2) in the bank 0. In this case, the memory cells in the memory groups 0 to 5 in the 1 st word line (WL1) in the memory plane 0, the memory cells in the memory groups 0 to 2 in the 2 nd word line (WL2) in the memory plane 0, and the memory cells in the memory group 2 in the 2 nd word line (WL2) in the memory plane 1 are damaged. Since one bank in TLC includes 3 bits (upper page, middle page, lower page) and each WL of the bank includes six banks, the number of damaged pages is (6+3+1) bank 3 pages/bank 30 pages.

TABLE 1

Table 2 shows a case where the spread is medium (case two), and in performing one-time multi-surface programming from plane 0 to plane 3 for the upper, middle, and lower pages of the memory cells in the memory group 2 in the 2 nd word line (WL2), a program state failure occurs in the upper, middle, and lower pages of the memory cells in the memory group 2 in the 2 nd word line (WL2) in plane 0. In this case, the data of the memory cells in the memory groups 0 to 5 in the 1 st word line (WL1) in the memory plane 0, the memory cells in the memory groups 0 to 2 in the 2 nd word line (WL2) in the memory plane 0, and the memory cells in the memory group 2 in the 2 nd word line (WL2) in the memory plane 1 to 3 are damaged. In the case of TLC, the number of damaged pages is (6+3+1+ 1) storage group x 3 pages/storage group 36 pages.

TABLE 2

Table 3 shows a case where the spread is the largest (case three), and in performing one-time multi-surface programming from plane 0 to plane 3 for the upper page, middle page, and lower page of the memory cells in the memory group 2 in the 2 nd word line (WL2), a program state failure occurs in the upper page, middle page, and lower page of the memory cells in the memory group 2 in the 2 nd word line (WL2) in plane 0. In this case, the data of the memory cells in the memory groups 0 to 5 in the 1 st word line (WL1) in the memory plane 0, the memory cells in the memory groups 0 to 2 in the 2 nd word line (WL2) in the memory plane 0, and the memory cells in the memory groups 0 to 2 in the 2 nd word line (WL2) in the memory plane 1 to 3 are damaged. In the case of TLC, the number of damaged pages is (6+3+3+ 3) stock set 3 pages/stock set 54 pages.

TABLE 3

From the above analysis of three cases, in the memory chip architecture where one memory chip includes 4 memory planes, each memory plane includes 6 memory groups, and each memory group includes 3 pages, when the adjacent plane effect is generated in one multi-plane programming, the upper, middle and lower pages of memory cells in memory group 2 in the 2 nd word line (WL2) in memory plane 0 fail in programming state when multi-sided programming, the maximum number of pages which can be destroyed on one memory chip is the case shown in table 3 above, and when multi-surface programming occurs, program state failure occurs in the upper, middle and lower pages of memory cells in the memory group 5 in the 2 nd word line (WL2) in the memory plane 0, as shown in table 4, the largest number of pages on a memory chip that can be destroyed is (6+6+6+ 6) memory bank 3 pages/memory bank 90 pages.

TABLE 4

Data errors may be caused by problems with operation timing and circuit stability in a programming operation of the memory system, or by the slow passage of charge among memory cells stored in a memory chip in the memory system over time.

When a small amount of data failure occurs in the memory system or data errors occur in a specific mode, the small amount of failed data can be corrected and recovered in an ECC (error correction code) checking mode. ECC is an error detection and correction algorithm that may be used in a memory system. At present, a relatively common mode for data recovery in a three-dimensional NAND memory is a Low Density Parity Check code (LDPC), which is also a mode of ECC coding Check in a broad sense, the LDPC can correct more than one bit of error, the error correction strength of the LDPC is approximately 200 bits/4 kilobytes, and if one memory page is approximately 16 kilobytes, the LDPC can correct approximately one kilobyte of error on one memory page. However, when the number of erroneous bits in one memory page exceeds the LDPC error correction range, the erroneous data cannot be recovered by the LDPC method.

Under the condition that the programming state fails, when the ECC encoding check mode cannot correct and recover the invalid data, the recovery of the damaged data in the memory system conventionally includes two methods, namely, Read Retry (english expression) and Redundant Array of Independent Disks (RAID). The nature of re-reading is an error correction mechanism that attempts to read data correctly by attempting to find the closest threshold voltage in a way that deviates from the normal threshold voltage when the data has a read error that is uncorrectable by ECC. The independent redundant disk array is a hard disk group (logical hard disk) formed by combining a plurality of independent hard disks (physical hard disks) in different modes, thereby providing higher storage performance than that of a single hard disk and providing a data backup technology, the data backup function is that once user data is damaged, the damaged data can be recovered by using backup information, thereby ensuring the safety of the user data, the formed disk group looks like a hard disk by a user, the user can partition, format and the like, the operation of the disk array is the same as that of the single hard disk, except that the storage speed of the disk array is much higher than that of the single hard disk, and automatic data backup can be provided.

For data corruption caused by the adjacent surface interference problem shown in tables 1 to 4, rereading is completely invalid, the Redundant Array of Independent Disks (RAID) mode includes a storage surface level RAID and a chip level RAID, the chip level RAID can recover corrupted data caused by the adjacent surface interference problem, but the configuration cost of the memory system is high; the RAID with the storage plane level having a lower configuration cost can only recover a failure in one storage plane, and if a plurality of storage planes fail to be programmed, the RAID with the storage plane level cannot recover data. Therefore, the existence of the adjacent interference problem causes the problem that the damaged data cannot be completely recovered, and the data is lost.

In view of the above problems, the embodiments of the present invention adopt the following technical solutions to solve.

The embodiment of the invention provides a memory controller, which is coupled with a plurality of memory chips, wherein each memory chip comprises a plurality of memory planes, and each memory plane comprises a plurality of word lines respectively coupled to a plurality of memory units; the memory controller is configured to:

a second instruction is sent out; and the second instruction indicates that the memory cells coupled with the Nth word line of each of the plurality of memory planes are sequentially programmed in a single-side programming mode.

Here, the number of memory planes, word lines, and memory groups in one memory chip is not limited to those shown in tables 1 to 4, and the number of memory planes, word lines, and memory groups in tables 1 to 4 is merely an exemplary example. In practical applications, the number of word lines in each storage plane includes, but is not limited to, 32, 64, 128, etc.

Fig. 1 shows a circuit diagram of a memory cell string of a three-dimensional NAND-type memory, the memory cell string including a plurality of memory cells, each memory cell string having a topmost memory cell connected to a top select pipe, the top select pipe connected to a bit line, and a memory cell string having a bottommost memory cell connected to a bottom select pipe.

For the programming process of the three-dimensional NAND type memory, the general programming Sequence is to start programming from the memory cell nearest to the bottom select tube and end from bottom to top to the memory cell nearest to the top select tube, i.e., the memory cells adjacent to the bottom select tube are programmed sequentially to the memory cells adjacent to the top select tube, and this programming Sequence can be referred to as a typical programming Sequence (expressed in english as Normal Program Sequence) or a forward programming Sequence. The reverse programming sequence is that the memory cells closest to the top selection tube are programmed from top to bottom to the memory cells closest to the bottom selection tube, namely the memory cells adjacent to the top selection tube are programmed to the memory cells adjacent to the bottom selection tube in sequence.

In practical applications, the neighbor effect generally occurs at the first few WLs when programming the memory cell. The first few WLs are herein understood to be the ones closest to the bottom select transistor when the programming sequence is forward programming, and the first few WLs are herein understood to be the ones closest to the top select transistor when the programming sequence is reverse programming. It will be appreciated that the problem of program anomalies is more likely to be caused by process defects in the first few WLs to be programmed (i.e., the few WLs nearest the bottom select transistor or the few WLs nearest the top select transistor).

Here, the first preset value is generally set to 5, but the first preset value is not limited thereto, and may be set according to specific situations in practical applications.

In some embodiments, the first buffer is disposed in a host or in the memory controller.

Here, when the first Buffer is provided in the Host, it may specifically be a Host Memory cache (HMB). The HMB is used for backing up cache because the HMB is relatively fast and can reduce performance loss to the maximum extent.

When the first buffer is disposed in the memory controller, the first memory may be a block area specifically disposed in the memory controller for buffering data, or a part of DRAM of the memory controller may be used as the first buffer. As shown in fig. 8, when the first buffer is disposed in the Memory controller, the first buffer may be a part of a Random Access Memory (RAM) 802, but is not limited thereto.

In some embodiments, a first buffer is provided in the host, and the determining that the first buffer does not satisfy a preset condition comprises:

In some specific examples, the obtaining of the capacity information of the first buffer may specifically be: after the memory controller determines that the N is less than or equal to the first preset value and the first buffer does not meet the preset condition, the memory controller may first send an instruction to the host to acquire the capacity information of the first buffer in the host, the host sends the capacity information of the first buffer to the controller after receiving the instruction, and the memory controller receives the capacity information of the first buffer sent by the host.

In some specific examples, the size information of the first buffer may also be included in the first instruction.

In some embodiments, the determining that the first buffer satisfies the preset condition includes:

Here, taking the first buffer as an example to be specifically explained as HMB, assuming that when the programmed memory chips are of the TLC type, that is, the number of pages stored in each memory unit includes three pages, as in the case shown in the foregoing table 4, the maximum number of pages destroyed in the memory unit coupled to the nth word line in one memory chip is 6 banks/planes 3 pages/banks 4/planes/memory chips 72 pages/memory chips, and typically one page has a size of 16KB, so that the backup space requirement of one memory chip is 72 pages/memory chips 16 KB/page 1152 KB/memory chip, and since only 16MB to 32MB of HMB is usually provided in the host for data backup, the number of memory chips capable of being backed up at the same time in the host is 16MB to 32MB/1152 KB/memory chips 14 to 28 memory chips, that is, when the host supports HMB, it can support the backup of the program data of 14 to 28 memory chips at the same time, considering that the programming can be performed in parallel at the memory chip level. That is, the storage space of the HMB is limited, and backup of the program data of a certain number (e.g. 14 to 28) of memory chips can be realized.

It can be understood that, when the HMB exists in the host and the storage space of the HMB is greater than or equal to the storage space that needs to be backed up, that is, the first buffer meets the preset condition. And when the HMB does not exist in the host computer or the storage space of the HMB is smaller than the storage space needing to be backed up, the first buffer does not meet the preset condition.

In some embodiments, the first preset value is obtained prior to receiving the first instruction.

In practical applications, the obtaining of the first preset value may be obtained from a register of the memory system, the first preset value needs to be set in the register in advance in the manner of obtaining the first preset value, the first preset value can also be obtained from an instruction of the host, and the first preset value obtained in the manner of obtaining the first preset value is dynamically changed and can be changed at any time according to requirements of users.

In the embodiment of the invention, when N is less than or equal to a first preset value, that is, when the memory cells coupled to the nth word line, which are easy to have programming abnormality, are programmed and the first buffer does not meet a preset condition, the memory cells coupled to the nth word line of each of the plurality of memory planes are sequentially programmed in a single-sided programming manner, so that when a certain memory plane has programming abnormality, data of other memory planes are not interfered. Therefore, when data is recovered, only the data of one storage surface with programming abnormality needs to be recovered, that is, only the data of a single storage surface needs to be recovered, although single-side programming is time-consuming, only the storage unit which is easy to have programming abnormality needs to be subjected to single-side programming, the number of the storage units is relatively small, and therefore relatively high programming efficiency can be achieved under the condition of reducing the influence of adjacent surface interference.

In some embodiments, the memory controller is configured to:

determining that a programming exception exists in a storage unit on an Nth word line in a first storage surface in a plurality of storage surfaces which are programmed in a single surface;

It can be understood that, in the embodiment of the present invention, when N is less than or equal to a first preset value, that is, when the memory cells coupled to the nth word line that are prone to programming abnormality are programmed, and the first buffer does not meet a preset condition, the memory cells coupled to the nth word line of each of the multiple storage planes are sequentially programmed in a single-sided programming manner, so that when abnormal data only exists in a single storage plane, data of one storage plane can be recovered in a storage plane level independent redundant disk array manner, and thus, the abnormal data in the foregoing situation can be completely recovered in a storage plane level independent redundant disk array manner.

In practical application, except for the condition that the N is less than or equal to the first preset value and the first buffer does not meet the preset condition, the method also comprises the step that the N is greater than the first preset value; and/or the first buffer meets the preset condition.

Based on the technical scheme, the embodiment of the invention also provides the following technical scheme.

In some embodiments, the memory controller is configured to:

Here, determining that N is greater than a first preset value; and/or the first buffer meets preset conditions, including the following conditions:

firstly, N is larger than a first preset value, and the first buffer meets a preset condition;

secondly, N is larger than a first preset value, and the first buffer does not meet preset conditions;

and thirdly, N is less than or equal to a first preset value, and the first buffer meets preset conditions.

It can be understood that, for the case one and the case two, that is, when N is greater than the first preset value, the probability of occurrence of a program abnormality is very low when the memory cells coupled to the nth word line are subjected to a program operation, or the program abnormality is substantially not occurred, in this case, when the memory cells coupled to the nth word line are directly subjected to a program operation in a multi-plane programming manner, the adjacent plane effect is substantially not occurred, that is, data of the memory cells coupled to the nth word line in the plurality of memory planes are not disturbed, so that the program efficiency can be improved under the condition of ensuring that the data program is normal.

For the third situation, N is less than or equal to the first preset value, and when the first buffer meets the preset condition, that is, when the memory cell coupled to the nth word line, which is prone to programming abnormality, is programmed, and when the first buffer meets the preset condition, the memory cell coupled to the nth word line is programmed in a multi-surface programming manner, so as to cause interference to data of the memory surface adjacent to the memory surface with programming abnormality, and when data errors occur to multiple memory surfaces under the same memory chip at the same time, the method of using the independent redundant disk array at the memory surface level cannot recover abnormal data, and therefore, the embodiment of the present invention provides the following technical solutions.

In some embodiments, the memory controller is configured to:

In practical application, a second buffer can also exist in the memory chip; the second Buffer may be a Page Buffer (PB).

When the first instruction is responded, the N is determined to be smaller than or equal to a first preset value, and the first buffer meets a preset condition, backing up data to be programmed into a storage unit coupled with an Nth word line of each storage surface to the first buffer; the method comprises the following steps:

and responding to the first instruction, determining that the N is less than or equal to a first preset value, and when the first buffer meets a preset condition, storing data to be programmed into each storage unit coupled with the Nth word line in the second buffer, and backing up the data of the second buffer to the first buffer.

In some embodiments, the memory controller is configured to:

Here, it can be understood that, since N is less than or equal to a first preset value and the first buffer satisfies a preset condition, the first storage plane is programmed in a multi-plane programming manner, and when a programming abnormality occurs in the first storage plane, a storage plane adjacent to the first storage plane on the nth word line is also interfered.

It can be understood that when N is less than or equal to a first preset value and the first buffer meets a preset condition, data in the memory cells coupled to the nth word line to be programmed to each storage plane are backed up to the first buffer, so that when the memory cells coupled to the nth word line in the first storage plane have programming abnormality, the data backed up to the first buffer can be used to perform programming operation again, so that the data cannot be recovered, and recovery of the data of the memory cells coupled to the nth word line in at least the first storage plane is realized.

In practical applications, when a programming abnormality exists in a memory cell on an nth word line in a first storage plane, data of a memory cell on an nth word line, that is, an N-1 th word line, in the first storage plane, may also be disturbed.

In some embodiments, the memory controller is configured to:

determining that the data of the memory cells coupled with the (N-1) th word line in the first storage surface has an exception;

an eighth instruction is sent out; and the eighth instruction indicates that the data of the storage unit coupled with the (N-1) th word line in the first storage surface is recovered in a storage surface level Redundant Array of Independent Disks (RAID) mode.

It can be understood that, in a plurality of storage planes, only the storage units coupled to the (N-1) th word line in the first storage plane are disturbed, so that data recovery can be realized by adopting a storage plane level redundant array of independent disks for the data of the storage units of the (N-1) th word line.

In the embodiment of the present invention, as shown in fig. 2, the locations of the damaged storage groups are divided into three types: the first is the word line and the adjacent storage surface corresponding to the storage group with the current programming exception, and is called as a position one; the second type is WL and storage surface corresponding to the storage group with abnormal programming of the current storage group with abnormal programming, and is called as a position two; the third is the memory plane and adjacent WL where the memory bank currently programming the exception is located, referred to as location three.

And when the N is less than or equal to a first preset value and the first buffer does not meet the preset condition, sequentially programming the memory cells coupled with the Nth word line of each memory plane in the plurality of memory planes in a single-side programming mode, so that when the programming of the second position is abnormal, the data in the first position can be prevented from being damaged, and the damaged data in the second position and the third position are recovered in a memory plane level independent redundant disk array mode.

When N is less than or equal to a first preset value and a first buffer meets a preset condition, data in a storage unit coupled with an Nth word line to be programmed to each storage surface is backed up to the first buffer in advance, then the storage unit coupled with the Nth word line of each storage surface in the plurality of storage surfaces is programmed in a multi-surface programming mode, when a second position is abnormal in programming, the data in the first buffer is used for recovering the data in the first position and the second position, and then the data recovery in the third position is realized in a storage surface level independent redundant disk array mode.

When N is greater than the first preset value, since the possibility of data abnormality is low or it can be considered that no abnormality occurs, the memory cells coupled to the nth word line of each memory plane in the memory planes are programmed directly in a multi-plane programming manner, and data does not need to be recovered after programming is finished.

The following further understands with reference to fig. 3 that, first, the first preset value Q is obtained, a first instruction for performing a programming operation on a memory cell coupled to an nth word line is received, when the requirement that the host supports sufficient HMB and HMB memory space and N is less than or equal to the first preset value Q is met, data to be programmed in the memory cell coupled to the nth word line of each storage plane is backed up to the HMB, the memory cell coupled to the nth word line of each storage plane in the multiple storage planes is programmed in a multi-plane programming manner, and when a programming abnormality occurs, the data stored in the HMB is read, and the data of the memory cell coupled to the nth word line is recovered; when N is larger than a first preset value Q, directly programming the memory cells coupled with the Nth word line of each memory plane in the plurality of memory planes in a multi-plane programming mode; and when the host does not support the HMB or the HMB storage space is not enough and N is less than or equal to a first preset value Q, programming the memory cells coupled with the Nth word line of each of the plurality of storage surfaces in a single-side programming mode.

In the embodiment of the invention, when the system does not support the HMB or the storage space of the HMB is insufficient, and when the memory cells coupled to the first few word lines are programmed, the memory cells coupled to the first few word lines are programmed by adopting a single-sided programming mode instead of a multi-sided programming mode, so that the situation that the data on the first position is damaged can be avoided. At this time, the second position and the third position are both only on the same storage plane, and the recovery can be realized by adopting the mode of the independent redundant disk array at the storage plane level. The cost of this alternative is that single-sided programming is theoretically 3 to 4 times worse than multi-sided programming, so there is performance jitter for the first few WL programming. But since there are few, typically 2 to 3, WLs to begin with, the performance jitter is within an acceptable range for architectures such as memory chips with 128-level WLs, which are around 2%.

On the premise that the adjacent surface effect only occurs in the first few WLs and the possibility that the adjacent surface effect occurs in other WLs is very small, the embodiment of the invention comprehensively utilizes three schemes of HMB backup data, a storage surface level independent redundant disk array and optional single-side programming instead of multi-side programming to solve the problem of adjacent surface interference existing in a memory system. On the first hand, the data damage caused by the adjacent surface interference can be completely recovered, and the bad user experience caused by the data loss caused by the adjacent surface interference is effectively avoided; in the second aspect, compared with a scheme for recovering the redundant array of independent disks at the level of a storage chip, the embodiment of the invention can solve the problem of adjacent surface interference at one time, does not increase the cost additionally and uses less recovery time; in the third aspect, from the aspect of influence of performance, performance loss can be stopped as much as possible, so that various performance requirements are met; in the fourth aspect, the comprehensive scheme is relatively flexible, and can be compatible with a host platform which supports or does not support HMB; in a fifth aspect, the memory system related to the implementation of the solution provided by the embodiment of the present invention has a smaller firmware modification, and is relatively easy to implement and also beneficial to the later maintenance.

An embodiment of the present invention provides a memory controller, where the memory controller is configured to: receiving a first instruction; the first instruction indicates to program memory cells coupled by an Nth word line in a plurality of storage surfaces in one memory chip; n is a positive integer; determining that the N is less than or equal to a first preset value and the first buffer does not meet a preset condition; the first buffer is used for backing up data to be programmed into memory cells coupled with the Nth word line of each storage surface; a second instruction is sent out; and the second instruction indicates that the memory cells coupled with the Nth word line of each of the plurality of memory planes are sequentially programmed in a single-side programming mode. In the embodiment of the invention, under the condition that N is determined to be less than or equal to the first preset value and the first buffer does not meet the preset condition, the memory cells coupled with the Nth word line of each memory surface in the plurality of memory surfaces are sequentially programmed in a single-surface programming mode, so that interference on data of adjacent memory surfaces when the programming of a single memory surface is abnormal can be avoided, and the effective recovery of abnormal data of a memory system is facilitated.

Based on the foregoing memory controller, an embodiment of the present invention further provides an operating method of a memory controller, as shown in fig. 4, the method includes:

step 401: receiving a first instruction; the first instruction indicates to program memory cells coupled to an Nth word line in a plurality of storage surfaces in one memory chip; n is a positive integer;

step 402: responding to the first instruction, and determining that the N is less than or equal to a first preset value and a first buffer does not meet a preset condition; the first buffer is used for backing up data to be programmed into memory cells coupled with the Nth word line of each storage surface

Step 403: a second instruction is sent out; and the second instruction indicates that the memory cells coupled with the Nth word line of each of the plurality of memory planes are sequentially programmed in a single-side programming mode.

In practical applications, the first command may be issued by the host, and then transmitted to the memory controller through the data transmission interface between the host and the memory controller. The responding to the first instruction may be that after the memory controller receives the first instruction, the memory controller responds to the first instruction to control a peripheral circuit in the memory chip to sequentially program the memory cells coupled to the nth word line of each of the multiple memory planes in a single-sided programming manner. The above description may be referred to both for receiving the first instruction and for an execution subject responding to the first instruction as described in the following embodiments.

In some embodiments, the method further comprises:

a third instruction is sent; and the third instruction indicates that the data of the memory unit with the abnormal programming in the first storage surface is recovered in a storage surface level Redundant Array of Independent Disks (RAID) mode.

In some embodiments, the method further comprises:

a fourth instruction is sent out; the fourth instruction indicates that the memory cells coupled by the Nth word line of each of the plurality of storage surfaces are programmed in a multi-surface programming manner.

In some embodiments, the method further comprises:

a sixth instruction is sent; the sixth instruction indicates that the memory cells coupled to the Nth word line of each of the plurality of storage surfaces are programmed in a multi-surface programming manner.

In some embodiments, the method further comprises:

In some embodiments, the memory controller is configured to:

the first buffer is arranged in the host, and the determining that the first buffer does not satisfy the preset condition comprises:

In some embodiments, the method further comprises:

and acquiring the first preset value before receiving the first instruction.

Based on the above memory controller, an embodiment of the present invention further provides a memory system, where the memory system includes: a memory controller as in any one of the above embodiments and a plurality of memory chips coupled to the memory controller; wherein the content of the first and second substances,

In some embodiments, the memory chip comprises a three-dimensional NAND-type memory.

In some embodiments, the number of storage bits of each of the plurality of memory cells comprises one or more bits.

In some embodiments, the number of storage bits of each of the plurality of storage cells comprises three bits.

In practical applications, the memory system according to the embodiment of the present invention includes, but is not limited to, a Solid State Drive (SSD).

The memory system is further described below with reference to the accompanying drawings.

As shown in fig. 5, system 500 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, Virtual Reality (VR) device, Augmented Reality (AR) device, or any other suitable electronic device having storage therein, system 500 may include a host 504 and a memory system 501, memory system 501 having one or more memory chips 502 and a memory controller 503. The host 504 may be a processor (e.g., a Central Processing Unit (CPU)) or a system on a chip (SoC) (e.g., an Application Processor (AP)) of an electronic device. The host 504 may be configured to send data to the memory chip 502 or receive data from the memory chip 502.

The memory controller 503 and the one or more memory chips 502 may be integrated into various types of memory devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 501 may be implemented and packaged into different types of end electronics. In one example as shown in FIG. 6a, the memory controller 503 and the single memory chip 502 may be integrated into a memory card 601. The memory card 601 may include a PC card (PCMCIA), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, and the like. The memory card 601 may also include a memory card connector 602 that couples the memory card 601 to a host. In another example as shown in fig. 6b, the memory controller 503 and the plurality of memory chips 502 may be integrated into the SSD 603. SSD603 may also include SSD connector 604 that couples SSD603 with a host.

In practice, the memory chip 502 may include a memory cell array 709 and peripheral circuits coupled to the memory cell array 706. The peripheral circuits may include any suitable analog, digital, and mixed-signal circuits, some exemplary peripheral circuits being shown in fig. 7 including page buffers/sense amplifiers 701, column decoders/bit line drivers 702, row decoders/word line drivers 703, voltage generators 704, control logic 705, registers 706, interfaces 707, and data buses 708. It should be understood that in some examples, additional peripheral circuitry not shown in fig. 7 may also be included.

The memory controller 503 has a storage unit (for example, a RAM802 described later) inside the memory controller 503, and receives an instruction from the host 504 to control the memory chip 502. The control of the memory chip 502 includes control unrelated to the instruction received from the host 504 and control based on the instruction received from the host 504. For example, the memory controller 503 writes data instructed to be written by the host 504 to the memory chip 502. In addition, the memory controller 503 reads out data instructed to be read out by the host 504 from the memory chip 502 and transmits the data to the host 504.

Fig. 8 illustrates some exemplary memory controllers 503. the memory controllers 503 may include a host interface 801, a random access memory 802, a read only memory 803, a memory interface 804, an ECC circuit 805, and an overall control 806. The memory controller 503 includes, for example, a processor such as a Central Processing Unit (CPU) as hardware, and executes firmware (program) stored in the ROM803 and loaded on the RAM802 by the processor to execute a part or all of the functions of each of the host interface 801, the memory interface 804, the ECC circuit 805, and the overall control Unit 806. The host interface 801, the RAM802, the ROM803, the memory interface 804, the ECC circuit 805, and the overall control unit 806 are connected to each other by a bus.

The RAM802 is, for example, a volatile memory. The RAM802 is an example of a storage unit provided inside the memory controller 503. The RAM802 temporarily holds data and has a function as a buffer. The data held in the RAM802 includes data received from the host 504, data to be transmitted to the host 504, data to be written into the memory chip 502 (write data), data read from the memory chip 502 (read data), various kinds of management data indicating the state of the memory chip 502 and referred to by the overall control unit 806 for control of the memory chip 502, and firmware. The management data includes an address conversion table, a job management table T1, and an adjustment value management table T2.

Based on the above operation method of the memory controller, an embodiment of the present invention further provides an operation method of a memory system, where the memory system includes a plurality of memory chips and a memory controller coupled to the plurality of memory chips, and the operation method of the memory system adopts the operation method of the memory controller described in any one of the above embodiments.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present invention, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention. The above-mentioned serial numbers of the embodiments of the present invention are only for description, and do not represent the advantages and disadvantages of the embodiments.

The methods disclosed in the several method embodiments provided by the present invention can be combined arbitrarily without conflict to obtain a new method embodiment.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A memory controller, wherein the memory controller is configured to:

2. The memory controller of claim 1, wherein the memory controller is configured to:

3. The memory controller of claim 1, wherein the memory controller is configured to:

4. The memory controller of claim 1, wherein the memory controller is configured to:

a sixth instruction is sent out; the sixth instruction indicates that the memory cells coupled to the Nth word line of each of the plurality of storage planes are programmed in a multi-plane programming manner.

5. The memory controller of claim 4, wherein the memory controller is configured to:

6. The memory controller of claim 4, wherein the memory controller is configured to:

7. The memory controller of claim 1, wherein the first buffer is disposed in a host or in the memory controller.

8. The memory controller of claim 7, wherein a first buffer is disposed in the host, and wherein determining that the first buffer does not satisfy a predetermined condition comprises:

9. A memory system, the memory system comprising: the memory controller of any of claims 1-8 and a plurality of memory chips coupled to the memory controller; wherein the content of the first and second substances,

each of the memory chips includes a plurality of memory planes, each of which includes a plurality of word lines respectively coupled to a plurality of memory cells.

10. The memory system according to claim 9, wherein the memory chip comprises a three-dimensional NAND-type memory.

11. The memory system of claim 9, wherein the number of storage bits of each of the plurality of memory cells comprises one or more bits.

12. The memory system of claim 9, wherein the number of storage bits for each of the plurality of memory cells comprises three bits.

13. A method of operating a memory controller, comprising:

14. The method of claim 13, further comprising:

15. The method of claim 13, further comprising:

16. The method of claim 13, further comprising:

a fifth instruction is sent; the fifth instruction indicates that data to be programmed to memory cells coupled to the Nth word line of each storage surface are backed up to the first buffer;

17. The method of claim 16, further comprising:

18. The method of claim 16, further comprising:

19. The method of claim 13, wherein the first buffer is disposed in a host or in the memory controller.

20. The method of claim 19, wherein the first buffer is disposed in a host, and wherein determining that the first buffer does not satisfy a predetermined condition comprises:

21. The method of claim 13, wherein determining that the first buffer satisfies the predetermined condition comprises:

22. The method of claim 13, further comprising:

and acquiring the first preset value before receiving the first instruction.