CN114781316A - Networking layout method, device, equipment and storage medium - Google Patents
Networking layout method, device, equipment and storage medium Download PDFInfo
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Abstract
The invention provides a networking layout method, a networking layout device, networking layout equipment and a storage medium, which belong to the field of integrated circuit chip design, wherein the networking layout method comprises the steps of carrying out networking segmentation on a design file according to a networking file to obtain a networking segmentation result, wherein the networking segmentation result is used for describing corresponding distribution positions, logical groups and connection relations among nodes of a hypergraph in a logical array system; acquiring physical networking data of the logic array; distributing each logic group in the networking segmentation result based on the physical networking data to obtain at least one first layout; and setting the first layout with the minimum interconnection cost as a final layout. By the processing scheme, the number of transfer routing paths, interconnection cost and communication delay are reduced, and the communication efficiency of the verification system is improved, so that the verification frequency is improved, and the verification process is accelerated.
Description
Technical Field
The invention relates to the field of integrated circuit chip design, in particular to a networking layout method, a networking layout device, networking layout equipment and a storage medium.
Background
When the resource consumed by the user chip design logic is larger than the upper limit of one editable logic device (FPGA), the user chip design needs to be divided into a plurality of parts, each part is called a logic group, each logic group is allocated to a corresponding FPGA, and the groups communicate with each other through the physical interconnection line between the FPGAs. In the existing segmentation process, a user chip design is directly segmented into N groups, and then the N groups are randomly distributed into a network of verification systems of M logic arrays. If the logic connection (communication signal) between the groups does not have direct physical connection, the path of the logic signal is adjusted, so that the logic signal is subjected to route transfer through other intermediate FPGAs. This may cause a large number of logical packets having external connection relations to be allocated to an edge of the networking topology, which is equivalent to a connection critical packet and a connection hot-spot packet, to be allocated to an edge zone, such as an edge of a matrix-type authentication array, which not only generates more routing relays and needs to span more interconnect lines, thereby increasing interconnection costs and increasing signal transmission delay, but also causes low communication efficiency, for example, other packets connected thereto need to communicate for a long distance to reach the edge, and then retrieve the signal processing result from the edge. In addition, the loose arrangement method may occupy more FPGAs, and the edge zone of the system array needs to perform signal routing through the transfer FPGA, and the transfer path occupies the unused FPGA, which not only increases unnecessary device loss, but also causes resource waste.
Disclosure of Invention
Therefore, in order to overcome the above disadvantages of the prior art, the present invention provides a networking layout method, apparatus, device and storage medium, which reduces the number of transit routing paths, interconnection cost and communication delay, and improves the communication efficiency of the verification system, thereby improving the verification frequency and speeding up the verification process.
In order to achieve the above object, the present invention provides a networking layout method, including: networking and segmenting the design file according to the networking file to obtain a networking and segmenting result, wherein the networking and segmenting result is used for describing corresponding distribution positions of the hypergraph nodes in the logic array system and the connection relation between the hypergraph nodes and each other; acquiring physical networking data of the logic array; distributing each logic group in the networking segmentation result based on the physical networking data to obtain at least one first layout; and setting the first layout with the minimum interconnection cost as a final layout.
In one embodiment, the allocating each logical grouping in the networking segmentation result based on the physical networking data to obtain at least one first layout includes: respectively setting each logic group in the networking segmentation result as a first layout node; and traversing the rest of the logic groups according to the breadth first, and distributing the logic groups of the networking segmentation result based on the physical networking data to obtain a plurality of first layouts.
In one embodiment, the allocating each logical grouping in the networking segmentation result based on the physical networking data to obtain at least one first layout includes: traversing all nodes, and taking the logic group with the largest selection value as a first layout node; determining the layout sequence of the logic groups of different levels according to the breadth-first access sequence; and distributing the logic groups based on the physical networking data and the layout sequence to obtain a first layout.
In one embodiment, the performing networking segmentation on the design file according to the networking file to obtain a networking segmentation result includes: performing networking segmentation on the design file according to the networking file to obtain a first segmentation result and a corresponding first segmentation negative influence function value; clustering the first segmentation result; performing node position theoretical adjustment on hypergraph nodes in each logic grouping in the clustered first segmentation result, calculating a segmentation negative influence function value after each adjustment, determining a minimum negative influence function value and actually adjusting the node positions in the logic grouping; re-clustering and iterating the previous operation until the reduction value with the minimum negative influence function value of the adjusted segmentation does not exceed the preset threshold value, and obtaining the networking segmentation result according to the logic grouping at the moment.
A networking arrangement comprising:
the networking segmentation module is used for performing networking segmentation on the design file according to the networking file to obtain a networking segmentation result, and the networking segmentation result is used for describing the corresponding distribution position, the logic grouping and the connection relation among the hypergraph nodes in the logic array system; the physical data acquisition module is used for acquiring physical networking data of the logic array; the distribution module is used for distributing each logic group in the networking division result based on the physical networking data to obtain at least one first layout; and the layout module is used for setting the first layout with the minimum interconnection cost as a final layout.
A computer arrangement comprising a memory and a processor, the memory storing a computer program, characterized in that the processor realizes the steps of the above method when executing the computer program.
A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the above-mentioned method.
Compared with the prior art, the invention has the advantages that: the connection relation between the physical networking data and the logic grouping of the networking files is combined, the layout with the minimum interconnection cost is generated, the number of transfer routing paths, the interconnection cost and the communication delay are reduced, and the communication efficiency of the verification system is improved, so that the verification frequency is improved, and the verification process is accelerated; meanwhile, the layout of the logic grouping is more compact and concentrated, the use number of logic arrays is saved, and the resource use efficiency is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a flow chart of a networking layout method in an embodiment of the invention;
FIG. 2 is a schematic diagram of a logical grouping in an embodiment of the present invention;
FIG. 3 is a schematic diagram of an embodiment of an editable logic array;
FIG. 4 is a flow diagram of a networking arrangement in an embodiment of the invention;
FIG. 5 is a schematic diagram of the logical grouping layout result in an embodiment of the present invention;
FIG. 6 is a flow diagram illustrating networking segmentation in an embodiment of the present invention;
fig. 7 is a block diagram of a configuration of a networking placement apparatus in an embodiment of the present invention;
fig. 8 is an internal configuration diagram of a computer device in an embodiment of the present invention.
Detailed Description
Embodiments of the present application are described in detail below with reference to the accompanying drawings.
The following embodiments of the present application are described by specific examples, and other advantages and effects of the present application will be readily apparent to those skilled in the art from the disclosure of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. The present application is capable of other and different embodiments and its several details are capable of modifications and/or changes in various respects, all without departing from the spirit of the present application. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.
It is noted that various aspects of the embodiments are described below within the scope of the appended claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present application, one skilled in the art should appreciate that one aspect described herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number and aspects set forth herein. Additionally, such an apparatus may be implemented and/or such a method may be practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present application, and the drawings only show the components related to the present application rather than the number, shape and size of the components in actual implementation, and the type, amount and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided to provide a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.
As shown in fig. 1, an embodiment of the present application provides a networking layout method, which may be applied to a terminal or a server, where the terminal may be, but is not limited to, various personal computers, notebook computers, smart phones, tablet computers, and portable smart devices, and the server may be implemented by an independent server or a server cluster formed by multiple servers, and the method includes the following steps:
And the server performs networking segmentation on the design file according to the networking file. The networking file is used for describing hardware resource information of the verification system, and may include the number of arrays of the editable logic devices, a topology structure between the editable logic devices, resource capacity and interconnection relation of each editable logic device, and the like. The networking division number is N, the hardware resource information comprises the total number M of the editable logic devices, a layout topological structure among the editable logic devices, interconnection line connection relation and the like, wherein M is larger than or equal to N. The logic grouping refers to a set of hypergraph nodes distributed on a certain FPGA, the logic grouping is a set of a plurality of hypergraph nodes, a plurality of hypergraph nodes are arranged in one logic grouping, and the connection weight between the two logic groupings is the sum of connections of the hypergraph nodes between the two hypergraph node sets.
The server may generate a networking layout file from the design file. The networking layout file may be a combination of the networking file and the layout file. The layout file contains a layout of logical groupings on the editable logical array. The design file is used for describing the structure of each circuit node of the circuit system and the connection relation among the circuit nodes. The design file contains a plurality of logic program blocks (modules), nesting or parallel relation exists among the logic program blocks, and each logic program block corresponds to each circuit node of the circuit system. A circuit node may be one or more electronic components. The design files can be format files such as Verilog, vhdl, systemVerilog and the like; the netlist is a mesh data structure formed by RTL after RTL logic synthesis, the design logic of a user is also described, and the RTL or netlist design forms a syntax tree diagram in a memory through a syntax parser. The RTL may be converted to a netlist by a logic synthesis process. The RTL and the netlist both have a hierarchical nested structure and both have logic program blocks containing logic functions, communication signals are arranged between the logic program blocks, and the signals can also pass through the logic program blocks to be transmitted into the logic program blocks. Thus, the server can convert the design file into a hypergraph structure through modeling and abstraction; and then, networking and segmenting the design file according to the networking file to obtain a networking segmentation result.
And the server acquires the physical networking data of the logic array from the hardware resource information. The physical networking data is the topological structure between the editable logic devices, the resource capacity and the interconnection relation of each editable logic device and the like.
And 103, distributing each logic group in the networking segmentation result based on the physical networking data to obtain at least one first layout.
The server distributes each logic group in the networking segmentation result based on the physical networking data to obtain at least one first layout. The server determines the placement order of the logical groups, i.e., which logical group is assigned first. For example, when a hypergraph structure of a design file after hypergraph modeling is shown in fig. 2, nodes represent logical groups, connection lines between the nodes represent communication relationships between the logical groups, and connection weights represent communication traffic volumes. The design file of fig. 2 is laid out in a matrix type FPGA array as shown in fig. 3. The server can determine the layout sequence of nodes in different levels according to the breadth-first access sequence, and determine the access sequence in the nodes on the same layer searched by breadth-first according to the order of edge weights from large to small. Then, the server puts the logic groups into the center of the matrix, and then sequentially performs layout according to the determined access sequence to obtain at least one first layout.
And step 104, setting the first layout with the minimum interconnection cost as a final layout.
The server sets the first layout with the minimum interconnection cost as the final layout. The interconnection cost is the number of times the edge weight crosses the logic array boundary times the edge weight, while the route distance is the manhattan distance of the direct turn, since there is only a physical interconnection line between adjacent logic arrays in the matrix.
According to the method, the layout with the minimum interconnection cost is generated by combining the connection relation between the physical networking data and the logic grouping of the networking file, the number of transfer routing paths, the interconnection cost and the communication delay are reduced, and the communication efficiency of the verification system is improved, so that the verification frequency is improved, and the verification process is accelerated; meanwhile, the layout of the logic grouping is more compact and concentrated, the use number of logic arrays is saved, and the resource use efficiency is improved.
In one embodiment, the allocating each logical grouping in the networking segmentation result based on the physical networking data to obtain at least one first layout includes: respectively setting each logic group in the networking segmentation result as a first layout node; and traversing the rest of logic groups according to the breadth first, and distributing the logic groups of the networking segmentation result based on the physical networking data to obtain a plurality of first layouts.
The server sets each logic group in the networking segmentation result as a first layout node respectively; and traversing the rest of logic groups according to the breadth first, and distributing the logic groups of the networking segmentation result based on the physical networking data to obtain a plurality of first layouts. Therefore, in this embodiment, the server generates a corresponding first layout according to each logical grouping, so as to perform the subsequent computational verification of the interconnection cost.
As shown in fig. 4, in one embodiment, the allocating each logical grouping in the networking segmentation result based on the physical networking data to obtain at least one first layout includes:
And traversing all the nodes by the server, and taking the logic group with the maximum selection value as a first layout node. The selection value refers to the number of external connecting lines of the hypergraph node. Taking fig. 2 as an example, the selectivity value of node D is 4, and node D is the first layout node.
And the server determines the layout sequence of the logic groups of different levels according to the breadth-first access sequence. The server takes the point D as a starting point, determines the layout sequence of nodes in different layers according to the breadth-first access sequence, and determines the access sequence in the breadth-first searched nodes in the same layer according to the order of the edge weights from large to small (because the interconnection cost possibly caused by the large edge weight is also large, placing the corresponding nodes at first is beneficial to reducing the interconnection cost, and reducing extra FPGA (field programmable gate array) crossing connecting lines caused by position occupation/limitation), and the access sequences are respectively E, B, C, G, F and A.
Based on the rectangular logic array matrix with the side length of 4 x 3 in fig. 3, the server firstly puts the first layout node D in the center of the matrix, and then performs layout according to E, B, C, G, F and a in sequence. Specifically, the server refers to a first access circle, where the server is connected with other nodes in a distance order according to a breadth-first access order, that is, according to a distance order in which a certain point is used as a starting point, such as D, and if the point D walks over an edge once, the point B, C, E, and G can be reached; starting from any point of B, C, E and G, and walking once again to reach all points of a second access circle; if a point can be contained from different paths by multiple access circles, the smallest access circle is the criterion. Then, the server randomly selects one of the areas with 3 same costs that B can select according to the access sequence, and gradually selects one of the areas according to the access sequence until the last node. Thus in the figure, the server may obtain at least one first layout centred on node D.
In one embodiment, when the nodes are placed in step 403, the principle of "finding a position where the interconnection cost generated by the new node to be allocated and the node in the matrix that has completed the placement is the minimum" may also be followed, and then the final initial placement and routing result is fig. 5. When placing G, the selectable area of G is unique, otherwise, placing any other unoccupied position generates larger interconnection cost with the placed node. When E, B, C are assigned in order, then G is assigned: the G is tried to be allocated to any FPGA which is not allocated, for example, the second FPGA in the first row in fig. 5, and the interconnection cost generated with the existing layout node is 4+4+1= 9; g if assigned to the upper left corner, the resulting interconnection cost is 4+1+1= 6; and if the G is placed at other positions, the positions with interconnection cost less than 6 can not be found, the allocation positions of all the G are the upper left corners and the configuration is completed, and a new existing layout state is formed with the existing nodes in the matrix and is named as state _ G temporarily. And when the subsequent node A to be distributed is distributed, trying to select the position with the minimum interconnection cost on other unallocated FPGAs in the state _ G.
Moreover, a right-angle path between the white node G and the node D is also a transfer path, a formed distance is called a manhattan distance, and an FPGA (FPGA where G is located) between the white node G and the node D, which completes the transfer of the connection line, is called a transfer FPGA between the GD. As shown in fig. 5, the three FPGAs on the right side are not used, and if all nodes are arranged according to random positions, it is very likely to form a dispersed arrangement, and then the relay connection line has to pass through the FPGAs that should not be used, and the FPGAs that should not be used are added into the verification system due to the relay, which causes waste of system hardware resources.
As shown in fig. 6, in an embodiment, the networking and segmenting the design file according to the networking file to obtain a networking and segmenting result includes:
And the server performs initial segmentation on the design file according to the hardware resource information in the networking file to obtain an initial segmentation result and a corresponding initial segmentation negative influence function value. And the server reads in the design file, performs initial segmentation on the design file according to the hardware resource information and the minimum segmentation principle to obtain an initial segmentation result, and calculates a segmentation negative influence function value Bad _ mul of the initial segmentation result. And the server generates a segmentation result variable Group _ var, wherein the segmentation result variable Group _ var describes the corresponding distribution positions of the hypergraph nodes in the logic array system, the connection relation among the hypergraph nodes and the corresponding segmentation negative influence function values. The set of all the segmentation result variables Group _ var constitutes the initial segmentation result.
And clustering the initial segmentation result by the server. The server can cluster a plurality of small nodes which are tightly connected into a large node according to the tight degree of the connection relation of each node, the weight of the large node is the sum of the weights of the small nodes, the external connection relation of the large node inherits the external connection relation of all the small nodes, and the connection relation between the small nodes and the connection relation inside the small nodes are hidden, so that the packaging and clustering operation of the nodes is realized.
And the server carries out node position theoretical adjustment on each logic group in the clustered initial segmentation result, calculates the segmentation negative influence function value after each adjustment, determines the minimum negative influence function value and actually adjusts the node position in the logic group. Assuming that the number of the clustered nodes is N, and numbering the nodes from 1 to N in sequence; the number of logic arrays of the verification system is M, and the logic arrays are numbered from 1 to M in sequence. M queue structures are created, each having a length of N. Starting from the node 1, keeping the positions of other nodes unchanged, sequentially trying to allocate the node 1 in a 1 st block logic array and a 2 nd block logic array …, until the position of other nodes remains unchanged in an Mth block logic array, dispersing large nodes after each allocation, calculating a negative impact function value Bad _ mul of the allocation attempt, storing the value in the first position of a corresponding queue, and if the node 1 tries to allocate in the x-th block logic array, storing the function value in the 1 st position of the x-th block logic array; if the node with the number e attempts to be allocated in the x-th block logic array, the function value is stored in the e-th position of the x-th block logic array. That is, the node's sequence number represents its position in the queue, and the logical array position that the node attempts to assign represents its position in the queue. According to the method, position adjustment is tried on each node from 1 to N, the corresponding adjusted negative influence function value Bad _ mul is stored in a queue, and in the process of trying to distribute a certain node, other nodes keep the position unchanged. The scatter operation is the inverse operation of the clustering operation in step 302, that is, the large node is restored to the form of the small node set, so as to facilitate the calculation of the negative impact function value.
When the server determines the minimum negative impact function value and actually adjusts the node position in the logical grouping. Taking the minimum value of all elements in the M queues, and if the minimum value is larger than the negative influence function value of the initial segmentation in the Group _ var, terminating the flow; otherwise, continuing. For example, if the jth element of the ith queue is the minimum, the optimal operation in this iteration may be determined as: and moving the jth large node to the ith logic array. And the server updates the segmentation result variable obtained after the logic grouping adjustment into a Group _ var.
And step 604, re-clustering and iterating the previous operation until the reduction value with the minimum adjusted segmentation negative influence function value does not exceed a preset threshold value, and obtaining a networking segmentation result according to the logic grouping at the moment.
And re-clustering the servers, and iterating the previous operation until the reduction value with the minimum function value of the adjusted segmentation negative influence does not exceed a preset threshold value, and obtaining an optimized networking segmentation result according to the logic grouping at the moment.
According to the method, the version with better performance is obtained step by means of node clustering and dispersion and continuous adjustment of positions to optimize the segmentation result.
In one embodiment, the segmentation negative impact function value Bad _ mul may represent the magnitude of the negative impact on the verification system from the perspective of different segmentation method principles. Bad _ mul = k 1+ Bad _ ffd + k2 + Bad _ clk + k3 + Bad _ delay + k 4+ Bad _ tdm + … + kn + Bad _
Bad _ mul can refer to overall negative influence, which includes user-specifiable configuration influencing factors Bad _ and corresponding influencing system kn, and the influencing factors should be kept isolated and independent from each other in principle and segmentation target as much as possible, so as to avoid errors introduced by repeated analysis.
Wherein Bad _ ffd is a cutting strategy impact value based on the register distribution position. The digital logic circuit designed by users usually has a plurality of registers, data is regularly and periodically transferred between the registers under a clock with a certain beat, in a clock period, the data has a certain preparation time to achieve the mutual cooperation of the circuit system, and paths with less combinational logic exist between the registers, the data waiting gap is large, and the paths can be cut on the paths to utilize the gap redundancy. The calculation method of Bad _ ffd is as follows: identifying logic in user design, screening paths between register pairs, and calculating delay generated by combinational logic on the paths between the register pairs; the cut paths are traversed and enumerated, i.e., paths between logic arrays are crossed, and the delays generated by the combinational logic passing through the paths are summed to obtain Bad _ ffd.
Bad _ clk is a clock domain based cut policy impact value. If the areas are cut, i.e. a large delay is added in the clock domain, the delay is transferred to the logic circuit which receives and uses the clock domain to output clock signals, so that the limitation to the system frequency is caused, and therefore, the cutting method protects the clock domain, i.e. the clock domain is not cut. The calculation method of Bad _ clk is as follows: identifying all clock domains, and defining importance weight of each clock domain according to the range covered by the clock signal output by the clock domain; traversing the cutting times of each clock domain, cutting the clock domain once, and adding the weight value of the corresponding clock domain by Bad _ clk.
Bad _ delay is a partitioning policy impact value based on a timing analysis critical path. The segmentation method takes the time sequence performance as an optimization target, carries out advanced time sequence analysis on user design logic before segmentation, and identifies a critical path, namely a circuit path with higher requirements on key and time in a digital circuit, wherein if excessive time delay is introduced into the path of the type, the working frequency of the whole system is influenced. The partitioning method needs to allocate the critical path to the logic array as much as possible to avoid being partitioned. The calculation method of Bad _ delay comprises the following steps: firstly, carrying out static Time sequence analysis on a user logic circuit to obtain a margin value (Slack) of the Setup Time (Setup Time) and the Hold Time (Hold Time) of each Time sequence path; dividing the time sequence path into a critical path and a non-critical path according to a preset margin threshold, wherein the margin of the critical path is smaller than the threshold; all the cut critical paths are counted (namely the paths cross the logic array), and the cable delay generated by crossing the logic array is calculated and accumulated to obtain Bad delay.
Bad _ TDM is a TDM-based cutting strategy impact value. TDM is a time division multiplexing device, which in practice refers to an IP core capable of performing serial-to-parallel conversion, operating in a logic array with customer design. The occurrence of the method is to solve the bottleneck that the number of physical cables between logic arrays is limited, parallel-parallel serial connection is carried out on signals needing to be transmitted between the logic arrays before transmission, and serial-parallel operation is carried out after the signals reach a target FPGA through interconnection lines to separate the signals. The time division multiplexing ratio, i.e. how many signals share a cable, often determines the operating frequency of the whole system, the local maximum time division multiplexing ratio will cause the local maximum delay, and the local maximum delay determines the highest operating frequency of the whole system. The calculation method of Bad _ tdm is as follows: and calculating the number of logic signals and the number of actual physical cables which need to be transmitted through the interconnection line between each pair of logic arrays by combining networking information, dividing the number of the logic signals by the number of the actual physical cables to obtain TDM Ratio, and taking the maximum Ratio between the logic array pairs as Bad _ TDM.
In one embodiment, as shown in fig. 7, a networking layout apparatus is provided, and the apparatus includes a networking partitioning module 701, a physical data obtaining module 702, an allocating module 703 and a layout module 704.
And the networking segmentation module 701 is used for performing networking segmentation on the design file according to the networking file to obtain a networking segmentation result, and the networking segmentation result is used for describing corresponding distribution positions, logic groups and connection relations among the hypergraph nodes in the logic array system.
A physical data acquiring module 702, configured to acquire physical networking data of the logical array.
The allocating module 703 is configured to allocate each logical grouping in the networking segmentation result based on the physical networking data, so as to obtain at least one first layout.
And a layout module 704, configured to set the first layout with the smallest interconnection cost as the final layout.
In one embodiment, the assignment module includes:
and a first node setting unit, configured to set each logical grouping in the networking division result as a first layout node.
And the layout unit is used for traversing the remaining logic groups according to the breadth first and distributing the logic groups of the networking segmentation result based on the physical networking data to obtain a plurality of first layouts.
In one embodiment, the assignment module includes:
and the first node setting unit is used for traversing all the nodes and taking the logic group with the maximum selection value as a first layout node.
And the sequence determining unit is used for determining the layout sequence of the logic groups of different layers according to the breadth-first access sequence.
And the layout unit is used for distributing the logic grouping based on the physical networking data and the layout sequence to obtain a first layout.
In one embodiment, the networking segmentation module comprises:
and the segmentation unit is used for performing networking segmentation on the design file according to the networking file to obtain a first segmentation result and a corresponding first segmentation negative influence function value.
And the clustering unit is used for clustering the first segmentation result.
And the adjusting unit is used for carrying out node position theoretical adjustment on the hypergraph nodes in each logic grouping in the clustered first segmentation result, calculating the segmentation negative influence function value after each adjustment, determining the minimum negative influence function value and actually adjusting the node positions in the logic grouping.
And the iteration unit is used for re-clustering and iterating the previous operation until the reduction value with the minimum adjusted segmentation negative influence function value does not exceed a preset threshold value, and obtaining a networking segmentation result according to the logic grouping at the moment.
For specific definition of the networking layout device, reference may be made to the definition of the networking layout method in the foregoing, and details are not described here again. All or part of each module in the networking layout device can be realized by software, hardware and a combination thereof. The modules can be embedded in a hardware form or independent of a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
In one embodiment, a computer device is provided, which may be a server, and the internal structure thereof may be as shown in fig. 8. The computer device includes a processor, a memory, a network interface, and a database connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operating system and the computer program to run on the non-volatile storage medium. The database of the computer device is used for storing data such as networking files and the like. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a method of networking layout.
Those skilled in the art will appreciate that the architecture shown in fig. 8 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, there is provided a computer device comprising a memory storing a computer program and a processor implementing the following steps when the processor executes the computer program: networking and segmenting the design file according to the networking file to obtain a networking segmentation result, wherein the networking segmentation result is used for describing corresponding distribution positions of the hypergraph nodes in the logic array system and the connection relation among the hypergraph nodes; acquiring physical networking data of the logic array; distributing each logic group in the networking segmentation result based on physical networking data to obtain at least one first layout; and setting the first layout with the minimum interconnection cost as the final layout.
In one embodiment, the allocating, by the processor when executing the computer program, each logical grouping in the networking segmentation result based on the physical networking data to obtain at least one first layout includes: respectively setting each logic group in the networking segmentation result as a first layout node; and traversing the rest of logic groups according to the breadth first, and distributing the logic groups of the networking segmentation result based on the physical networking data to obtain a plurality of first layouts.
In one embodiment, the allocating, by the processor when executing the computer program, each logical grouping in the networking segmentation result based on the physical networking data to obtain at least one first layout includes: traversing all nodes, and taking the logic group with the largest selection value as a first layout node; determining the layout sequence of the logic groups of different levels according to the breadth-first access sequence; and distributing the logic groups based on the physical networking data and the layout sequence to obtain a first layout.
In one embodiment, the implementation of the networking segmentation of the design file according to the networking file when the processor executes the computer program to obtain the networking segmentation result includes: performing networking segmentation on the design file according to the networking file to obtain a first segmentation result and a corresponding first segmentation negative influence function value; clustering the first segmentation result; performing node position theoretical adjustment on hypergraph nodes in each logic grouping in the clustered first segmentation result, calculating a segmentation negative influence function value after each adjustment, determining a minimum negative influence function value and actually adjusting the node positions in the logic grouping; and re-clustering and iterating the previous operation until the reduction value with the minimum adjusted segmentation negative influence function value does not exceed a preset threshold value, and obtaining a networking segmentation result according to the logic grouping at the moment.
In one embodiment, a computer-readable storage medium is provided, having a computer program stored thereon, which when executed by a processor, performs the steps of: networking and segmenting the design file according to the networking file to obtain a networking segmentation result, wherein the networking segmentation result is used for describing corresponding distribution positions of the hypergraph nodes in the logic array system and the connection relation among the hypergraph nodes; acquiring physical networking data of the logic array; distributing each logic group in the networking segmentation result based on physical networking data to obtain at least one first layout; and setting the first layout with the minimum interconnection cost as the final layout.
In one embodiment, the computer program, when executed by the processor, performs the assigning of each logical grouping in the networking segmentation result based on the physical networking data, to obtain at least one first layout, including: respectively setting each logic group in the networking segmentation result as a first layout node; and traversing the rest of logic groups according to the breadth first, and distributing the logic groups of the networking segmentation result based on the physical networking data to obtain a plurality of first layouts.
In one embodiment, the computer program, when executed by the processor, performs the assigning of each logical grouping in the networking segmentation result based on physical networking data, and obtains at least one first layout, including: traversing all nodes, and taking the logic group with the largest selection value as a first layout node; determining the layout sequence of the logic groups of different levels according to the breadth-first access sequence; and distributing the logic groups based on the physical networking data and the layout sequence to obtain a first layout.
In one embodiment, the implementation of the computer program when executed by a processor for performing networking segmentation on a design file according to a networking file to obtain a networking segmentation result includes: performing networking segmentation on the design file according to the networking file to obtain a first segmentation result and a corresponding first segmentation negative influence function value; clustering the first segmentation result; performing node position theoretical adjustment on hypergraph nodes in each logic grouping in the clustered first segmentation result, calculating a segmentation negative influence function value after each adjustment, determining a minimum negative influence function value and actually adjusting the node positions in the logic grouping; and re-clustering and iterating the previous operation until the reduction value with the minimum adjusted segmentation negative influence function value does not exceed a preset threshold value, and obtaining a networking segmentation result according to the logic grouping at the moment.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database or other medium used in the embodiments provided herein can include non-volatile and/or volatile memory. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (7)
1. A networking layout method, comprising:
networking and segmenting the design file according to the networking file to obtain a networking and segmenting result, wherein the networking and segmenting result is used for describing corresponding distribution positions, logic groups and connection relations among the corresponding distribution positions, logic groups and the logic groups of the hypergraph nodes in the logic array system;
acquiring physical networking data of the logic array;
distributing each logic group in the networking segmentation result based on the physical networking data to obtain at least one first layout;
and setting the first layout with the minimum interconnection cost as a final layout.
2. The method of claim 1, wherein the assigning each logical grouping in the networking segmentation result based on the physical networking data to obtain at least one first layout comprises:
respectively setting each logic group in the networking segmentation result as a first layout node;
traversing the rest of the logic groups according to the breadth first, and distributing the logic groups of the networking segmentation result based on the physical networking data to obtain a plurality of first layouts.
3. The method of claim 1, wherein the assigning each logical grouping in the networking segmentation result based on the physical networking data to obtain at least one first layout comprises:
traversing all nodes, and taking the logic group with the largest selection value as a first layout node;
determining the layout sequence of the logic groups of different levels according to the breadth-first access sequence;
and distributing the logic groups based on the physical networking data and the layout sequence to obtain a first layout.
4. The method according to claim 1, wherein the networking segmentation is performed on the design file according to the networking file to obtain a networking segmentation result, and the method comprises the following steps:
performing networking segmentation on the design file according to the networking file to obtain a first segmentation result and a corresponding first segmentation negative influence function value;
clustering the first segmentation result;
performing node position theoretical adjustment on hypergraph nodes in each logic grouping in the clustered first segmentation result, calculating a segmentation negative influence function value after each adjustment, determining a minimum negative influence function value and actually adjusting the node positions in the logic grouping;
re-clustering and iterating the previous operation until the reduction value with the minimum negative influence function value of the adjusted segmentation does not exceed the preset threshold value, and obtaining the networking segmentation result according to the logic grouping at the moment.
5. A networking arrangement, comprising:
the networking segmentation module is used for performing networking segmentation on the design file according to the networking file to obtain a networking segmentation result, and the networking segmentation result is used for describing the corresponding distribution position, the logic grouping and the connection relation among the hypergraph nodes in the logic array system;
the physical data acquisition module is used for acquiring physical networking data of the logic array;
the distribution module is used for distributing all logic groups in the networking segmentation result based on the physical networking data to obtain at least one first layout;
and the layout module is used for setting the first layout with the minimum interconnection cost as a final layout.
6. A computer device comprising a memory and a processor, the memory storing a computer program, wherein the processor when executing the computer program performs the steps of the method according to any of claims 1 to 4.
7. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 4.
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