CN114780464B

CN114780464B - Serial data transmission circuit and data transmission method

Info

Publication number: CN114780464B
Application number: CN202210665744.XA
Authority: CN
Inventors: 黎明; 刘云杰; 陈虎; 周锦; 邓梁; 汪文心
Original assignee: Hunan Guliang Microelectronics Co ltd
Current assignee: Hunan Guliang Microelectronics Co ltd
Priority date: 2022-06-14
Filing date: 2022-06-14
Publication date: 2022-09-23
Anticipated expiration: 2042-06-14
Also published as: CN114780464A

Abstract

The present application relates to a serial data transmission circuit and a data transmission method, the circuit including a transmitting-side circuit and a receiving-side circuit. The sending control circuit is used for shifting the data in the sending shift register to a data output signal according to bits, and the sending interruption unit is used for indicating the CPU to write new data into the sending buffer register. The receiving shift register of the receiving end circuit is used for storing data currently being received, the receiving control circuit is used for shifting the data of the data input signal to the receiving shift register according to bits, the receiving backup register is used for backing up the data in the receiving shift register, the receiving buffer register is used for storing data words to be read, and the receiving interrupt unit is used for indicating the CPU to read new data from the receiving buffer register. The data transmission rate and the flexibility are effectively considered.

Description

Serial data transmission circuit and data transmission method

Technical Field

The invention belongs to the technical field of data transmission, and relates to a serial data transmission circuit and a data transmission method.

Background

In the fields of consumer electronics, industrial control, etc., a large number of peripheral subsystems or interface converters are required to communicate with the CPU serially, such as audio codecs, analog interface chips, a/D and D/a converters. Different data types have different time characteristics, requiring serial transmission circuits with high speed and very high flexibility. The conventional serial transmission circuit still has the technical problem that the transmission rate and the flexibility cannot be considered in the above applications, and a high-rate and flexible serial data transmission circuit scheme is urgently needed.

Disclosure of Invention

In view of the above problems in the conventional technologies, the present invention provides a high-speed and flexible serial data transmission circuit and a serial data transmission method.

In order to achieve the above purpose, the embodiment of the present invention adopts the following technical solutions:

on one hand, the serial data transmission circuit comprises a sending end circuit and a receiving end circuit, wherein the sending end circuit comprises a sending buffer register, a sending shift register, a sending control circuit and a sending interrupt unit;

the sending buffer register and the receiving buffer register are respectively used for being connected to the CPU through a data bus, and the sending shift register is respectively connected with the sending buffer register, the sending control circuit and the sending interrupt unit; the receiving shift register is connected with the receiving control circuit, and the receiving backup register is respectively connected with the receiving shift register, the receiving buffer register and the receiving interrupt unit;

the transmission control circuit is used for shifting the data in the transmission shift register to a data output signal according to the bit, and the transmission interrupt unit is used for indicating the CPU to write new data into the transmission buffer register;

the receiving shift register is used for storing data currently being received, the receiving control circuit is used for shifting data of a data input signal to the receiving shift register according to bits, the receiving backup register is used for backing up the data in the receiving shift register, the receiving buffer register is used for storing data words to be read, and the receiving interrupt unit is used for indicating the CPU to read new data from the receiving buffer register.

On the other hand, a serial data transmission method is also provided, which is applied to the serial data transmission circuit, and the method comprises the following steps:

resetting a sending buffer register, a sending shift register and a sending control circuit, and setting an interrupt enable signal, a word length parameter, a frame length parameter, a sending mode parameter and a channel mode parameter of a sending end;

when the ready-to-send state signal jumps from invalid to valid, the sending interruption unit sends an interruption signal to the CPU, and the sending buffer register stores data written by the CPU through a system bus;

when the sending ready state signal is invalid and the word sending completion signal is valid, if the channel is enabled, copying data in the sending buffer register to a sending shift register, turning the sending ready state signal to be valid, and turning the word sending completion signal to be invalid;

if the channel is enabled, the sending control circuit shifts the data in the sending shift register to the data output signal according to the MSB principle; the first bit data of the first channel of each frame is transmitted and simultaneously generates a frame synchronization signal, a word transmission completion signal is turned into valid after each shifting is completed by one data word, and if the channel is not forbidden or unmasked, the data shifted out according to the bit appears on the data output signal.

One of the above technical solutions has the following advantages and beneficial effects:

the serial data transmission circuit and the data transmission method complete the data transmission and reception functions by adopting a transmitting end circuit consisting of a transmitting buffer register, a transmitting shift register, a transmitting control circuit and a transmitting interrupt unit and a receiving end circuit consisting of a receiving shift register, a receiving control circuit, a receiving backup register, a receiving buffer register and a receiving interrupt unit. At the transmitting end, after the transmission interrupt unit instructs the CPU to write new data to be transmitted into the transmission buffer register, the written data can be directly copied into the transmission shift register as the data to be transmitted currently when the channel is enabled, and the transmission control circuit shifts the data in the transmission shift register to the data output signal according to the bit, namely, the data can be transmitted outwards through the data output signal. The data transmission rate is high and multiple operating modes can be supported.

At the receiving end, when there is a data input signal sent from outside, the receiving control circuit can shift the data on the data input signal to the receiving shift register for storage according to the received frame synchronization signal, then copy and backup the data through the receiving backup register, so that the data stored in the receiving buffer register is read and then the data from the receiving backup register is received as new data to be read, and then the receiving interrupt unit informs the CPU to continue to read the new data from the receiving buffer register, and the receiving control circuit has high data receiving rate and can support multiple working modes.

Compared with a traditional serial transmission circuit, the circuit has the advantages that the transmission rate is high, the flexible working mode is supported, the transmission rate and the flexibility are effectively considered, the circuit structure is simple, and the usability is good.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of a serial data transmission circuit according to an embodiment;

FIG. 2 is a schematic diagram of a transmit control circuit according to one embodiment;

FIG. 3 is a block diagram of a receive control circuit in one embodiment;

FIG. 4 is a flow diagram illustrating a serial data transmission method according to one embodiment;

FIG. 5 is a diagram illustrating the steps of serial data transmission in one embodiment;

FIG. 6 is a flow chart illustrating a serial data transmission method according to another embodiment;

FIG. 7 is a diagram illustrating the steps of serial data reception in one embodiment;

FIG. 8 is a diagram illustrating an example of data transmission in an enabled and unmasked mode in one embodiment;

FIG. 9 is a diagram illustrating an example of a masked and disabled mode of data transmission in one embodiment;

FIG. 10 is a diagram illustrating an example of data transmission in an enabled and maskable mode, under an embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It should be appreciated that reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.

One skilled in the art will appreciate that the embodiments described herein can be combined with other embodiments. The term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

The following detailed description of embodiments of the invention will be made with reference to the accompanying drawings.

Aiming at the technical problem that the transmission rate and the flexibility of the traditional serial transmission circuit can not be considered in some practical applications, the application provides a flexible time division multiplexing serial data transmission circuit solution, which can realize: 1) enable and not mask: all time channels in the data frame are occupied and effective data are sent; 2) masking and disabling: the shielded and forbidden time channel is released for other equipment to transmit data; 3) enable and maskable: all time channels within a data frame are occupied, but the masked channels have no valid data transmission (nullification). The serial data transmission circuit has the advantages of flexibility, simplicity, easiness in use and the like.

To facilitate understanding of the concepts of the present application, definitions of related terms are provided herein:

data word (word): is the basic unit of data transmission. Such as when the word length parameter (which may be denoted as XWDLEN) =0, 1, 2, 3, 4, or 5, the word length is 8, 12, 16, 20, 24, or 32 bits, respectively.

A channel: a channel refers to a time period on the data output signal (which may be denoted as DX) occupied by the successive transmission of a word.

And (3) data frame: a set of data words is transmitted in succession over the occupied channel. When the frame length parameter (which may be denoted as XWNUM) =0, 1, 2, 3, 4, 5, 6, or 7, the frame lengths are 16, 32, 48, 64, 80, 96, or 128, respectively, i.e., the frame length is at most 128.

Channel enable and disable: when a channel is enabled, data transmission is allowed in a corresponding time period, the transmission control circuit allows the data in the transmission shift register to be shifted out bit by bit, but whether the data appears on the data output signal DX depends on whether the channel is shielded or not; when a lane is disabled, no data transmission is allowed for the corresponding time period (DX state is high impedance).

Shielding the channel: when one channel is enabled, data transmission is allowed in a corresponding time period, and if the channel is not shielded, the data appears on the output signal DX; if the channel is masked then data will not appear on the output signal DX (DX state is high). One channel is blocked while the other is blocked.

The working mode is as follows: the system comprises the above 3 working modes, which are controlled by the sending/receiving mode parameters (which can be marked as XMODE [1:0]/RMODE [1:0 ]), and the sending/receiving channel mode parameters (which can be marked as XCM [127:0]/RCM [127:0 ]). Each bit in XCM/RCM corresponds to a channel:

enable and not mask: transmission mode parameter XMODE =0 (mode 1) or reception mode parameter RMODE =0 (mode 1), and the setting of transmission channel mode parameter XCM or reception channel mode parameter RCM is invalid. All time channels within a data frame are occupied and there is efficient data transmission.

Masking and inhibiting: a transmission mode parameter XMODE =1 (mode 2) or a reception mode parameter RMODE =1 (mode 2); transmit channel mode parameter XCM [ [ alpha ] ]i]=1 (active) or reception channel mode parameter RCM [ [ solution ] ]i]=1 (active), meaning that the channel is enabled and not shieldedi(ii) a Sending channel mode parameter XCM [, ]i]=0 (invalid) or reception channel mode parameter RCM [ ]i]=0 (invalid), meaning disabling and masking the channeli. The masked and disabled time channel is released for other devices to transmit data.

Enable and maskable: transmit mode parameter XMODE =2 (mode 3) or receive mode parameter RMODE =2 (mode 3); transmit channel mode parameter XCM [ [ alpha ] ]i][1 (active) or reception channel mode parameter RCM ], [ 2 ]i]=1 (effective), meaning unshielded channeli(ii) a Transmit channel mode parameter XCM [ [ alpha ] ]i]=0 (invalid) or reception channel mode parameter RCM [ ]i]=0 (invalid), representing a mask channeli. Channels are enabled, all time channels within a data frame are occupied, but the shielded channels have no valid data transmission (nullification).

Referring to fig. 1, in one embodiment, a serial data transmission circuit 100 includes a transmitting circuit 12 and a receiving circuit 14. The transmitting-side circuit 12 includes a transmission buffer register 122, a transmission shift register 124, a transmission control circuit 126, and a transmission interrupt unit 128. The receiving-end circuit 14 includes a receiving shift register 142, a receiving control circuit 144, a receiving backup register 146, a receiving buffer register 148, and a receiving interrupt unit 149. The transmission buffer register 122 and the reception buffer register 148 are respectively used for connection to the CPU through a data bus. The transmission shift register 124 is connected to the transmission buffer register 122, the transmission control circuit 126, and the transmission interrupt unit 128, respectively. The reception shift register 142 is connected to the reception control circuit 144, and the reception backup register 146 is connected to the reception shift register 142, the reception buffer register 148, and the reception interrupt unit 149, respectively.

The transmit buffer register 122 is used to store data words to be transmitted. The transmit shift register 124 is used to hold data that is currently being transmitted. The transmit control circuit 126 is used to shift the data in the transmit shift register 124 to the data output signal. The transmit interrupt unit 128 is used to instruct the CPU to write new data to the transmit buffer register 122. The receive shift register 142 is used to hold data currently being received. The reception control circuit 144 is used to shift data of the data input signal to the reception shift register 142. The receive backup register 146 is used to backup the data in the receive shift register 142. The receive buffer register 148 is used to store the data word to be read. The receive interrupt unit 149 is used to instruct the CPU to read new data from the receive buffer 148.

It can be understood that the CPU refers to a microprocessor of a system/device with which the serial data transmission circuit 100 needs to perform serial communication (e.g., data transmission and reception), and the connection between the circuit components of the serial data transmission circuit 100 may be communication connection, or electrical connection, or connection in a mixed manner of communication and power, and may be determined according to the needs of the application, as long as the transmission function of data, signals, and the like between the circuit components can be realized. The serial data transmission circuit 100 may adopt a discrete component layout design, or may adopt a layout design integrally designed on a substrate, and may be specifically selected according to process requirements.

The send buffer register 122 (which may be denoted DXR) may be a register component that enables a storing function of a data word to be sent, and may perform an update of stored data, such as receiving new data to be sent written by the CPU, under control of a send ready state signal (which may be denoted XRDY). The transmit shift register 124 (which may be denoted as XSR) may be a register component capable of performing a store function for data currently being transmitted (shifted), and its operational state may be controlled by a transmit ready state signal XRDY and a word transmit complete signal (which may be denoted as XWDONE), which data is from a copy of the data in DXR.

The transmission control circuit 126 can be implemented by, but not limited to, a microcontroller, a programmable logic circuit, or other control chips, as long as the required data shift control function and word transmission state feedback function can be implemented. For simplicity, as a reset signal (may be denoted as RSTn) and a system operating clock (may be denoted as SYSCLK) of the circuit are not shown in fig. 1, those skilled in the art can understand that in practical applications, the signal and the clock may also be accessed by each component that needs the foregoing RSTn and SYSCLK to ensure normal operation thereof, and the access manner of the signal and the clock may be understood in the same way as the addition manner of the existing reset signal and system operating clock in the art.

The data output signal DX is an external transmission signal containing data to be transmitted, and can be used as an external input (i.e., a data input signal) of the receiving end of the serial data transmission circuit 100 in other systems/devices. Transmit interrupt unit 128 may be a circuit element or module capable of providing the required interrupt signals for generating interrupt signals to the CPU, thereby informing the CPU that new data may be written to transmit buffer 122.

The receive shift register 142 (which may be denoted as RSR) may be a register component that enables a storing function of data currently being received (shifted), which is stored from data in the external data input signal DR. The receiving control circuit 144 may be implemented by, but not limited to, a microcontroller, a programmable logic circuit, or other control chips, as long as the required data shift control function and word receiving state feedback function can be implemented. The receive backup register 146 (which may be designated as RBR) may be a register component that enables data backup storage functionality, with the data backed up from RSR.

The receive buffer 148 (which may be designated as DRR) may be a register component that enables the storage function of the data word to be read, and may perform the update of the stored data under the control of a receive completion status signal (which may be designated as RRDY), such as the DRR may receive new data to be read from the RBR after the CPU completes the reading of the stored data via the data bus. The receive interrupt unit 149 may be a circuit element or circuit module capable of providing a required interrupt signal for generating an interrupt signal to the CPU, thereby informing the CPU that new data can be read from the DRR.

The serial data transmission circuit 100 completes data transmission and reception functions by using the transmitting-side circuit 12 including the transmission buffer register 122, the transmission shift register 124, the transmission control circuit 126, and the transmission interrupt unit 128, and the receiving-side circuit 14 including the reception shift register 142, the reception control circuit 144, the reception backup register 146, the reception buffer register 148, and the reception interrupt unit 149. At the transmitting end, after the transmitting interrupt unit 128 instructs the CPU to write new data to be transmitted into the transmitting buffer register 122, the written data can be directly copied into the transmitting shift register 124 as the data to be transmitted currently when the channel is enabled, and the transmitting control circuit 126 shifts the data in the transmitting shift register 124 to the data output signal according to the bit, that is, the data can be transmitted to the outside through the data output signal. The data transmission rate is high and multiple operating modes can be supported.

At the receiving end, when there is a data input signal sent from the outside, the receiving control circuit 144 may shift the data on the data input signal to the receiving shift register 142 for storage according to the received frame synchronization signal, and then copy and backup the data through the receiving backup register 146, so that the receiving buffer register 148 receives the data from the receiving backup register 146 as new data to be read after the stored data is completely read, and then the receiving interrupt unit 149 notifies the CPU to continue to read the new data from the receiving buffer register 148, and the receiving control circuit has a high data receiving rate and can support multiple operating modes. Compared with a traditional serial transmission circuit, the circuit has the advantages that the transmission rate is high, the flexible working mode is supported, the transmission rate and the flexibility are effectively considered, the circuit structure is simple, and the usability is good.

In one embodiment, the transmit buffer register 122 copies the data word to be transmitted to the transmit shift register 124 and flips the transmit ready state signal XRDY and the word transmit complete signal XWDONE if the transmit control circuit 126 allows copying of the data in the transmit buffer register 122 while the transmit ready state signal XRDY is inactive and the word transmit complete signal XWDONE is active. The send buffer register 122 may receive and store a data word to be sent written by the CPU over the data bus when the send ready state signal is active.

Specifically, the transmission buffer 122 (for example, DXR [31:0 ]) has a word length parameter XWDLEN =0, 1, 2, 3, 4, or 5, and the number of significant bits of the data word in DXR is 8, 12, 16, 20, 24, or 32 bits, respectively. Sending a ready state signal XRDY controls the updating of DXR. DXR may receive new data when XRDY =1 (active). When the CPU writes data into DXR through the data bus, XRDY is set to 0 (invalid); when data in DXR is copied to XSR, XRDY is set to 1. The updating function of DXR controlled by sending the ready state signal XRDY is realized.

In one embodiment, send interrupt unit 128 sends an interrupt signal to the CPU when the interrupt enable signal is active and the send ready state signal transitions from inactive to active; the interrupt signal is used to instruct the CPU to write new data to the transmission buffer register 122.

Specifically, when XRDY makes a 0- >1 transition, the send interrupt unit 128 may also issue an interrupt signal (which may be denoted as XINT) to the CPU to notify the CPU to write data to DXR. The send interrupt unit 128 is controlled by an interrupt enable signal (which may be noted as XINTEN). When XINTEN =1 (valid), if the ready state signal XRDY makes a 0 — >1 transition, an interrupt signal XINT is issued to the CPU, thereby completing accurate notification of writing data to DXR.

In one embodiment, transmit shift register 124 copies data in transmit buffer register 122 and flips the transmit ready status signal and the word transmit complete signal if transmit control circuitry 126 allows copying of data in transmit buffer register 122 while the word transmit complete signal is active and the transmit ready status signal is inactive.

Specifically, a Transmit Shift register 124 (taking XSR [31:0] as an example) is used to hold the data currently being transmitted (shifted), controlled by a Ready to Send status signal XRDY and a word Transmit complete signal XWDONE. When XWDONE =1 (valid) (transmission of the current data word is completed by the transmission control circuit 126) and XRDY =0 (invalid) (newly written data exists in DXR), if the transmission control circuit 126 allows the data in DXR to be copied to XSR (i.e., channel enable), the XRDY is set to 1 and XWDONE is set to 0 while copying the data, so that the data copy from DXR to XSR is efficiently realized.

In one embodiment, as shown in FIG. 2, the transmit control circuitry 126 includes a transmit word counter 1261, a transmit shift counter 1263, and a mask control unit 1265. The transmission word counter 1261 is connected to the transmission shift register 124, and the transmission shift counter 1263 is connected to the transmission shift register 124 and the mask control unit 1265, respectively. The mask control unit 1265 is used to determine whether the data shifted out of the transmit shift register 124 is present in the data output signal. Transmit word counter 1261 is used to frame-length count the data shifted out of transmit shift register 124. The transmission shift counter 1263 is used to count the word length of the data shifted out by the transmission shift register 124.

It will be appreciated that the transmit control circuit 126 is responsible for shifting the data in XSR onto the output signal DX. Transmit control circuitry 126 may include a transmit word counter 1261 (which may be written as a word count XWCNT, e.g., XWCNT [6:0 ]), a transmit shift counter 1263 (which may be written as a shift count XBCNT, e.g., XBCNT [4:0 ]), and a mask control unit 1265. XWCNT and XBCNT are controlled by a frame length parameter XWNUM and a word length parameter XWDLEN, respectively. If the data in XSR allows a shift out bit by bit (i.e., channel enable), then the count of XBCNT is incremented from 0 to XWDLEN-1 to indicate that a word is sent; the count of XWCNT increases from 0 to XWNUM-1 indicating that one frame transmission is complete. The XBCNT and XWCNT continue to count to maintain the internal state while the corresponding channel is disabled or masked.

The mask control unit 1265 determines whether the shifted data is present on the data output signal DX, if the corresponding channel is not disabled or masked, the shifted data is present on the data output signal DX, otherwise the state of DX is high impedance (disabled) or high level (masked).

The data shift and transmission control are efficiently realized by the transmission control circuit 126 described above.

In one embodiment, as shown in fig. 2, the shift sequence of the transmission control circuit 126 is sequentially shifted from high to low, and the transmission control circuit 126 generates a transmission clock and a frame synchronization signal at the same time of the first-bit data transmission of the first channel of each frame when shifting the data in the transmission shift register 124 to the data output signal.

Specifically, the transmission control circuit 126 is responsible for shifting the data in XSR to the output signal DX according to the msb (most Significant bit) principle, i.e., sequentially shifting from high to low. The transmission control circuit 126 simultaneously generates the transmission clock CLKX and the transmission frame synchronization signal FSX. CLKX has the same frequency and phase as the system operating clock SYSCLK. A frame synchronization signal FSX is generated to indicate the start of a new data frame at the same time as the first bit of data on the first lane of each frame is transmitted. The frame sync signal FSX is maintained at the high level for one CLKX clock period. The active time of a bit of data on the data output signal DX is also one CLKX clock cycle.

The transmit control circuit 126 will also generate a word transmit complete signal XWDONE. Each time a word is transmitted, a high pulse (XWDONE = 1) is generated on signal XWDONE, indicating that the data in DXR can be copied to XSR for the next word transmission.

By the data shift control, the data transmission of each word and frame can be efficiently and accurately completed.

In one embodiment, the reception shift register 142 holds the data input from the data input signal under the shift control of the reception control circuit 144 after the externally input frame synchronization signal is asserted.

Specifically, receive shift register 142 (exemplified by RSR [31:0 ]) is used to hold the data currently being received (shifted). When the high-level pulse signal (active) on the externally input frame synchronization signal FSR comes, the reception control circuit 144 shifts the data of the data input signal DR to RSR.

In one embodiment, as shown in FIG. 3, receive control circuitry 144 includes a receive word counter 1441 and a receive shift counter 1443. A receive word counter 1441 and a receive shift counter 1443 are connected to the receive shift register 142, respectively. Receive word counter 1441 is used for frame length counting of data received by receive shift register 142, and receive shift counter 1443 is used for word length counting of data received by receive shift register 142.

It is to be understood that the reception control circuit 144 is responsible for shifting the data of the data input signal DR into RSR when a high-level pulse signal on the externally input frame synchronization signal FSR comes. Receive control circuitry 144 may include a receive word counter 1441 (which may be referred to as word count RWCN, e.g., RWCN [6:0 ]) and a receive shift counter 1443 (which may be referred to as shift count RBCNT, e.g., RBCNT [4:0 ]). RWCNT and RBCNT are controlled by a frame length parameter RWMUM and a word length parameter RWDLEN, respectively. The count of RBCNT increases from 0 to RWDLEN-1 indicating that one word reception is complete; the increase of the RWCNT count from 0 to RWMUM-1 indicates that one frame reception is complete. The RBCNT and RWCNT continue to count to maintain internal state while the corresponding channel is disabled or masked.

The data shift and reception control are efficiently realized by the reception control circuit 144 described above.

In one embodiment, the shift sequence of the receive control circuit 144 is sequentially high to low, and the receive control circuit 144 asserts the word receive complete signal each time a word is received.

Specifically, the receive control circuit 144 generates a high level pulse (RWDONE =1, indicating that the signal is valid) on the word receive complete signal RWDONE every time a word is received, and if the current channel is enabled and not masked, indicating that the data in RSR can be copied to RBR. By the data shift control, the data reception of each word and frame can be efficiently and accurately completed.

In one embodiment, receive backup register 146 copies the data in receive shift register 142 for backup if the channel is enabled and not masked when the word receive done signal is active.

Specifically, receive backup register 146 (e.g., RBR [31:0 ]) is responsible for backing up the data in the RSR. If the current channel is enabled and not masked, the data in the RSR is copied to the RBR when the word receive done signal RWDONE is active.

In one embodiment, the receive buffer 148 receives the data of the receive backup register 146 and toggles the receive completion status signal when the receive completion status signal is inactive.

It will be appreciated that the receive buffer register 148 (exemplified by DRR [31:0 ]) is used to store the data word to be read. When the word length parameter RWDLEN =0, 1, 2, 3, 4, or 5, the number of significant bits of the data word in the DRR is 8, 12, 16, 20, 24, or 32 bits, respectively. The reception completion status signal RRDY controls the update of the DRR.

Specifically, when RRDY =0 (invalid), the DRR may receive data from the RBR. When receiving data, RRDY is set to 1 (effective); when the CPU reads data from the DRR through the data bus, RRDY is set to 0. The updating function of controlling the DRR by receiving the completion status signal RRDY is realized.

In one embodiment, when the interrupt enable signal is enabled, if the receiving completion status signal is toggled from disabled to enabled, the receiving interrupt unit 149 sends an interrupt signal to the CPU; the interrupt signal is used to instruct the CPU to read new data from the receive buffer register 148.

It will be appreciated that the receive interrupt unit 149 may notify the CPU to read new data from the DRR via an interrupt signal (which may be denoted as RINT), controlled by an interrupt enable signal (which may be denoted as RINTEN). Specifically, when RINTEN =1, if RRDY makes a 0 — >1 transition, the reception interrupt circuit may simultaneously issue a reception interrupt signal RINT to the CPU to notify the CPU to read data from the DDR, thereby completing accurate notification of data read from the DDR.

In an embodiment, referring to fig. 4 and 5, there is further provided a serial data transmission method applied to the serial data transmission circuit, the method including the following data transmission processing steps:

s12, resetting the sending buffer register, sending shift register and sending control circuit, setting the interrupt enable signal, word length parameter, frame length parameter, sending mode parameter and channel mode parameter of the sending end;

s14, when the ready state signal jumps from invalid to valid, the sending interrupt unit sends an interrupt signal to the CPU, and the sending buffer register stores the data written by the CPU through the system bus;

s16, when the ready-to-send status signal is invalid and the word-send completion signal is valid, if the channel is enabled, copying the data in the send buffer register to the send shift register, and turning the ready-to-send status signal to valid, and turning the word-send completion signal to invalid;

s18, if the channel is enabled, the sending control circuit shifts the data in the sending shift register to the data output signal according to the MSB principle; the first bit data of the first channel of each frame is transmitted and simultaneously generates a frame synchronizing signal, the word transmission completion signal is turned into valid after each shift is completed by one data word, and if the channel is not forbidden or unshielded, the data shifted out according to the bit appears on the data output signal.

It can be understood that, regarding the specific description and limitation of each related term in the serial data transmission method of the present embodiment, the same reason and limitation of the serial data transmission circuit 100 can be referred to, and are not repeated herein.

Specifically, as shown in fig. 5, the work flow of the data transmission part can be divided into 5 parts: initialization, data writing, data copying, shift control, and mask control. Wherein, the initialization: resetting a sending buffer register DXR, a sending shift register XSR, a sending word counter XWCNT and a sending shift counter XBCNT of a sending end; an interrupt enable signal XINTEN (such as an initial value) of the sending terminal is set, a word length parameter XWDLEN (a specific assignment can be selected according to a word length required in an actual application scene), a frame length parameter XWNUM (a specific assignment can be selected according to a frame length required in an actual application scene), a sending mode parameter XMODE and a channel mode parameter XCM (can be set according to a selected sending mode).

Data writing: when the send ready state signal XRDY =1 (active), the send buffer register DXR may receive new data. The send interrupt circuit may also issue a send interrupt signal XINT to the CPU to notify the CPU to write data to DXR via the data bus when XRDY makes a 0- >1 transition. And after receiving the interrupt notification, the CPU writes new data into the DXR. New data is written while the status signal XRDY is set to 0 (inactive).

Data copying: when the transmit ready state signal XRDY =0 (i.e., the transmit buffer DXR has newly written data) and the word transmit complete signal XWDONE =1 (valid indicating that the transmit control circuit has completed transmitting the current data word), the data in the transmit buffer DXR is copied to the transmit shift register XSR if the corresponding channel is enabled, and the transmit ready state signal XRDY is set to 1 and the word transmit complete signal XWDONE is set to 0 (invalid indicating that the transmit control circuit has not completed transmitting the current data word) at the same time during copying.

And (3) displacement control: if the corresponding channel is enabled, the transmission control circuit shifts the data in the transmission shift register XSR to the output signal DX according to the principle of MSB. When the first bit data of the first channel of each frame is transmitted, a high level pulse is generated on the frame synchronization signal FSX to indicate the beginning of a frame.

The transmission shift counter XBCNT increases from 0 to XWDLEN-1 indicating that a word transmission is complete; the increment of the transmit word counter XWCNT from 0 to XWNUM-1 indicates the completion of a frame transmission. When the corresponding channel is disabled or masked, XBCNT, XWCNT still continue to count to maintain the internal state.

Each time the transmit shift completes a data word, a high pulse is generated on XWDONE, indicating that the data in transmit buffer DXR can be copied to transmit shift register XSR to begin the next word shift control if the next lane is enabled.

Shielding control: if the corresponding channel is not disabled or masked, the data shifted out by bit in shift control appears on the output signal DX, otherwise the state of DX is high impedance (disabled) or high level (masked).

In the serial data transmission method, by applying the serial data transmission circuit 100, at the transmitting end, after the transmitting interrupt unit instructs the CPU to write new data to be transmitted into the transmitting buffer register, the written data can be directly copied into the transmitting shift register as the data to be transmitted currently when the channel is enabled, and the transmitting control circuit shifts the data in the transmitting shift register to the data output signal, that is, the data can be transmitted to the outside through the data output signal. The data transmission rate is high, multiple working modes can be supported, and the data transmission rate and flexibility are effectively considered.

In one embodiment, referring to fig. 6 and fig. 7, the serial data transmission method may further include the following data reception processing steps:

s11, resetting the receiving shift register, receiving backup register, receiving buffer register and receiving control circuit, setting the interrupt enable signal, word length parameter, frame length parameter, receiving mode parameter and channel mode parameter of the receiving end;

s13, when the frame synchronization signal inputted from outside is valid, the receiving control circuit shifts the data of the data input signal to the receiving shift register according to the bit; wherein, the receiving control circuit sets the word receiving completion signal as valid when receiving one word;

s15, if the current channel is enabled and not shielded, copying the data in the receiving shift register to the receiving backup register when the word receiving completion signal is valid;

s17, when the receiving completion status signal is invalid, copying the data in the receiving backup register to the receiving buffer register and turning the receiving completion status signal to be valid;

s19, when the interrupt enable signal is effective, if the receiving completion state signal jumps from invalid to effective, the receiving interrupt unit sends the interrupt signal to the CPU; the interrupt signal is used to instruct the CPU to read new data from the reception buffer register and to invert the reception completion status signal to be invalid.

It should be understood that, regarding the specific description and limitation of each related term in the serial data transmission method of the present embodiment, the same principle as the corresponding description and limitation of the serial data transmission circuit 100 in the foregoing can be referred to for understanding, and no further description is provided herein.

Specifically, as shown in fig. 7, the work flow of the data receiving part can also be divided into 5 parts: initialization, reception control, data backup, data buffering and data reading. Wherein, the initialization: the receiving shift register RSR, receiving backup register RBR, receiving buffer register DRR, receiving word counter RWCNT and receiving shift counter RBCNT of the receiving end are reset. An interrupt enable signal RINTEN (such as an initial value) of the receiving end, a word length parameter RWDLEN (specific assignment can be selected according to the word length of the transmitting end), a frame length parameter RWNUM (specific assignment can be selected according to the frame length of the transmitting end), a receiving mode parameter RMODE, and a channel mode parameter RCM (can be set according to a selected receiving mode) are set.

Optionally, the parameters RWDLEN, RWNUM, RMODE, and RCM at the receiving end correspond to the parameters XWDLEN, XWNUM, XMODE, and XCM at the sending end, respectively, and are the same, so as to ensure that data can be received efficiently and correctly.

Receiving and controlling: when the frame synchronization signal FSR inputted from the outside is valid, the reception control circuit starts to shift the data of the data input signal DR to the reception shift register RSR. The increment of the receive shift counter RBCNT from 0 to RWDEN-1 indicates the completion of one word reception. The increment of the received word counter RWCNT from 0 to RWNUM-1 indicates that one frame reception is completed. The RBCNT and RWCNT continue to count to maintain internal state while the corresponding channel is disabled or masked.

Each time a word is received, a high level pulse is generated on the word receiving completion signal RWDONE, and if the current channel is enabled and not masked, it indicates that the data in the receiving shift register RSR can be copied to the receiving backup register RBR.

Data backup: if the current channel is enabled and not masked, the data in the receiving shift register RSR is copied to the receiving backup register RBR when the word receive done signal RWDONE is active.

Data buffering: when the reception completion status signal RRDY =0 indicates that the reception buffer register DRR can receive new data, and the reception backup register RBR has the latest data, the data in the RBR is copied to the DRR, and the signal RRDY is set to 1.

Data reading: when the reception completion status signal RRDY =1, it indicates that there is new data in the reception buffer DRR. When RRDY makes a 0- >1 transition, the receive interrupt circuit can also send a send interrupt signal RINT to the CPU to inform the CPU to read the data in DRR via the data bus. And the CPU reads the data in the DRR after receiving the interrupt notification, and simultaneously sets a state signal RRDY to 0.

Through the steps, when a data input signal is sent from the outside at a receiving end, the receiving control circuit can shift the data on the data input signal to the receiving shift register for storage according to the received frame synchronization signal, then copy and back up the data through the receiving backup register, so that the data from the receiving backup register is received as new data to be read after the stored data in the receiving buffer register is read, and then the receiving interrupt unit informs the CPU to continue to read the new data from the buffer register.

In some embodiments, in order to more intuitively and fully describe the serial data transmission circuit and method, some specific application examples are provided below. It should be noted that the application examples given in this specification are only illustrative and are not the only limitations of the specific implementation examples of the present invention, and those skilled in the art can implement time division multiplexing serial data transmission for different application scenarios by using the serial data transmission circuit and method provided above in the illustration of the implementation examples provided in the present invention.

Figures 8-10 give examples of data transmission with the mode enabled and not masked, the mode masked and disabled, and the mode enabled and maskable, and so on for the data reception process. In FIGS. 8 to 10, the y-th bit of the x-th word is represented by WxBy, and the 0-th bit of the 0-th word is represented by W0B 0.

Fig. 8 gives an example of data transmission in the enabled and unshielded mode. Wherein, some parameters are set as follows: interrupt enable signal XINTEN =1 on the initiator side, word length parameter XWDLEN =0 (8 bits), frame length parameter XWNUM =0 (16), and transmission mode parameter XMODE = 0. Under this mode, 0~15 of passageway enable and do not shield, and 16 periods of passageway are all occupied and have the valid data to send.

Fig. 9 gives an example of data transmission in the mask and inhibit mode. Wherein, some parameters are set as follows: the interrupt enable signal XINTEN =1 at the initiator, the word length parameter XWDLEN =0 (8 bits), the frame length parameter XWNUM =0 (16), the transmit mode parameter XMODE =1, and the channel mode parameter XCM =0x0FF 0F. In the mode, the channels 0-3 and the channels 8-15 are enabled and not shielded, and the corresponding time periods are occupied and valid data are sent; the channels 4-7 are forbidden and shielded, the corresponding time period is released for other equipment to send data, and the data output DX signal state is high-impedance.

Fig. 10 gives an example of data transmission in the enabled and maskable mode. Wherein, some parameters are set as follows: the interrupt enable signal XINTEN =1 at the initiator, the word length parameter XWDLEN =0 (8 bits), the frame length parameter XWNUM =0 (16), the transmit mode parameter XMODE =2, and the channel mode parameter XCM =0x0FF 0F. In the mode, the channels 0-3 and the channels 8-15 are enabled and not shielded, and the corresponding time periods are occupied and valid data are sent; the channels 4-7 are enabled but shielded, the corresponding time period is occupied but no valid data is sent (data is invalidated), and the data output DX signal state is high.

It should be understood that although the steps in the flowcharts of fig. 4-7 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps of fig. 4-7 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performing the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above examples only express several embodiments of the present application, and the description thereof is more specific and detailed, but not to be construed as limiting the scope of the invention. It should be noted that, for those skilled in the art, various changes and modifications can be made without departing from the spirit of the present application, and all of them fall within the scope of the present application. Therefore, the protection scope of the present patent should be subject to the appended claims.

Claims

1. A serial data transmission circuit is characterized by comprising a sending end circuit and a receiving end circuit, wherein the sending end circuit comprises a sending buffer register, a sending shift register, a sending control circuit and a sending interrupt unit;

the sending buffer register and the receiving buffer register are respectively used for being connected to a CPU through data buses, and the sending shift register is respectively connected with the sending buffer register, the sending control circuit and the sending interrupt unit; the receiving shift register is connected with the receiving control circuit, and the receiving backup register is respectively connected with the receiving shift register, the receiving buffer register and the receiving interrupt unit;

after the sending interrupt unit instructs the CPU to write new data to be sent into the sending buffer register, the written data to be sent is copied into the sending shift register to be used as the current data to be sent when a channel is enabled, and the sending control circuit shifts the data in the sending shift register to a data output signal according to the displacement;

the receiving shift register is used for storing currently received data, when a transmitted data input signal exists outside, the receiving control circuit shifts the data on the data input signal to the receiving shift register according to a received frame synchronization signal for storage, the receiving backup register is used for backing up the data in the receiving shift register, the receiving buffer register is used for storing data words to be read, and the receiving interrupt unit is used for indicating the CPU to read new data from the receiving buffer register.

2. The serial data transmission circuit according to claim 1, wherein the transmission control circuit comprises a transmission word counter, a transmission shift counter and a mask control unit, the transmission word counter is connected to the transmission shift register, and the transmission shift counter is connected to the transmission shift register and the mask control unit, respectively;

the shielding control unit is used for determining whether the data shifted out from the sending shift register appears in the data output signal, the sending word counter is used for counting the frame length of the data shifted out from the sending shift register, and the sending shift counter is used for counting the word length of the data shifted out from the sending shift register.

3. The serial data transmission circuit of claim 1, wherein the receive control circuit comprises a receive word counter and a receive shift counter, the receive word counter and the receive shift counter being respectively connected to the receive shift register;

the receiving word counter is used for counting the frame length of the data received by the receiving shift register, and the receiving shift counter is used for counting the word length of the data received by the receiving shift register.

4. The serial data transmission circuit according to claim 1 or 2, wherein when the send-ready state signal is invalid and the word send complete signal is valid, if the send control circuit allows copying of data in the send buffer register, the send data word to be sent is copied to the send shift register and the send-ready state signal and the word send complete signal are inverted;

and when the sending ready state signal is effective, the sending buffer register receives and stores the data word to be sent, which is written by the CPU through a data bus.

5. The serial data transmission circuit according to claim 4, wherein the transmission interrupt unit transmits an interrupt signal to the CPU when an interrupt enable signal is active and the transmission ready state signal transitions from inactive to active; the interrupt signal is used for instructing the CPU to write new data into the sending buffer register.

6. The serial data transmission circuit according to claim 4, wherein the transmission control circuit shifts the data in the transmission shift register in order from high to low, generates a transmission clock and generates a frame synchronization signal simultaneously with the first bit data transmission of the first lane of each frame when shifting the data in the transmission shift register to the data output signal.

7. The serial data transmission circuit according to claim 1 or 3, wherein the reception shift register holds the data input from the data input signal under shift control of the reception control circuit after the externally input frame synchronization signal is asserted.

8. The serial data transmission circuit of claim 7, wherein the shift sequence of the reception control circuit is sequentially shifted from high to low, and the reception control circuit asserts the word reception completion signal every time a word is received.

9. The serial data transmission circuit of claim 7, wherein the receive backup register copies data in the receive shift register for backup if lane enable and unmask when a word receive complete signal is active.

10. The serial data transmission circuit of claim 7, wherein the receive buffer register receives the data of the receive backup register and inverts the receive completion status signal when the receive completion status signal is inactive.

11. The serial data transmission circuit of claim 7, wherein the reception interrupt unit sends an interrupt signal to the CPU if the reception completion status signal transitions from invalid to valid when the interrupt enable signal is valid; the interrupt signal is used to instruct the CPU to read new data from the receive buffer register.

12. A serial data transmission method applied to the serial data transmission circuit according to any one of claims 1 to 11, the method comprising:

when the sending ready state signal jumps from invalid to valid, the sending interruption unit sends an interruption signal to the CPU, and the sending buffer register stores data written by the CPU through a system bus;

when the sending ready state signal is invalid and the word sending completion signal is valid, if the channel is enabled, copying the data in the sending buffer register to the sending shift register, turning the sending ready state signal to be valid, and turning the word sending completion signal to be invalid;

if the channel is enabled, the sending control circuit shifts the data in the sending shift register to a data output signal according to the MSB principle; the first bit data of the first channel of each frame is transmitted and simultaneously generates a frame synchronization signal, the word transmission completion signal is turned into valid after each shift is completed by one data word, and if the channel is not forbidden or unmasked, the data shifted out according to the bit appears on the data output signal.

13. The serial data transmission method according to claim 12, characterized in that the method further comprises the step of:

resetting the receiving shift register, the receiving backup register, the receiving buffer register and the receiving control circuit, and setting an interrupt enable signal, a word length parameter, a frame length parameter, a receiving mode parameter and a channel mode parameter of a receiving end;

when the frame synchronization signal input from the outside is valid, the receiving control circuit shifts the data of the data input signal to the receiving shift register according to the bit; wherein, the receiving control circuit sets the word receiving completion signal to be effective when receiving one word;

if the current channel is enabled and not shielded, copying the data in the receiving shift register to the receiving backup register when the word receiving completion signal is valid;

when the receiving completion status signal is invalid, copying the data in the receiving backup register into the receiving buffer register and turning the receiving completion status signal to be valid;

when the interrupt enable signal is effective, if the receiving completion state signal jumps from invalid to effective, the receiving interrupt unit sends an interrupt signal to the CPU; the interrupt signal is used for instructing the CPU to read new data from the receiving buffer register and turning the receiving completion status signal to be invalid.