CN114780460B - DMA controller and method - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 230000005540 biological transmission Effects 0.000 claims abstract description 47
- 239000000872 buffer Substances 0.000 claims abstract description 23
- 230000003139 buffering effect Effects 0.000 claims abstract description 7
- 125000004122 cyclic group Chemical group 0.000 claims description 31
- 238000004364 calculation method Methods 0.000 claims description 20
- 230000001351 cycling effect Effects 0.000 claims description 4
- 230000002085 persistent effect Effects 0.000 claims description 4
- 230000002045 lasting effect Effects 0.000 claims description 2
- 210000005036 nerve Anatomy 0.000 description 8
- 238000013528 artificial neural network Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000013500 data storage Methods 0.000 description 2
- 238000003062 neural network model Methods 0.000 description 2
- 230000002688 persistence Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 1
- 210000002569 neuron Anatomy 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
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Abstract
The embodiment of the invention discloses a DMA controller and a method, wherein the controller comprises the following steps: the system comprises a control state register, a read controller and a data buffer register, wherein the control state register is used for storing a control instruction corresponding to a preset transmission mode; the read controller reads multidimensional data from an external storage unit according to the control instruction; the data buffer register is used for buffering the multidimensional data once, and the read controller sends the multidimensional data to the memory once after the multidimensional data buffering is completed. Through the technical scheme of the embodiment, the DMA controller can be configured once, the multidimensional data can be completely stored, and the access efficiency of the multidimensional data is improved.
Description
Technical Field
The embodiment of the invention relates to the field of DMA (Direct Memory Access ) data transmission, in particular to a DMA controller and a method.
Background
A DMA controller is a device for data transfer between a CPU and an external device inside a computer system, and by means of the DMA controller, a high-speed data transfer between an internal memory and an external memory of the computer system can be performed. In the prior art, when the DMA controller controls the internal memory and the external memory to perform data transmission, the continuous data transmission of the address can be performed, and the data address of the multidimensional data is discontinuous, so that the DMA controller in the prior art needs to start the DMA controller for transmitting the multidimensional data for a plurality of times, and a large amount of time is consumed for starting and interrupting the DMA controller each time, and the CPU resource is occupied for controlling the starting and stopping of the DMA controller, thereby the data transmission performance is reduced, the data transmission efficiency is too low, and the requirement of the multidimensional data in nerve calculation cannot be met.
Disclosure of Invention
The embodiment of the invention provides a DMA controller and a method, which can improve the efficiency and performance of multidimensional data transmission.
In a first aspect, embodiments of the present invention provide a DMA controller comprising a control status register, a read controller, a data buffer register,
The control state register is used for storing a control instruction corresponding to a preset transmission mode;
The read controller is used for reading multidimensional data from an external storage unit according to the control instruction;
The data buffer register is used for buffering the multidimensional data once, and the read controller sends the multidimensional data to the memory once after the multidimensional data buffering is completed.
In a second aspect, an embodiment of the present invention further provides a DMA control method, including:
controlling a read controller to read multidimensional data from an external storage unit according to a control instruction;
One-time caching the multidimensional data into the data buffer register;
And after the multidimensional data is cached, the multidimensional data is sent to the memory through the read controller at one time.
According to the DMA controller provided by the embodiment of the invention, the control instruction corresponding to the preset transmission mode sent by the CPU is stored by the control state register, the read controller reads the multidimensional data from the external storage unit according to the control instruction, the multidimensional data is cached in the data cache register at one time, the multidimensional data is sent to the memory at one time by the read controller after the multidimensional data is cached, the multidimensional data is completely read by the control state register, the multidimensional data is read once only by one control instruction, the technical problem that the DMA controller needs to be started and interrupted for many times when the multidimensional data is read by the DMA controller in the prior art is solved, the data transmission performance is improved, the efficient data transmission is realized, and the requirement on the multidimensional data in nerve calculation is met.
Drawings
FIG. 1 is a schematic diagram of a DMA controller according to a first embodiment of the present invention;
Fig. 2 is a schematic diagram of a three-dimensional data block structure according to a second embodiment of the present invention;
fig. 3 is a flow chart of a DMA control method according to a third embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof.
It should be further noted that, for convenience of description, only some, but not all of the matters related to the present invention are shown in the accompanying drawings. Before discussing exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart depicts operations (or steps) as a sequential process, many of the operations can be performed in parallel, concurrently, or at the same time. Furthermore, the order of the operations may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.
The terms first and second and the like in the description and in the claims and drawings of embodiments of the invention are used for distinguishing between different objects and not necessarily for describing a particular sequential or chronological order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to the listed steps or elements but may include steps or elements not expressly listed.
Example 1
Fig. 1 is a schematic diagram of a DMA controller according to a first embodiment of the present invention, which is applicable to a data transmission case and is generally integrated in a computer, as shown in fig. 1:
Specifically, the DMA controller may include: a control status register 110 (Control Status Register, CSR), a read controller 120 (read control), a data buffer register 130 (date buffer), wherein:
the control status register 110 is used for storing a control instruction corresponding to a preset transmission mode.
The preset transmission mode may be a transmission mode preset according to multidimensional data transmitted by the DMA controller. The control instruction may be an instruction that the CPU transmits the multidimensional data to the DMA controller through the bus, and it is understood that the DMA controller obtains the data address and the transmission direction of the multidimensional data according to the instruction transmitted by the CPU.
In the embodiment of the invention, the control state register stores the control instruction corresponding to the preset transmission mode, that is to say, the DMA controller comprises a multidimensional data address, a transmission direction and the control instruction of the preset transmission mode, and then stores the acquired control instruction, wherein the multidimensional data can be three-dimensional data, and the three-dimensional data can be a large amount of picture data used in neural network calculation; the transmission direction may be from SRAM (Static Random-Access Memory) to DDR (Double Data Rate).
The read controller 120 is used to read the multi-dimensional data from the external memory unit according to the control instruction.
The external storage unit may be a storage unit that stores multidimensional data outside the system.
In the embodiment of the invention, the read controller acquires the data address of the multidimensional data storage and the transmission direction of the multidimensional data from the control instruction, reads the multidimensional data according to the data address of the multidimensional data storage and transmits the multidimensional data according to the transmission direction of the multidimensional data.
The data buffer register 130 is configured to buffer the multidimensional data at a time, and the read controller sends the multidimensional data to the memory at a time after the multidimensional data buffering is completed.
In the embodiment of the invention, the data buffer register receives the multidimensional data read by the read controller, buffers the received multidimensional data once, and sends the multidimensional data to the memory once after the multidimensional data is buffered. Optionally, a read path is jointly constructed through the data buffer register and the read controller, and then the multidimensional data is read according to the data address of the multidimensional data through the read path persistence, and the read multidimensional data is transmitted according to the target address persistence in the data transmission direction.
Optionally, the DMA controller further comprises: a write controller 140, wherein the read controller acquires the multidimensional data from the data buffer register at one time according to the control instruction; and the read control sequentially writes the multidimensional data into an external storage unit after acquiring the multidimensional data, and is used for finishing the persistent storage of the multidimensional data.
In the embodiment of the invention, the read controller acquires the multidimensional data from the data buffer register at one time according to the control instruction, and sequentially writes the multidimensional data into the external storage unit, thereby completing the persistent storage of the multidimensional data. Optionally, the read controller may form a write path with the data buffer register, and continuously transmit the multidimensional data to the external storage unit according to the target address of the external storage unit in the data transmission direction, so as to complete the persistent storage of the multidimensional data.
Optionally, the DMA controller further comprises: the main controller is used for receiving control signals of the preset transmission modes provided by the external CPU and storing the control signals of the preset transmission modes in the control state register, the preset transmission modes are determined by the external CPU according to a preset calculation model, and the control instructions are generated by the external CPU according to the preset transmission modes.
The preset calculation model may be a neural network calculation model, and it is understood that the neural network model is a complex network system formed by interconnecting a large number of neurons, and the neural network model needs to input corresponding calculation data during calculation, so as to determine corresponding input data according to the neural network calculation model.
In the embodiment of the invention, a CPU determines a preset transmission mode according to calculation data required by calculation of a neural network calculation model, generates a corresponding control instruction, and sends the control instruction to a DMA controller through a bus, and the bus between the CPU of the main controller and the DMA controller receives the control instruction of the preset transmission mode sent by the CPU and stores a control signal of the preset transmission mode in the control state register.
Optionally, the read controller sends the multidimensional data to the memory once after the multidimensional data is cached, and then is further used for the main controller to generate an interrupt signal and send the interrupt signal to the CPU.
According to the DMA controller provided by the embodiment of the invention, the control instruction corresponding to the preset transmission mode sent by the CPU is stored by the control state register, the read controller reads the multidimensional data from the external storage unit according to the control instruction, the multidimensional data is cached in the data cache register at one time, the multidimensional data is sent to the memory at one time by the read controller after the multidimensional data is cached, the multidimensional data is completely read by the control state register, the multidimensional data is read once only by one control instruction, the technical problem that the DMA controller needs to be started and interrupted for many times when the multidimensional data is read by the DMA controller in the prior art is solved, the data transmission performance is improved, the efficient data transmission is realized, and the requirement on the multidimensional data in nerve calculation is met.
Example two
The present embodiment is embodied based on the foregoing embodiment, and further describes a control instruction of a preset transmission mode including multidimensional data in the DMA controller in the foregoing embodiment, where the control instruction at least includes: a reference address, a first cyclic offset, a first cyclic upper limit, and a second cyclic upper limit for the multidimensional data, wherein:
The reference address of the multi-dimensional data may be a data address storing the multi-dimensional data; the first cycle upper limit may be an upper limit number of the first cycle read multidimensional data number; the second cycle upper limit may be an upper limit number of the second cycle read multidimensional data number; the first loop offset may be an offset of the reference address after the end of the first loop reading.
Step one, the reference address of the multidimensional data is read by the read controller to read the first cyclic upper limit multidimensional data.
Specifically, the read controller reads the reference address to the first cycle upper limit multi-dimensional data stored at the first cycle upper limit data address according to the reference address of the multi-dimensional data.
And step two, after the read controller reads the first cyclic upper limit multi-dimensional data, updating the reference address of the multi-dimensional data according to the reference address of the multi-dimensional data and the first cyclic offset.
Specifically, after the read controller reads the first cyclic upper limit multi-dimensional data, the read controller updates the reference address of the multi-dimensional data according to the reference address of the multi-dimensional data and the first cyclic offset, and generates the updated reference address of the multi-dimensional data.
And thirdly, the read controller reads the first cycle upper limit multi-dimensional data according to the updated multi-dimensional data reference address until the second cycle upper limit multi-dimensional data is read.
Specifically, the read controller reads the updated reference address to the first cycle upper limit multi-dimensional data stored by the first cycle upper limit data address according to the updated reference address of the multi-dimensional data, and then continues to update the reference address of the multi-dimensional data again according to the first cycle offset until the second cycle upper limit multi-dimensional data is read.
Further, the control instruction further includes: a second cyclic offset and a third cyclic upper limit; the third cycle upper limit may be an upper limit number of the third cycle read multidimensional data number; the second loop offset may be an offset of the reference address after the second loop read ends.
And step four, after the read controller finishes reading the second cyclic upper limit multi-dimensional data, updating the reference address of the multi-dimensional data according to the reference address of the multi-dimensional data and the second cyclic offset.
Specifically, after the second cycle upper limit multi-dimensional data is read, the read controller updates the reference address of the multi-dimensional data according to the reference address of the multi-dimensional data and the second cycle offset, and generates the updated reference address of the multi-dimensional data.
And fifthly, the read controller reads a first cyclic upper limit of the multidimensional data according to the updated reference address of the multidimensional data, and then updates the reference address of the multidimensional data again according to the updated reference address of the multidimensional data and the first cyclic offset.
Specifically, the read controller reads the updated reference address to the first cycle upper limit multi-dimensional data stored in the first cycle upper limit data address according to the updated reference address of the multi-dimensional data, and then continues to update the reference address of the multi-dimensional data again according to the first cycle offset.
And step six, the read controller reads the first cycle upper limit multi-dimensional data according to the reference address of the multi-dimensional data updated again until the second cycle upper limit multi-dimensional data is read.
And sequentially cycling until the read controller reads the third cycle upper limit multidimensional data.
In the embodiment of the invention, the read controller circularly reads the multidimensional data through the steps one to six until all the multidimensional data are read.
Exemplary: fig. 2 discloses a schematic structure of a three-dimensional data block, as shown in fig. 2: in the calculation process of some nerve convolution models, only a part of three-dimensional data in the original three-dimensional data block, such as a smaller three-dimensional data block h ' w ' c ' in the illustration, is needed to be used for each calculation, so that the original three-dimensional data block is split into a plurality of identical three-dimensional data blocks h ' w ' c ', when an external CPU executes an interrupt instruction for data reading, the external CPU can continuously read one three-dimensional data block h ' w ' c ' at a time, and the read three-dimensional data block h ' w ' c ' is provided to a memory for one calculation of the nerve convolution model, thereby avoiding the need of occupying CPU resources to control the starting and stopping of a DMA controller to read one complete three-dimensional data block h ' w ' c ' for a plurality of times when the nerve convolution model performs one calculation.
In the following embodiments, taking the reading of a smaller three-dimensional data block H 'W' c 'as an example, the first upper cycle limit may be W', the second upper cycle limit may be H ', the third upper cycle limit may be c', the reference address of the multidimensional data may be BA, the first cycle offset may be W, the first cycle offset may be w×h, assuming that BA is 0, the flow of the multidimensional data reading may be as follows:
step one, w 'data stored at addresses 0 to w' -1 are read by using ba=0 as a base address.
Step two, updating the base address BA, ba=0+s1= 0+W =w.
Step three, W 'data stored in the addresses W to w+w' -1 are read, and the base address BA is continuously updated (ba=ba+s1=w+w=w), and W 'data stored in the addresses W to w+w' -1 are read; and the like, finishing reading the h' row of data.
Step four, updating the base address BA (ba=0+s2=0+w×h=w×h).
Step five, reading the data of addresses w×h-w×h+w' -1, updating the base address BA (ba=ba+s1=w×h+s1=w×h+w).
Step six, reading addresses w×h+w to w×h+w' -1 data
Similarly, reading of the data block h ' w ' c ' is completed.
According to the DMA controller provided by the embodiment of the invention, the control instruction corresponding to the preset transmission mode sent by the CPU is stored by the control state register, and then the read controller reads the multidimensional data from the external storage unit according to the control instruction, further, the controller caches the data in the data buffer register by circularly reading the multidimensional data, the read controller sends the multidimensional data to the memory once after caching the multidimensional data, the control of the read controller by the control state register realizes the complete reading of the multidimensional data, and the technical problem that the DMA controller needs to be started and interrupted for many times when the DMA controller reads the multidimensional data in the prior art is solved, so that the data transmission performance is improved, the efficient data transmission is realized, and the requirement on the multidimensional data in nerve calculation is met.
Embodiment III:
Fig. 3 is a schematic diagram of a DMA control method according to a third embodiment of the present invention, where the DMA control data transmission is applicable, the method may be executed by a DMA controller, and may be generally integrated in a computing device. As shown in fig. 3, the method comprises the steps of:
S210, controlling the read controller to read the multidimensional data from the external storage unit according to the control instruction.
S220, caching the multidimensional data into the data buffer register at one time;
and S230, after the multidimensional data is cached, the multidimensional data is sent to a memory through the read controller at one time.
Optionally, the method further comprises:
controlling the write controller to acquire the multidimensional data from the data buffer register at one time according to a control instruction;
and after the multidimensional data are acquired, the multidimensional data are sequentially written into an external storage unit through the write controller, so that the lasting storage of the multidimensional data is completed.
Optionally, the control instruction includes at least a reference address of the multidimensional data, a first loop offset, a first loop upper limit, and a second loop upper limit, and the method further includes controlling the read controller to read the multidimensional data from the external storage unit according to the control instruction:
reading a first cycle upper limit of the multidimensional data according to the reference address of the multidimensional data;
after the first cyclic upper limit multi-dimensional data are read, updating the reference address of the multi-dimensional data according to the reference address of the multi-dimensional data and the first cyclic offset;
And reading the first cycle upper limit multi-dimensional data according to the updated reference address of the multi-dimensional data until the second cycle upper limit multi-dimensional data is read.
Further, the control instruction further includes a second loop offset and a third loop upper limit, and the control unit is configured to control the read controller to read the multidimensional data from the external storage unit according to the control instruction, and further includes:
After the second cycle upper limit multi-dimensional data is read, updating the reference address of the multi-dimensional data according to the reference address of the multi-dimensional data and the second cycle offset;
reading a first cyclic upper limit of the multidimensional data according to the updated reference address of the multidimensional data, and updating the reference address of the multidimensional data again according to the updated reference address of the multidimensional data and the first cyclic offset;
Reading the first cycle upper limit multi-dimensional data according to the reference address of the multi-dimensional data updated again until the second cycle upper limit multi-dimensional data is read; and sequentially cycling until the read controller reads the third cycle upper limit multidimensional data.
According to the DMA controller provided by the embodiment of the invention, the control instruction corresponding to the preset transmission mode sent by the CPU is stored by the control state register, the read controller reads the multidimensional data from the external storage unit according to the control instruction, the multidimensional data is cached in the data cache register at one time, the multidimensional data is sent to the memory at one time by the read controller after the multidimensional data is cached, the multidimensional data is completely read by the control state register, the multidimensional data is read once only by one control instruction, the technical problem that the DMA controller needs to be started and interrupted for many times when the multidimensional data is read by the DMA controller in the prior art is solved, the data transmission performance is improved, the efficient data transmission is realized, and the requirement on the multidimensional data in nerve calculation is met.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (6)
1. A DMA controller comprises a control status register, a read controller and a data buffer register,
The control state register is used for storing a control instruction corresponding to a preset transmission mode;
The read controller is used for reading multidimensional data from an external storage unit according to the control instruction;
The data buffer register is used for buffering the multidimensional data once, and the read controller is used for transmitting the multidimensional data to the memory once after the multidimensional data buffering is completed;
The control instruction at least comprises a reference address of the multi-dimensional data, a first cyclic offset, a first cyclic upper limit and a second cyclic upper limit, and the read controller reads the first cyclic upper limit multi-dimensional data according to the reference address of the multi-dimensional data;
After the read controller reads the multi-dimensional data with the first cycle upper limit, updating the reference address of the multi-dimensional data according to the reference address of the multi-dimensional data and the first cycle offset;
The read controller reads the first cycle upper limit multi-dimensional data according to the updated multi-dimensional data reference address until the second cycle upper limit multi-dimensional data is read;
the control instruction further includes a second loop offset and a third loop upper limit,
After the second cycle upper limit multi-dimensional data is read, the read controller updates the reference address of the multi-dimensional data according to the reference address of the multi-dimensional data and the second cycle offset;
The read controller reads a first cyclic upper limit of the multi-dimensional data according to the updated multi-dimensional data reference address, and then updates the multi-dimensional data reference address again according to the updated multi-dimensional data reference address and the first cyclic offset;
The read controller reads the first cycle upper limit multi-dimensional data according to the reference address of the multi-dimensional data updated again until the second cycle upper limit multi-dimensional data is read; and sequentially cycling until the read controller reads the third cycle upper limit multidimensional data.
2. The DMA controller of claim 1, further comprising: the write controller is configured to control the write operations,
The write controller acquires the multidimensional data from the data buffer register at one time according to the control instruction;
The write controller sequentially writes the multidimensional data into an external storage unit after acquiring the multidimensional data, and is used for completing the persistent storage of the multidimensional data.
3. The DMA controller according to claim 1, further comprising a main controller,
The main controller is used for receiving a control signal of the preset transmission mode provided by the external CPU, storing the control signal of the preset transmission mode in the control state register, wherein the preset transmission mode is determined by the external CPU according to a preset calculation model, and the control instruction is generated by the external CPU according to the preset transmission mode.
4. A DMA controller according to claim 3, wherein the read controller is configured to send the multi-dimensional data to the memory once after the multi-dimensional data is buffered, and then further configured to generate an interrupt signal by the main controller and send the interrupt signal to the CPU.
5. A DMA control method, characterized by comprising:
controlling a read controller to read multidimensional data from an external storage unit according to a control instruction;
Caching the multidimensional data into a data buffer register at one time;
after the multidimensional data is cached, the multidimensional data is sent to a memory through the read controller at one time;
the control instruction at least comprises a reference address of the multidimensional data, a first cyclic offset, a first cyclic upper limit and a second cyclic upper limit, and the control instruction is used for controlling a read controller to read the multidimensional data from an external storage unit, and the control instruction comprises the following steps:
reading a first cycle upper limit of the multidimensional data according to the reference address of the multidimensional data;
after the first cyclic upper limit multi-dimensional data are read, updating the reference address of the multi-dimensional data according to the reference address of the multi-dimensional data and the first cyclic offset;
Reading the first cycle upper limit multi-dimensional data according to the updated reference address of the multi-dimensional data until the second cycle upper limit multi-dimensional data is read;
The control instruction further includes a second loop offset and a third loop upper limit, and the control unit is configured to control the read controller to read the multidimensional data from the external storage unit according to the control instruction, and further includes:
After the second cycle upper limit multi-dimensional data is read, updating the reference address of the multi-dimensional data according to the reference address of the multi-dimensional data and the second cycle offset;
reading a first cyclic upper limit of the multidimensional data according to the updated reference address of the multidimensional data, and updating the reference address of the multidimensional data again according to the updated reference address of the multidimensional data and the first cyclic offset;
Reading the first cycle upper limit multi-dimensional data according to the reference address of the multi-dimensional data updated again until the second cycle upper limit multi-dimensional data is read; and sequentially cycling until the read controller reads the third cycle upper limit multidimensional data.
6. The method according to claim 5, comprising:
Controlling a write controller to acquire the multidimensional data from the data buffer register at one time according to the control instruction;
and after the multidimensional data are acquired, the multidimensional data are sequentially written into an external storage unit through the write controller, so that the lasting storage of the multidimensional data is completed.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101266585A (en) * | 2008-03-24 | 2008-09-17 | 北京中星微电子有限公司 | Direct storage access controller data-transmission system and method |
| CN101986287A (en) * | 2010-11-25 | 2011-03-16 | 中国人民解放军国防科学技术大学 | Reform buffer for vector data streams |
| CN111126589A (en) * | 2019-12-31 | 2020-05-08 | 北京百度网讯科技有限公司 | Neural network data processing device and method and electronic equipment |
| CN113900974A (en) * | 2021-12-07 | 2022-01-07 | 睿思芯科(深圳)技术有限公司 | Storage device, data storage method and related equipment |
-
2022
- 2022-04-20 CN CN202210416816.7A patent/CN114780460B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101266585A (en) * | 2008-03-24 | 2008-09-17 | 北京中星微电子有限公司 | Direct storage access controller data-transmission system and method |
| CN101986287A (en) * | 2010-11-25 | 2011-03-16 | 中国人民解放军国防科学技术大学 | Reform buffer for vector data streams |
| CN111126589A (en) * | 2019-12-31 | 2020-05-08 | 北京百度网讯科技有限公司 | Neural network data processing device and method and electronic equipment |
| CN113900974A (en) * | 2021-12-07 | 2022-01-07 | 睿思芯科(深圳)技术有限公司 | Storage device, data storage method and related equipment |
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