CN114780283B - Fault processing method and device - Google Patents
Fault processing method and device Download PDFInfo
- Publication number
- CN114780283B CN114780283B CN202210698612.7A CN202210698612A CN114780283B CN 114780283 B CN114780283 B CN 114780283B CN 202210698612 A CN202210698612 A CN 202210698612A CN 114780283 B CN114780283 B CN 114780283B
- Authority
- CN
- China
- Prior art keywords
- fault
- data
- register
- specified
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0793—Remedial or corrective actions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
The present specification discloses a method and an apparatus for fault handling, wherein the method for fault handling comprises: if it is monitored that the equipment has the specified fault, register data corresponding to a specified register in a CPU of the core processor of the equipment and request table data are obtained, a fault source corresponding to the specified fault is determined according to the register data and is used as a first fault source, a fault source corresponding to the specified fault is determined according to the request table data and is used as a second fault source, a fault source which actually fails is determined according to the first fault source and the second fault source and is used as a target fault source, and fault processing is carried out on the equipment according to the target fault source.
Description
Technical Field
The present disclosure relates to the field of fault handling, and in particular, to a method and an apparatus for fault handling.
Background
In the process of operation and maintenance of equipment, for example, a server deployed in a data center room, because the load is high and needs to be kept running for a long time, various faults occur inevitably in the server in such a high-load running mode, and once a fault occurs, the server cannot continue to provide services for services.
In general, 30% Of failures result from a Request Table Timeout (TOR Timeout) error, and when a server fails, it is necessary to find a corresponding failure source and perform corresponding processing, so that the server can recover to normal operation.
However, in the currently adopted method, once it is detected that the TOR Timeout has failed, a Core Processor (CPU) that may have the failure is immediately found and replaced, and if the TOR Timeout of multiple CPUs has failed at the same time, the multiple CPUs are replaced at the same time, but such an operation and maintenance cost is high, and the reason for the failure may also appear in a memory bank, other serial bus (PCI express, PCIe) devices, a motherboard, and associated other CPUs, so that only replacing the CPU often cannot solve the actual problem.
Therefore, how to accurately determine the fault source of the current device with the fault and perform corresponding processing on the fault source is an urgent problem to be solved.
Disclosure of Invention
The present specification provides a method and an apparatus for fault handling, which partially solve the above problems in the prior art.
The technical scheme adopted by the specification is as follows:
the present specification provides a method of fault handling, including:
if the specified fault of the equipment is monitored, register data corresponding to a specified register in a CPU (central processing unit) of the core processor of the equipment and request table data are obtained;
determining a fault source corresponding to the specified fault as a first fault source according to the register data, and determining a fault source corresponding to the specified fault as a second fault source according to the request table data;
determining a fault source of the actual fault of the equipment as a target fault source according to the first fault source and the second fault source;
and carrying out fault processing on the equipment according to the target fault source.
Optionally, the specifying register includes: an address ADDR register, a miscellaneous MISC register;
determining a fault source corresponding to the specified fault according to the register data, wherein the determining is used as a first fault source and specifically comprises:
and if the ADDR register and the MISC register are determined to be in a normal working state, determining the first fault source according to the register data corresponding to the ADDR register and the register data corresponding to the MISC register.
Optionally, determining the first fault source according to the register data corresponding to the ADDR register and the register data corresponding to the MISC register specifically includes:
and if the first specified data contained in the register data corresponding to the ADDR register is a first specified value, determining that the input/output I/O equipment has a fault, and determining a component with the fault in the I/O equipment as a first fault source according to an Internet protocol IP address contained in the initialization data corresponding to the BIOS of the basic input/output system of the equipment.
Optionally, determining the first fault source according to the register data corresponding to the ADDR register and the register data corresponding to the MISC register specifically includes:
if the first specified data contained in the register data corresponding to the ADDR register is not the first specified value, determining a combined value of the first specified data and the second specified data in the register data corresponding to the MISC register;
and determining the first fault source according to the combined value.
Optionally, determining the first fault source according to the combination value specifically includes:
and if the combined value is the combined value recorded in the first data table, determining that the first fault source is the CPU fault.
Optionally, determining the first fault source according to the combination value specifically includes:
if the combined value is not the combined value recorded in the first data table and the equipment has a super path interconnect (UPI) fault, judging whether first specified data in register data corresponding to the MISC register is a second specified value or not and judging whether second specified data in register data corresponding to the MISC register is a third specified value or not;
if the first specified data is determined to be a second specified value and the second specified data is determined to be a third specified value, determining that the first fault source is the CPU fault;
and if the first specified data is determined not to be the second specified value and/or the second specified data is determined not to be the third specified value, determining that the first fault source is a memory fault.
Optionally, determining the first fault source according to the combination value specifically includes:
if the combined value is not the combined value recorded in the first data table and the UPI fault does not occur in the equipment, judging whether the combined value is the combined value recorded in the second data table;
if the combined value is the combined value recorded in a second data table, determining that the first fault source is the CPU fault;
and if the combined value is not the combined value recorded in the second data table, determining that the first fault source is a memory fault.
Optionally, determining, according to the request table data, a fault source corresponding to the specified fault, as a second fault source, specifically including:
determining valid data in the request table;
and determining a fault source corresponding to the target port information as the second fault source according to the target port information corresponding to the effective data in the request table.
Optionally, if it is monitored that the device has a specified fault, acquiring register data corresponding to a specified register in a CPU of a core processor of the device and request table data, specifically including:
if the priority of the specified fault is the highest among all faults occurring at the same time of the equipment, register data corresponding to a specified register in the CPU and the request table data are obtained.
Optionally, the method further comprises:
if the faults with the priority higher than the specified faults exist in other faults occurring at the same time of the equipment, determining the target fault source according to the other faults with the priority higher than the specified faults.
Optionally, determining, according to the first fault source and the second fault source, a fault source where the device actually fails, as a target fault source, specifically including:
and if the first fault source is different from the second fault source, taking the first fault source as the target fault source.
The present specification provides an apparatus for fault handling, comprising:
the device comprises an acquisition module, a processing module and a processing module, wherein the acquisition module is used for acquiring register data corresponding to a specified register in a CPU (central processing unit) of the device core processor and request table data if the specified fault of the device is monitored;
the first determining module is used for determining a fault source corresponding to the specified fault as a first fault source according to the register data, and determining a fault source corresponding to the specified fault as a second fault source according to the request table data;
the second determining module is used for determining a fault source of the actual fault of the equipment as a target fault source according to the first fault source and the second fault source;
and the processing module is used for carrying out fault processing on the equipment according to the target fault source.
The present specification provides a computer-readable storage medium storing a computer program which, when executed by a processor, implements the above-described fault handling method.
The present specification provides an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the above-mentioned fault handling method when executing the program.
The technical scheme adopted by the specification can achieve the following beneficial effects:
in the method for processing a fault provided in this specification, when it is monitored that a specified fault occurs in a device, register data corresponding to a specified register in a CPU of the device and request table data are obtained, a first fault source is determined according to the register data, a second fault source is determined according to the request table data, a target fault source where the device actually fails is determined according to the first fault source and the second fault source, and the device is processed according to the target fault source.
According to the method, after the appointed failure of the equipment is monitored, the fault source which is possible to fail is determined according to the request table data and the register data, the fault source which is actually failed of the equipment is determined according to the fault source, and corresponding fault processing is carried out.
Drawings
The accompanying drawings, which are included to provide a further understanding of the specification and are incorporated in and constitute a part of this specification, illustrate embodiments of the specification and together with the description serve to explain the specification and not to limit the specification in a non-limiting sense. In the drawings:
FIG. 1 is a schematic flow diagram of a method of fault handling provided herein;
FIG. 2 is a first data representation provided in the present specification;
FIG. 3 is a schematic diagram of a second data table provided herein;
FIG. 4 is a request presentation intent provided in the subject specification;
FIG. 5 is a schematic diagram of fault determination when multiple faults occur simultaneously according to the present disclosure;
FIG. 6 is a schematic diagram of a fault handling apparatus provided herein;
fig. 7 is a schematic diagram of an electronic device corresponding to fig. 1 provided in this specification.
Detailed Description
In order to make the objects, technical solutions and advantages of the present disclosure more clear, the technical solutions of the present disclosure will be clearly and completely described below with reference to the specific embodiments of the present disclosure and the accompanying drawings. It is to be understood that the embodiments described are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present specification without any creative effort belong to the protection scope of the present specification.
The technical solutions provided by the embodiments of the present description are described in detail below with reference to the accompanying drawings.
Fig. 1 is a schematic flow chart of a method for fault handling provided in this specification, including the following steps:
s101: and if the equipment is monitored to have the specified fault, acquiring register data corresponding to the specified register in the CPU of the core processor of the equipment and requesting table data.
During the operation of the server, data synchronization is performed with units such as an Integrated I/O Controller (IIO), a Core Unit Core, and an Ultra Path Interconnect (UPI) in a request form, so as to complete data consistency check between different cores and different Core Processors (CPUs). The IIO is used to connect the CPU with a serial device (such as a video card, a sound card, a network card, etc.), and the Core is a Core processing unit of the CPU, and usually, at least one Core is provided in one CPU, and the UPI is used to implement mutual communication of data between the CPU and the CPU.
When any one Of the units has an error, the Request in the Request Table is not responded within a specified time, so that a Table Of timeout (TOR timeout) fault occurs, and the CPU stops operating. Therefore, when a TOR timeout fault occurs in a device, a fault source (such as a serial device fault, other CPU faults, a CPU fault, a motherboard fault, etc.) of the fault needs to be found, so as to perform processing according to the fault source to recover the device to operate.
Based on this, the present specification provides a method for handling a fault, where if it is detected that a specified fault (i.e., TOR timeout fault) occurs in a device, a server needs to obtain register data corresponding to a specified register in a CPU and request table data.
When a device fails, a Machine Check Architecture (MCA) of the device is triggered first, then a programmable logic device (CPLD) arranged on a motherboard of the device stores detected hardware information in a corresponding register, and then a server may acquire register information of the CPU through a Platform Environment Control Interface (PCIe).
Therefore, in practical applications, whether the fault occurred is the specified fault can be determined through a Status register in the CPU, where the Status register is used to store the fault type of the fault occurred in the device and information about whether other registers in the CPU are valid, and when the value of the 16 th to 31 th bytes (i.e., bit [31 ] of the Status register is 0x0C, it indicates that the fault occurred in the device is a TOR timeout fault.
When the TOR timeout fault of the device is determined, register data corresponding to a designated register in the CPU and request table data may be obtained, where the designated register includes an Address register (ADDR) for storing device system Address data and Address data corresponding to each component, a Miscellaneous register (MISC) for storing supplementary data such as state machine data and interrupt request data, and the like. The request table data will be described in detail below, and will not be described in detail herein.
It should be noted that before determining that the TOR timeout fault occurs in the device, it is further required to determine whether the Status register is valid (that is, whether the 63 rd bit byte of the Status register is 1), and if the bit63 of the Status register is not 1, it is determined that the Status register is invalid, and then it is required to determine a fault source occurring in the fault through other registers.
In this specification, the failed device may refer to a server, or may be a specific device such as a notebook computer, a desktop computer, a mobile phone, and the like, which is not specifically limited in this specification.
In addition, the main execution body for implementing the fault processing method in the present specification may be a Baseboard Management Controller (BMC) provided in the device, or may be a server, and for convenience of description, the present specification describes a fault processing method provided in the present specification, by taking the server as the main execution body.
S102: and determining a fault source corresponding to the specified fault as a first fault source according to the register data, and determining a fault source corresponding to the specified fault as a second fault source according to the request table data.
After the server obtains the register data corresponding to the ADDR register and the register data corresponding to the MISC register, the server may determine a fault source corresponding to the specified fault (i.e., TOR timeout fault) according to the register data, and use the fault source as the first fault source.
Specifically, the server needs to first determine whether the ADDR register and the MISC register are both in a normal operating state, where when the 58 th bit of the Status register is set to 1 (i.e., bit [58] = 1), it indicates that the ADDR register is valid (i.e., in the normal operating state), and when the 59 th bit of the Status register is set to 1 (i.e., bit [59] = 1), it indicates that the MISC register is valid.
After determining that all the designated registers are valid, the server may further determine whether first designated data included in the register data corresponding to the ADDR register is a first designated value, and in practical applications, data corresponding to bytes 45 th to 55 th of the MISC register (i.e., bit [ 55.
When the data value of the ORIGERO data (first specific data) is 0x1D5 or 0x1DC (i.e., the first specific value), it indicates that the address data included in the register data corresponding to the ADDR register is the address data corresponding to the I/O Device, and further, the fault source address (e.g., bus, device, function) BDF) may be determined according to the internet protocol IP address included in the initialization data corresponding to the Basic Input Output System (BIOS) of the Device. The server may then determine the failed component of the I/O device based on the failure source address and treat the component as the first failure source. When the component that has failed is a Platform Controller Hub (PCH) on the motherboard, the corresponding motherboard is replaced, and if the PCIe component fails, the corresponding PCIe component may be replaced.
When the data value of the origo data (first specifying data) is not 0x1D5 or 0x1DC, the server may determine a combination value of the first specifying data (origo data) and the second specifying data (FSM data) in the register data corresponding to the MISC register, determine a fault source corresponding to the specified fault from the combination value, and set the fault source as the first fault source.
From analyzing a large amount of actual fault data, it can be known that when the above-mentioned combination value is in the first data table shown in fig. 2, it can be stated that the first fault source is a CPU fault.
Fig. 2 is a first data representation intent provided in this specification.
In fig. 2, the data in each row represents a combination of ORIGERO data and FSM data, and when the combination determined by the server is the combination recorded in the first data table, the first failure source is a CPU failure.
When the combination value determined by the server is the combination value recorded in the first data table, it indicates that the first failure source may not be a CPU failure, so it needs to be further determined.
Therefore, in this case, the server may first determine whether the UPI fault still occurs in the device, and if the UPI fault occurs, since the UPI is used for data communication between the CPU and the CPU, once the UPI fault occurs, the fault source of the fault is likely to be the CPU fault or other CPU faults associated with the CPU, and of course, may also be a fault of a memory device (such as a memory bank) connected to the fault source.
Specifically, the server may first determine whether a value of a Status register corresponding to the UPI of the device is 0, if the value of the Status register corresponding to the UPI is 0, it indicates that the register is invalid, and if the value of the Status register corresponding to the UPI is 1, it indicates that the register is valid, and at this time, no UPI fault occurs.
After determining that the UPI fault occurs in the device, the server may determine whether the first specified data (ORIGERO data) in the register data corresponding to the MISC register is the second specified value, and determine whether the second specified data (FSM data) in the register data corresponding to the MISC register is the third specified value, to determine whether the first fault source is the CPU itself, and from analyzing a large amount of actual fault data, when ORIGREQ =0x200/0x202 (i.e., the second specified value) and FSM =0x02/0x03 (i.e., the third specified value) are simultaneously satisfied, the first fault source is the CPU itself, and at this time, the fault may be handled by replacing the CPU.
When ORIGREQ =0x200/0x202 and FSM =0x02/0x03 are not satisfied at the same time, it is described that the first failure source is not the CPU itself but a memory device connected thereto, and at this time, the memory device having the failure may be determined by corresponding address data in the address register.
If the device is not located in the first data table and no UPI failure occurs, the server may further determine whether the combined value of the ORIGERO data and the FSM data is in the second data table shown in fig. 3.
Fig. 3 is a schematic diagram of a second data table provided in the present specification.
The table is used for judging that the precondition of the first fault source is that the equipment has no UPI fault, and the analysis can be carried out according to a large amount of actual fault data to obtain that when the equipment has no UPI fault and the combination value is the combination value recorded in the second data table, the first fault source is the CPU fault, the corresponding CPU can be replaced at the moment, and when the combination value is not the combination value recorded in the second data table, the first fault source is not the CPU and is the corresponding memory equipment, and the memory equipment with the fault can be determined through the corresponding address data in the address register at the moment.
Therefore, a first fault source corresponding to the TOR timeout can be determined. It should be noted that, the second data table is different from the first data table in determining the precondition of the failure source, and only when the UPI failure does not occur in the device and the combination value is not the combination value recorded in the first data table, the failure source is determined according to the second data table.
In addition, the server may also determine a failure source corresponding to the specified failure (i.e., TOR timeout failure) as a second failure source according to the acquired request table data. The flow direction of data is stored in the request table, so that a component with a fault can be judged according to the flow direction of the data, in addition, the request table can be stored in a CPLD of the device in advance, and when the TOR timeout is determined to occur and the Status register is valid, the BMC deployed in the server can acquire the request table data stored in the CPLD through the PECI channel.
Specifically, when the server determines that the Status register is valid and the TOR timeout has failed, the server may determine valid data in the request table according to the obtained request table, and then determine a fault source corresponding to the target port information according to target port information corresponding to the valid data in the request table, as the second fault source. The request table is shown in fig. 4.
Fig. 4 is a request presentation intent provided in this specification.
The Valid data in the row is Valid data when Valid =1, the row of data is invalid data when Valid =0, retry is a Retry, slice _ Number is a Slice Number, TOR _ Entry _ Number is a request table Number, address is a component Address, FSM _ State is a State corresponding to a State machine, target _ Port is Target Port information, when data corresponding to Target _ Port is IMC, the second failure source is a memory device, when data corresponding to Target _ Port is PCI, the second failure source is a PCIe device, and when data corresponding to Target _ Port is KTI, the second failure source is a motherboard or another CPU associated with the CPU. As can be seen from fig. 4, the target port information corresponding to the valid data is IMC, which indicates that the second failure source is a memory device.
Of course, in this specification, the destination port information may also be directed to other units such as UPI, IIO, and the like, which is not specifically limited in this specification.
In addition, the server may determine the failure source where the device actually fails through the two manners, or may determine the failure source where the device actually fails according to the first failure source and the second failure source by combining the two manners.
S103: and determining a fault source of the actual fault of the equipment as a target fault source according to the first fault source and the second fault source.
After the server determines the first fault source and the second fault source, a target fault source where the device actually fails may be determined according to the first fault source and the second fault source.
Specifically, when the server determines that the first failure source is the same as the second failure source, it indicates that the first failure source and the second failure source are target failure sources where the device actually fails.
When the first fault source and the second fault source determined by the server are different, the fault source determined by the register data is more accurate than the fault source determined by the request table, so that the server can use the first fault source as a target fault source of the actual fault of the equipment. Of course, the server may also use the second failure source as a target failure source for the actual failure of the device.
In the actual operation process of the device, other faults are likely to occur while the specified fault (TOR timeout) occurs, and when some other faults occur, the fault certainly causes the TOR timeout to fail, and the fault source where the fault occurs can be directly judged through the other faults.
And if the priority of the specified fault is monitored to be lower than the priority of other faults which occur simultaneously in the equipment, determining a target fault source according to other faults of which the priority is higher than the TOR timeout fault.
In practical applications, other faults that usually occur in a device include: the method includes three times of striking a timeout 3-strike timeout fault, a Platform Environment Control Interface (PECI) 0x91 fault, a PECI0x81 fault, a memory Uce or CE fault, a Power Control Unit (PCU) fault, a Data Cache Unit (DCU) fault, and the like.
When the TOR timeout fault and other faults occur simultaneously in the device, the server may determine a fault source corresponding to a fault with the highest priority according to the priority corresponding to each fault, and use the fault source as a target fault source.
When the device has a PECI0x81 fault (the PECI0x81 represents that the return code is 0x81 when the CPU is accessed through the PECI channel, and the return code represents an access failure), the target fault source can be directly judged to be the CPU fault, and at this time, which CPU has a PECI return 0x81 is judged to be faulty.
When memory Uce or CE faults occur in a register related to the memory, the target fault source can be directly judged to be the memory fault.
When there is a PCU failure, it is described that a power supply control unit inside the CPU has failed, and at this time, it may also be directly determined that the target failure source is a CPU failure.
When the return value of the secondary Cache (MLC) is 0x0040, it indicates that the secondary Cache of the CPU fails at this time, and at this time, it may also directly determine that the target failure source is a CPU failure. The method for determining the fault is to check whether the value of the 16 th byte to the 31 th byte (i.e. bit [31 ] of the Status register corresponding to the MLC is 0x0040.
When the DCU has a Posion fault, the target fault source can be directly judged to be a memory fault, and at the moment, the memory device with the fault can be determined according to the address data pointed by the ADDR register corresponding to the DCU.
When the UPI of the device has a Uce fault, it may be continuously determined whether register data corresponding to the MISC register satisfies origarq =0x200/0x202+ fsm =0x01/0x02/0x03, if so, it may be determined that the target fault source is a CPU fault, and if not, it may determine the memory device having the fault according to address data pointed by the ADDR register.
When the device has a 3-strike timeout fault, it indicates that sending a data from the CPU core unit to the non-core unit is not completed within a specified time, or the data is not completed within a specified time when looking up in the first-level cache or the second-level cache, when the TOR timeout fault occurs, the 3-strike timeout must also be generated, so when the two faults occur simultaneously, the nature of the fault can be considered to be the TOR timeout fault, and the target fault source can be determined by the first fault source and the second fault source.
When the device has the PECI0x91 fault, the data is relatively reliable in general, so that the data can be analyzed as normal data, the nature of the fault can be considered to be a TOR timeout fault, and the server can determine a target fault source through the first fault source and the second fault source.
Based on this, it can be determined that the priority corresponding to the MLC0x0040 fault, the PECI0x81 fault, the memory voltage Uce or CE fault, the PCU fault, the version fault of the DCU, and the Uce fault of the UPI are all higher than the priority corresponding to the TOR timeout fault, and the priority corresponding to the 3-strike timeout fault and the PECI0x91 fault are lower than the priority corresponding to the TOR timeout fault.
For the convenience of understanding, the specification also provides a fault determination schematic diagram when multiple faults occur simultaneously.
Fig. 5 is a schematic diagram of fault determination when multiple faults occur simultaneously according to the present disclosure.
When multiple faults including a TOR timeout fault occur in the equipment, the server can determine whether a PECI0x81 fault occurs or not, if so, the target fault source is judged to be a CPU fault, if not, the server continues to judge whether a Uce or CE fault occurs or not, if not, the server continues to judge whether a PCU fault occurs or not, if so, the server determines that the CPU fault occurs or not, if not, the server continues to judge whether an MLC0x0040 fault occurs or not, if so, the server determines that the CPU fault occurs or not, if not, the server continues to judge whether a DCUPUPUPIUce fault occurs or not, if not, the server determines that the final target fault source is the target fault source according to a determination method for determining the target fault source when only the TOR timeout fault occurs or not, and if the DCUPOSI fault does not occur or not, the server determines that the final target fault source is the target fault source according to the determination method for determining the target fault source when only the TOR timeout fault occurs.
The method for determining the fault source is only described in a few representative fault types, and other fault types may also be included in practical applications, and are not listed here.
S104: and carrying out fault processing on the equipment according to the target fault source.
After the target failure source where the device actually fails is determined, the server may perform corresponding failure processing according to the target failure source, for example, when it is determined that the target failure source is a CPU failure, only the failed CPU may be replaced at this time, and when the target failure source is a memory failure, the server may resolve address data corresponding to the failed memory device into a physical address (i.e., determine which memory device actually failed), and then replace the memory device.
According to the method, after the appointed failure of the equipment is monitored, the fault source which is possible to fail is determined according to the request table data and the register data, the fault source which is actually failed of the equipment is determined according to the fault source, and corresponding fault processing is carried out.
In addition, when the server monitors that the priority of other faults occurring at the same time is higher than the priority corresponding to the specified fault, the server can directly determine the corresponding fault source according to the other faults, and the efficiency of fault source determination and fault processing is further improved.
Based on the same idea, the present specification also provides a corresponding fault handling apparatus, as shown in fig. 6.
Fig. 6 is a schematic diagram of a fault handling apparatus provided in the present specification, including:
an obtaining module 601, configured to obtain register data corresponding to a specified register in a CPU of a core processor of a device and request table data if it is monitored that the device has a specified fault;
a first determining module 602, configured to determine, according to the register data, a fault source corresponding to the specified fault as a first fault source, and determine, according to the request table data, a fault source corresponding to the specified fault as a second fault source;
a second determining module 603, configured to determine, according to the first fault source and the second fault source, a fault source where the device actually fails, as a target fault source;
the processing module 604 performs fault processing on the device according to the target fault source.
Optionally, the specifying register includes: an address ADDR register, a miscellaneous MISC register;
the first determining module 602 is specifically configured to, if it is determined that the ADDR register and the MISC register are in a normal operating state, determine the first fault source according to the register data corresponding to the ADDR register and the register data corresponding to the MISC register.
Optionally, the first determining module 602 is specifically configured to determine that an input or output I/O device fails if first specified data included in register data corresponding to the ADDR register is a first specified value, and determine, according to an internet protocol IP address included in initialization data corresponding to the BIOS of the device, a component in the I/O device that fails, as a first failure source.
Optionally, the first determining module 602 is specifically configured to determine, if first specified data included in the register data corresponding to the ADDR register is not the first specified value, a combined value of the first specified data and the second specified data in the register data corresponding to the MISC register; and determining the first fault source according to the combined value.
Optionally, the first determining module 602 is specifically configured to determine that the first failure source is the CPU failure if the combined value is a combined value recorded in a first data table.
Optionally, the first determining module 602 is specifically configured to, if the combined value is not a combined value recorded in the first data table and the apparatus has a failure of a super path interconnect UPI, determine whether first specified data in register data corresponding to the MISC register is a second specified value, and determine whether second specified data in register data corresponding to the MISC register is a third specified value; if the first specified data is determined to be a second specified value and the second specified data is determined to be a third specified value, determining that the first fault source is the CPU fault; and if the first specified data is determined not to be the second specified value and/or the second specified data is determined not to be the third specified value, determining that the first fault source is a memory fault.
Optionally, the first determining module 602 is specifically configured to, if the combined value is not a combined value recorded in a first data table, and the UPI fault does not occur in the device, determine whether the combined value is a combined value recorded in a second data table; if the combined value is the combined value recorded in a second data table, determining that the first fault source is the CPU fault; and if the combined value is not the combined value recorded in the second data table, determining that the first fault source is a memory fault.
Optionally, the first determining module 602 is specifically configured to determine valid data in the request table; and determining a fault source corresponding to the target port information as the second fault source according to the target port information corresponding to the valid data in the request table.
Optionally, the obtaining module 601 is specifically configured to, if it is monitored that the priority of the specified fault is highest among all faults occurring at the same time in the device, obtain register data corresponding to a specified register in the CPU and the request table data.
Optionally, the obtaining module 601 is further configured to determine the target fault source according to other faults having a priority higher than the specified fault if it is monitored that a fault having a priority higher than the specified fault exists among other faults occurring at the same time in the device.
Optionally, the second determining module 603 is specifically configured to, if the first failure source is different from the second failure source, use the first failure source as the target failure source.
The present specification also provides a computer-readable storage medium having stored thereon a computer program operable to execute a method of fault handling as provided above with respect to fig. 1.
This specification also provides a schematic block diagram of an electronic device corresponding to fig. 1 shown in fig. 7. As shown in fig. 7, at the hardware level, the electronic device includes a processor, an internal bus, a network interface, a memory, and a non-volatile memory, but may also include hardware required for other services. The processor reads the corresponding computer program from the non-volatile memory into the memory and then runs the computer program to implement the method for processing the fault as described in fig. 1. Of course, besides the software implementation, the present specification does not exclude other implementations, such as logic devices or a combination of software and hardware, and the like, that is, the execution subject of the following processing flow is not limited to each logic unit, and may be hardware or logic devices.
In the 90's of the 20 th century, improvements to a technology could clearly distinguish between improvements in hardware (e.g., improvements to circuit structures such as diodes, transistors, switches, etc.) and improvements in software (improvements to process flow). However, as technology advances, many of today's process flow improvements have been seen as direct improvements in hardware circuit architecture. Designers almost always obtain the corresponding hardware circuit structure by programming an improved method flow into the hardware circuit. Thus, it cannot be said that an improvement in the process flow cannot be realized by hardware physical blocks. For example, a Programmable Logic Device (PLD), such as a Field Programmable Gate Array (FPGA), is an integrated circuit whose Logic functions are determined by programming the Device by a user. A digital system is "integrated" on a PLD by the designer's own programming without requiring the chip manufacturer to design and fabricate application-specific integrated circuit chips. Furthermore, nowadays, instead of manually manufacturing an Integrated Circuit chip, such Programming is often implemented by "logic compiler" software, which is similar to a software compiler used in program development, but the original code before compiling is also written in a specific Programming Language, which is called Hardware Description Language (HDL), and the HDL is not only one kind but many kinds, such as abll (Advanced boot Expression Language), AHDL (alternate hard Description Language), traffic, CUPL (computer universal Programming Language), HDCal (Java hard Description Language), lava, lola, HDL, PALASM, software, rhydl (Hardware Description Language), and vhul-Language (vhyg-Language), which is currently used in the field. It will also be apparent to those skilled in the art that hardware circuitry for implementing the logical method flows can be readily obtained by a mere need to program the method flows with some of the hardware description languages described above and into an integrated circuit.
The controller may be implemented in any suitable manner, for example, the controller may take the form of, for example, a microprocessor or processor and a computer-readable medium storing computer-readable program code (e.g., software or firmware) executable by the (micro) processor, logic gates, switches, an Application Specific Integrated Circuit (ASIC), a programmable logic controller, and an embedded microcontroller, examples of which include, but are not limited to, the following microcontrollers: ARC 625D, atmel AT91SAM, microchip PIC18F26K20, and Silicone Labs C8051F320, the memory controller may also be implemented as part of the control logic for the memory. Those skilled in the art will also appreciate that, in addition to implementing the controller as pure computer readable program code, the same functionality can be implemented by logically programming method steps such that the controller is in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Such a controller may thus be regarded as a hardware component and the means for performing the various functions included therein may also be regarded as structures within the hardware component. Or even means for performing the functions may be regarded as being both a software module for performing the method and a structure within a hardware component.
The systems, devices, modules or units illustrated in the above embodiments may be implemented by a computer chip or an entity, or by a product with certain functions. One typical implementation device is a computer. In particular, the computer may be, for example, a personal computer, a laptop computer, a cellular telephone, a camera phone, a smartphone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.
For convenience of description, the above devices are described as being divided into various units by function, and are described separately. Of course, the functions of the various elements may be implemented in the same one or more software and/or hardware implementations of the present description.
As will be appreciated by one skilled in the art, embodiments of the present description may be provided as a method, system, or computer program product. Accordingly, the description may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the description may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The description has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the description. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include forms of volatile memory in a computer readable medium, random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium.
Computer-readable media, including both permanent and non-permanent, removable and non-removable media, may implement the information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Disks (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising one of 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises that element.
As will be appreciated by one skilled in the art, embodiments of the present description may be provided as a method, system, or computer program product. Accordingly, the description may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the description may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and so forth) having computer-usable program code embodied therein.
This description may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.
All the embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
The above description is only an example of the present specification, and is not intended to limit the present specification. Various modifications and alterations to this description will become apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present specification should be included in the scope of the claims of the present specification.
Claims (13)
1. A method of fault handling, comprising:
if the specified fault of the equipment is monitored, register data corresponding to a specified register in a CPU (central processing unit) of the core processor of the equipment and request table data are obtained;
a component that determines a fault source corresponding to the specified fault as a first fault source according to the register data, determines valid data in the request table, determines a fault source corresponding to the target port information as a second fault source according to target port information corresponding to the valid data in the request table, wherein the request table stores a data flow direction, and the data flow direction is used for judging that a fault occurs;
determining a fault source of the actual fault of the equipment as a target fault source according to the first fault source and the second fault source;
and carrying out fault processing on the equipment according to the target fault source.
2. The method of claim 1, wherein the specifying the register comprises: address ADDR register, miscellaneous MISC register;
determining a fault source corresponding to the specified fault according to the register data, wherein the determining is used as a first fault source and specifically comprises:
and if the ADDR register and the MISC register are determined to be in a normal working state, determining the first fault source according to the register data corresponding to the ADDR register and the register data corresponding to the MISC register.
3. The method of claim 2, wherein determining the first fault source based on the register data corresponding to the ADDR register and the register data corresponding to the MISC register comprises:
and if the first specified data contained in the register data corresponding to the ADDR register is a first specified value, determining that the input or output I/O equipment has a fault, and determining a component with the fault in the I/O equipment as a first fault source according to an Internet Protocol (IP) address contained in the initialization data corresponding to the basic input/output system (BIOS) of the equipment.
4. The method of claim 2, wherein determining the first fault source based on the register data corresponding to the ADDR register and the register data corresponding to the MISC register comprises:
if the first specified data contained in the register data corresponding to the ADDR register is not the first specified value, determining the combination value of the first specified data and the second specified data in the register data corresponding to the MISC register;
and determining the first fault source according to the combined value.
5. The method of claim 4, wherein determining the first failure source based on the combined value comprises:
and if the combined value is the combined value recorded in the first data table, determining that the first fault source is the CPU fault.
6. The method of claim 4, wherein determining the first failure source based on the combined value comprises:
if the combination value is not the combination value recorded in the first data table and the equipment has a super path interconnection (UPI) fault, judging whether first specified data in register data corresponding to the MISC register is a second specified value or not and judging whether second specified data in register data corresponding to the MISC register is a third specified value or not;
if the first specified data is determined to be a second specified value and the second specified data is determined to be a third specified value, determining that the first fault source is the CPU fault;
and if the first specified data is determined not to be the second specified value and/or the second specified data is determined not to be the third specified value, determining that the first fault source is a memory fault.
7. The method according to claim 4, wherein determining the first failure source based on the combined value specifically comprises:
if the combination value is not the combination value recorded in the first data table and the equipment has no UPI fault, judging whether the combination value is the combination value recorded in the second data table;
if the combined value is the combined value recorded in a second data table, determining that the first fault source is the CPU fault;
and if the combined value is not the combined value recorded in the second data table, determining that the first fault source is a memory fault.
8. The method of claim 1, wherein if it is monitored that a device has a specified failure, acquiring register data corresponding to a specified register in a CPU of a core processor of the device and requesting table data, specifically comprising:
and if the priority of the specified fault is the highest among all the faults which occur simultaneously in the equipment, acquiring register data corresponding to the specified register in the CPU and the request table data.
9. The method of claim 1, wherein the method further comprises:
if the faults with the priority higher than the specified faults exist in other faults occurring at the same time of the equipment, determining the target fault source according to the other faults with the priority higher than the specified faults.
10. The method according to claim 1, wherein determining, according to the first fault source and the second fault source, a fault source where the device actually fails, as a target fault source, specifically includes:
and if the first fault source is different from the second fault source, taking the first fault source as the target fault source.
11. An apparatus for fault handling, comprising:
the device comprises an acquisition module, a processing module and a processing module, wherein the acquisition module is used for acquiring register data corresponding to a specified register in a CPU (central processing unit) of the device and request table data if the specified fault of the device is monitored;
a first determining module, configured to determine, according to the register data, a fault source corresponding to the specified fault as a first fault source, determine valid data in the request table, and determine, according to target port information corresponding to the valid data in the request table, a fault source corresponding to the target port information as a second fault source, where a flow direction of data is stored in the request table, and the flow direction of the data is used to determine a component that generates a fault;
the second determining module is used for determining a fault source of the actual fault of the equipment as a target fault source according to the first fault source and the second fault source;
and the processing module is used for carrying out fault processing on the equipment according to the target fault source.
12. A computer-readable storage medium, characterized in that the storage medium stores a computer program which, when executed by a processor, implements the method of any of claims 1 to 10.
13. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the method of any one of claims 1 to 10 when executing the program.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210698612.7A CN114780283B (en) | 2022-06-20 | 2022-06-20 | Fault processing method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210698612.7A CN114780283B (en) | 2022-06-20 | 2022-06-20 | Fault processing method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114780283A CN114780283A (en) | 2022-07-22 |
| CN114780283B true CN114780283B (en) | 2022-11-01 |
Family
ID=82420319
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210698612.7A Active CN114780283B (en) | 2022-06-20 | 2022-06-20 | Fault processing method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114780283B (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57133598A (en) * | 1981-02-10 | 1982-08-18 | Fujitsu Ltd | System for write control of erroneous operation address |
| US6629271B1 (en) * | 1999-12-28 | 2003-09-30 | Intel Corporation | Technique for synchronizing faults in a processor having a replay system |
| CN105589776A (en) * | 2015-12-23 | 2016-05-18 | 华为技术有限公司 | Fault location method and server |
| WO2017215377A1 (en) * | 2016-06-16 | 2017-12-21 | 中兴通讯股份有限公司 | Method and device for processing hard memory error |
| CN108282383A (en) * | 2017-12-18 | 2018-07-13 | 瑞斯康达科技发展股份有限公司 | A kind of method and apparatus for realizing troubleshooting |
| CN109086193A (en) * | 2017-06-13 | 2018-12-25 | 阿里巴巴集团控股有限公司 | Monitoring method, apparatus and system |
| CN109947585A (en) * | 2019-03-13 | 2019-06-28 | 西安易朴通讯技术有限公司 | The processing method and processing device of PCIE device failure |
| CN111414268A (en) * | 2020-02-26 | 2020-07-14 | 华为技术有限公司 | Fault processing method and device and server |
| CN111625382A (en) * | 2020-05-21 | 2020-09-04 | 浪潮电子信息产业股份有限公司 | Server fault diagnosis method, device, equipment and medium |
| CN112256507A (en) * | 2020-10-22 | 2021-01-22 | 地平线(上海)人工智能技术有限公司 | Chip fault diagnosis method and device, readable storage medium and electronic equipment |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040221198A1 (en) * | 2003-04-17 | 2004-11-04 | Vecoven Frederic Louis Ghislain Gabriel | Automatic error diagnosis |
| US7340582B2 (en) * | 2004-09-30 | 2008-03-04 | Intel Corporation | Fault processing for direct memory access address translation |
| WO2012053110A1 (en) * | 2010-10-22 | 2012-04-26 | 富士通株式会社 | Fault monitoring device, fault monitoring method and program |
| JP2013061887A (en) * | 2011-09-14 | 2013-04-04 | Fujitsu Ltd | Fault position determining circuit, storage device and information processing apparatus |
| US9003223B2 (en) * | 2012-09-27 | 2015-04-07 | International Business Machines Corporation | Physical memory fault mitigation in a computing environment |
| JP2015185968A (en) * | 2014-03-24 | 2015-10-22 | 三菱電機インフォメーションネットワーク株式会社 | Failure message aggregation device and failure message aggregation program |
| CN106330501A (en) * | 2015-06-26 | 2017-01-11 | 中兴通讯股份有限公司 | Fault correlation method and device |
| CN110135604A (en) * | 2019-05-22 | 2019-08-16 | 北京秦淮数据有限公司 | Fault handling method, device and processing equipment |
| US11237928B2 (en) * | 2019-12-02 | 2022-02-01 | Advanced Micro Devices, Inc. | Method for a reliability, availability, and serviceability-conscious huge page support |
| CN112148515B (en) * | 2020-09-16 | 2023-06-20 | 锐捷网络股份有限公司 | Fault positioning method, system, device, medium and equipment |
| CN114461439A (en) * | 2022-04-13 | 2022-05-10 | 苏州浪潮智能科技有限公司 | Fault diagnosis method, device, equipment and storage medium |
-
2022
- 2022-06-20 CN CN202210698612.7A patent/CN114780283B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57133598A (en) * | 1981-02-10 | 1982-08-18 | Fujitsu Ltd | System for write control of erroneous operation address |
| US6629271B1 (en) * | 1999-12-28 | 2003-09-30 | Intel Corporation | Technique for synchronizing faults in a processor having a replay system |
| CN105589776A (en) * | 2015-12-23 | 2016-05-18 | 华为技术有限公司 | Fault location method and server |
| WO2017215377A1 (en) * | 2016-06-16 | 2017-12-21 | 中兴通讯股份有限公司 | Method and device for processing hard memory error |
| CN109086193A (en) * | 2017-06-13 | 2018-12-25 | 阿里巴巴集团控股有限公司 | Monitoring method, apparatus and system |
| CN108282383A (en) * | 2017-12-18 | 2018-07-13 | 瑞斯康达科技发展股份有限公司 | A kind of method and apparatus for realizing troubleshooting |
| CN109947585A (en) * | 2019-03-13 | 2019-06-28 | 西安易朴通讯技术有限公司 | The processing method and processing device of PCIE device failure |
| CN111414268A (en) * | 2020-02-26 | 2020-07-14 | 华为技术有限公司 | Fault processing method and device and server |
| CN111625382A (en) * | 2020-05-21 | 2020-09-04 | 浪潮电子信息产业股份有限公司 | Server fault diagnosis method, device, equipment and medium |
| CN112256507A (en) * | 2020-10-22 | 2021-01-22 | 地平线(上海)人工智能技术有限公司 | Chip fault diagnosis method and device, readable storage medium and electronic equipment |
Non-Patent Citations (3)
| Title |
|---|
| CPU小系统故障定位方法;季力等;《轻工机械》;20090630(第03期);全文 * |
| 面向崩溃预测的寄存器软错误故障传播分析;薛利兴等;《计算机工程与应用》;20171031(第20期);全文 * |
| 龙芯3号板卡HT互联及内存故障诊断方法的设计与实现;冯珂珂等;《计算机测量与控制》;20200625(第06期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114780283A (en) | 2022-07-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107239324B (en) | Service flow processing method, device and system | |
| US8769504B2 (en) | Method and apparatus for dynamically instrumenting a program | |
| CN109086193B (en) | Monitoring method, device and system | |
| US20140164827A1 (en) | Method and device for managing hardware errors in a multi-core environment | |
| US9342393B2 (en) | Early fabric error forwarding | |
| JP2007188315A (en) | Device trouble detector, control method, and program | |
| US20180239905A1 (en) | Method, checking device, and system for determining security of a processor | |
| US10133654B1 (en) | Firmware debug trace capture | |
| CN114548744A (en) | Business risk management method, device and equipment | |
| US9395992B2 (en) | Instruction swap for patching problematic instructions in a microprocessor | |
| US20110202903A1 (en) | Apparatus and method for debugging a shared library | |
| CN114780283B (en) | Fault processing method and device | |
| US9092333B2 (en) | Fault isolation with abstracted objects | |
| CN112559565A (en) | Abnormity detection method, system and device | |
| US11126486B2 (en) | Prediction of power shutdown and outage incidents | |
| KR101505258B1 (en) | Replaying architectural execution with a probeless trace capture | |
| US7617417B2 (en) | Method for reading input/output port data | |
| CN114003416B (en) | Memory error dynamic processing method, system, terminal and storage medium | |
| US8819494B2 (en) | Automatically changing parts in response to tests | |
| US11095313B2 (en) | Employing single error correction and triple error detection to optimize bandwidth and resilience under multiple bit failures | |
| CN111796864A (en) | Data verification method and device | |
| CN116743550B (en) | Processing method of fault storage nodes of distributed storage cluster | |
| CN109992510B (en) | Remote debugging device and method | |
| US20230114636A1 (en) | Systems, methods, and devices for accessing a device program on a storage device | |
| US20220229932A1 (en) | Method for performing multi-system log access management, associated system on chip integrated circuit and non-transitory computer-readable medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |